KR20020059161A - Method for forming the bit line contact in semiconductor device - Google Patents
Method for forming the bit line contact in semiconductor device Download PDFInfo
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- KR20020059161A KR20020059161A KR1020010000224A KR20010000224A KR20020059161A KR 20020059161 A KR20020059161 A KR 20020059161A KR 1020010000224 A KR1020010000224 A KR 1020010000224A KR 20010000224 A KR20010000224 A KR 20010000224A KR 20020059161 A KR20020059161 A KR 20020059161A
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- 238000000034 method Methods 0.000 title claims abstract description 45
- 239000004065 semiconductor Substances 0.000 title claims abstract description 19
- 238000005530 etching Methods 0.000 claims abstract description 53
- 239000010410 layer Substances 0.000 claims abstract description 48
- 239000011229 interlayer Substances 0.000 claims abstract description 19
- 229920002120 photoresistant polymer Polymers 0.000 claims abstract description 16
- 125000006850 spacer group Chemical group 0.000 claims abstract description 6
- 239000000758 substrate Substances 0.000 claims abstract description 6
- 238000000151 deposition Methods 0.000 claims abstract description 5
- 150000004767 nitrides Chemical class 0.000 claims description 15
- 239000007789 gas Substances 0.000 claims 10
- 239000011248 coating agent Substances 0.000 claims 1
- 238000000576 coating method Methods 0.000 claims 1
- 230000000087 stabilizing effect Effects 0.000 claims 1
- 230000015572 biosynthetic process Effects 0.000 abstract 2
- 239000002184 metal Substances 0.000 description 8
- 229910052751 metal Inorganic materials 0.000 description 8
- 239000000203 mixture Substances 0.000 description 3
- 239000002245 particle Substances 0.000 description 2
- 230000006641 stabilisation Effects 0.000 description 2
- 238000011105 stabilization Methods 0.000 description 2
- 239000006227 byproduct Substances 0.000 description 1
- 238000011109 contamination Methods 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 230000010354 integration Effects 0.000 description 1
- 239000011368 organic material Substances 0.000 description 1
- 229920000642 polymer Polymers 0.000 description 1
- 239000000047 product Substances 0.000 description 1
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B12/00—Dynamic random access memory [DRAM] devices
- H10B12/30—DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells
- H10B12/48—Data lines or contacts therefor
- H10B12/485—Bit line contacts
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3105—After-treatment
- H01L21/311—Etching the insulating layers by chemical or physical means
- H01L21/31105—Etching inorganic layers
- H01L21/31111—Etching inorganic layers by chemical means
- H01L21/31116—Etching inorganic layers by chemical means by dry-etching
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3105—After-treatment
- H01L21/311—Etching the insulating layers by chemical or physical means
- H01L21/31144—Etching the insulating layers by chemical or physical means using masks
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76897—Formation of self-aligned vias or contact plugs, i.e. involving a lithographically uncritical step
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- Microelectronics & Electronic Packaging (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
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- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
Abstract
Description
본 발명은 반도체 소자의 비트라인 콘택 형성방법에 관한 것으로, 특히, 금속 콘택 식각 공정을 두단계로 나누어 진행함에 있어서, 제 1단계에서는 절연막의 식각 특성과 감광막 마스크에 대한 선택비가 높은 조건으로 식각 정지막 전까지 식각한 후, 제 2 단계로 하드 마스크 질화막의 식각 특성이 우수한 조건으로 식각하여 콘택 형성 시 식각이 멈추는 것을 방지할 수 있는 것을 특징으로 하는 반도체 소자의 비트라인 콘택 형성방법에 관한 것이다.The present invention relates to a method for forming a bit line contact of a semiconductor device, and in particular, in the process of dividing a metal contact etching process into two steps, in the first step, the etching stop is performed under the condition that the etching characteristics of the insulating film and the selectivity to the photoresist mask are high. After etching before the film, the second step is a method for forming a bit line contact of the semiconductor device, characterized in that the etching is performed under conditions excellent in the etching characteristics of the hard mask nitride film to prevent the etching stops when forming the contact.
일반적으로, 다층 구조의 금속 배선 구조에서 하층의 금속과 상층의 금속은 층간절연막에 의하여 분리되어 있으며, 상층과 하층의 연결이 필요한 부분은 상층의 금속을 증착하기 전에 층간절연막에 금속층간 콘택홀을 통하여 두 층의 금속배선이 연결되게 된다.In general, in the multi-layered metal wiring structure, the lower metal and the upper metal are separated by an interlayer insulating film, and the portions requiring the connection between the upper and lower layers are formed with intermetallic contact holes in the interlayer insulating film before the upper metal is deposited. Through these two layers of metal wiring are connected.
최근 반도체 소자의 고집적화 추세에 따라 유기물, 폴리머 부산물 및 파티클(particle) 등으로 대표되는 오염이 제품의 수율과 신뢰성에 큰 영향을 미치게 되었다.With the recent trend toward higher integration of semiconductor devices, contamination represented by organic materials, polymer by-products, and particles (particles) has a great effect on the yield and reliability of the product.
도 1a 내지 도 1d는 종래 반도체 소자의 비트라인 콘택 형성방법을 순차적으로 나타낸 단면도이다.1A to 1D are cross-sectional views sequentially illustrating a method of forming a bit line contact of a conventional semiconductor device.
도 1a에 도시된 바와 같이, 반도체 기판(10) 상에 도전층(20)과 하드마스크질화막(30)을 증착하고 감광막(미도시함)을 도포하여 비트라인 형성 식각 공정을실시하여 비트라인을 형성한다. 그리고, 상기 비트라인 측벽에 스페이서(40)를 형성하여 도전층(20)의 손상을 방지한다.As shown in FIG. 1A, the conductive layer 20 and the hard mask nitride layer 30 are deposited on the semiconductor substrate 10, and a photosensitive layer (not shown) is applied to the bit line forming etching process. Form. The spacer 40 is formed on the sidewalls of the bit line to prevent damage to the conductive layer 20.
그리고, 도 1b에 도시된 바와 같이, 상기 결과물 상에 층간절연막(50)으로 산화막과 층간절연막(50)을 보호하기 위한 반사방지막(60)을 순차적으로 증착한다.As shown in FIG. 1B, an antireflection film 60 is sequentially deposited on the resultant to protect the oxide film and the interlayer insulating film 50 with the interlayer insulating film 50.
이어서, 도 1c에 도시된 바와 같이, 상기 반사방지막(60) 상부에 비트라인 콘택을 형성하기 위해 감광막(70)을 적층한 후, 패터닝 한다.Subsequently, as shown in FIG. 1C, the photoresist layer 70 is stacked to form a bit line contact on the anti-reflection layer 60, and then patterned.
계속하여, 도 1d에 도시된 바와 같이, 상기 감광막(70)을 마스크로 하여 비트라인의 하드마스크질화막(30)까지 식각하여 비트라인 콘택(80)을 형성한다.Subsequently, as shown in FIG. 1D, the bit line contact 80 is formed by etching the photoresist layer 70 as a mask to the hard mask nitride layer 30 of the bit line.
그런데, 상기와 같이 종래 반도체 소자의 비트라인 콘택 형성방법에 따르면, 상기 비트라인 콘택 형성 시 한번의 식각 공정을 통하여 반사방지막, 층간절연막 및 하드마스크질화막을 식각함에 있어서, 각각의 막들마다 식각 선택비가 달라서 하나의 식각 조건으로 식각공정을 진행할 경우 보잉(bowing) 현상이 없는 프로파일(profile)을 구현하는데 문제점이 있었다.However, according to the bit line contact forming method of the conventional semiconductor device as described above, in etching the anti-reflection film, the interlayer insulating film, and the hard mask nitride film through one etching process when forming the bit line contact, the etching selectivity for each film is high. Therefore, when the etching process is performed under one etching condition, there is a problem in implementing a profile without bowing.
또한, 상기 층간절연막이 두꺼운 경우 식각시간이 길어져 웨이퍼의 온도가 상승하여 하드마스크질화막 식각을 방해하기 때문에 에치 스톱(etch stop)이 발생되는 문제점이 있었다.In addition, when the interlayer insulating layer is thick, the etching time is long, and thus the temperature of the wafer is increased, thereby preventing the hard mask nitride layer from being etched.
본 발명은 상기와 같은 문제점을 해결하기 위해 안출된 것으로, 본 발명의 목적은 금속 콘택 식각 공정을 두단계로 나누어 진행함에 있어서, 제 1단계에서는절연막의 식각 특성과 감광막 마스크에 대한 선택비가 높은 조건으로 식각 정지막 전까지 식각한 후, 제 2 단계로 하드 마스크 질화막의 식각 특성이 우수한 조건으로 식각하여 콘택 형성 시 식각이 멈추는 것을 방지하도록 하는 것이 목적이다.The present invention has been made to solve the above problems, the object of the present invention is to divide the metal contact etching process in two steps, in the first step the etching characteristics of the insulating film and the selectivity to the photoresist mask mask conditions After etching to the etch stop layer, the second step is to etch the etching conditions on the excellent condition of the hard mask nitride film to prevent the etching stops when forming the contact.
도 1a 내지 도 1d는 종래 반도체 소자의 비트라인 콘택 형성방법을 순차적으로 나타낸 단면도이다.1A to 1D are cross-sectional views sequentially illustrating a method of forming a bit line contact of a conventional semiconductor device.
도 2a 내지 도 2d는 본 발명에 따른 반도체 소자의 비트라인 콘택 형성방법을 순차적으로 나타낸 단면도이다.2A through 2D are cross-sectional views sequentially illustrating a method of forming bit line contacts in a semiconductor device according to the present invention.
-- 도면의 주요부분에 대한 부호의 설명 ---Explanation of symbols for the main parts of the drawing-
110 : 반도체 기판 120 : 도전층110 semiconductor substrate 120 conductive layer
130 : 하드마스크 질화막 140 : 비트라인 스페이서130: hard mask nitride layer 140: bit line spacer
150 : 제 1 층간절연막 160 : 식각정지막150: first interlayer insulating film 160: etch stop film
170 : 제 2 층간절연막 180 : 감광막170: second interlayer insulating film 180: photosensitive film
190 : 콘택홀190: contact hole
상기 목적을 달성하기 위하여, 본 발명은 반도체 기판 상에 도전층과 하드마스크질화막을 순차적으로 증착하여 비트라인을 형성한 후, 비트라인 스페이서를 형성하는 단계와, 상기 결과물 상에 제 1 층간절연막, 식각정지막 및 제 2 층간절연막을 순차적으로 증착하는 단계와, 상기 제 2 층간절연막 상부에 비트라인 콘택을 형성하기 위한 감광막을 도포하고, 상기 감광막을 마스크로 하여 식각정지막 전까지 제 1 콘택 식각 공정을 진행하여 제 1 콘택을 형성한 후 안정화시키는 단계와, 상기 감광막을 마스크로 하여 도전층 상부까지 제 2 콘택 식각 공정을 진행하여 비트라인 콘택을 형성하는 단계를 포함하여 이루어진 것을 특징으로 하는 반도체 소자의 비트라인 콘택 형성방법을 제공한다.In order to achieve the above object, the present invention is to form a bit line by sequentially depositing a conductive layer and a hard mask nitride film on a semiconductor substrate, and then forming a bit line spacer, a first interlayer insulating film on the result, Sequentially depositing an etch stop layer and a second interlayer dielectric layer, and applying a photoresist layer to form a bit line contact on the second interlayer dielectric layer, and using the photosensitive layer as a mask until the etch stop layer is formed. And forming a first contact by forming a first contact, and performing a second contact etching process to the upper portion of the conductive layer using the photoresist as a mask to form a bit line contact. A bit line contact forming method is provided.
본 발명은 비트라인 콘택 식각 시 각각 다른 식각 조건으로 두 번 식각공정을 진행하여 콘택 프로파일의 보잉 현상과 에치 스톱 현상을 방지하는 것을 특징으로 한다.The present invention is characterized in that the etching process of the contact profile to prevent the bowing phenomenon and the etch stop phenomenon of the contact profile by performing the etching process twice with different etching conditions, respectively.
이하, 첨부한 도면을 참조하여 본 발명의 바람직한 실시예에 대해 상세히 설명하고자 한다.Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings.
도 2a 내지 도 2d는 본 발명에 따른 반도체 소자의 비트라인 콘택 형성방법을 순차적으로 나타낸 단면도이다.2A through 2D are cross-sectional views sequentially illustrating a method of forming bit line contacts in a semiconductor device according to the present invention.
도 2a에 도시된 바와 같이, 반도체 기판(110) 상에 도전층(120)과 하드마스크질화막(130)을 증착하고 감광막(미도시함)을 도포하여 비트라인 형성 식각 공정을 실시하여 비트라인을 형성한다. 그리고, 상기 비트라인 측벽에 스페이서(140)를 형성하여 도전층(120)의 손상을 방지한다.As shown in FIG. 2A, the conductive layer 120 and the hard mask nitride layer 130 are deposited on the semiconductor substrate 110, and a photoresist layer (not shown) is applied to the bit line forming etching process. Form. In addition, a spacer 140 is formed on the sidewalls of the bit line to prevent damage to the conductive layer 120.
이때, 상기 하드마스크질화막(130)은 500∼1500Å 의 두께로 증착한다.At this time, the hard mask nitride film 130 is deposited to a thickness of 500 ~ 1500Å.
그리고, 도 2b에 도시된 바와 같이, 상기 결과물 상에 제 1 층간절연막(150), 식각 정지막(160) 및 제 2 층간절연막(170)을 순차적으로 증착한다.As shown in FIG. 2B, the first interlayer insulating layer 150, the etch stop layer 160, and the second interlayer insulating layer 170 are sequentially deposited on the resultant.
이때, 상기 식각 정지막(160)은 후속 두단계의 식각 공정 시 제 1 콘택 식각 공정과 제 2 콘택 식각 공정의 경계점으로 사용되며, 200∼1000Å 범위의 두께로 증착한다.In this case, the etch stop layer 160 is used as a boundary point between the first contact etching process and the second contact etching process in the subsequent two-step etching process, and is deposited to have a thickness in the range of 200 to 1000 GPa.
이어서, 도 2c에 도시된 바와 같이, 상기 제 2 층간절연막(170) 상부에 비트라인 콘택이 형성되도록 감광막(180)을 도포하여, 이 감광막(180)을 마스크로 하여 식각 정지막(160) 전까지 제 1 콘택 식각 공정을 진행한 후 웨이퍼의 상태를 안정화시킨다.Subsequently, as illustrated in FIG. 2C, a photoresist layer 180 is coated to form a bit line contact on the second interlayer insulating layer 170, and the photoresist layer 180 is used as a mask before the etch stop layer 160. After the first contact etching process is performed, the state of the wafer is stabilized.
이때, 상기 제 1 콘택 식각 공정 시 감광막(180)에 대한 식각 선택비가 높은 C/F비율을 지닌 C4F8, C5F8및 C4F6가스와 콘택홀 식각 특성 개선을 위한 CO, O2및 Ar가스가 혼합된 가스를 사용하여 식각한다.In this case, in the first contact etching process, C 4 F 8 , C 5 F 8 and C 4 F 6 gas having a high C / F ratio for the photoresist layer 180 and CO for improving the contact hole etching characteristics, Etch using a mixture of O 2 and Ar gas.
또한, 상기 제 1 콘택 식각 공정을 마친 후 20∼120sec 정도 안정화 단계를 거친 후에 후속 공정인 제 2 콘택 식각 공정을 실시하며, 상기 안정화 단계에서는 플라즈마가 생성되지 않게 파워가 오프된 상태에서 CxHyFz 가스인 CH3F, CH2F2, CHF3및 C2H2F5가스와 CO, O2및 Ar가스가 혼합된 가스만 흘려준다.In addition, after the first contact etching process, the second contact etching process, which is a subsequent process after the stabilization step of about 20 to 120 sec, is performed, and in the stabilization step, the CxHyFz gas is turned off so that plasma is not generated. Only the mixtures of CH 3 F, CH 2 F 2 , CHF 3 and C 2 H 2 F 5 gas with CO, O 2 and Ar gas flow.
계속하여, 도 2d에 도시된 바와 같이, 상기 감광막(180)을 마스크로 하여 비트라인의 하드마스크질화막(130)까지 제 2 콘택 식각 공정을 진행하여 비트라인 콘택(190)을 형성한다.Subsequently, as shown in FIG. 2D, the second contact etching process is performed to the hard mask nitride layer 130 of the bit line by using the photoresist layer 180 as a mask to form the bit line contact 190.
이때, 상기 제 2 콘택 식각 공정은 비트라인의 하드마스크질화막(130)이 완전 식각되도록 전체 식각 시간의 20∼70% 정도 과도식각하며, CxHyFz 가스인 CH3F, CH2F2, CHF3및 C2H2F5가스와 CO, O2및 Ar가스가 혼합된 가스를 사용하여 콘택홀의 식각 특성을 향상시킨다.In this case, the second contact etching process may overetch 20 to 70% of the entire etching time so that the hard mask nitride layer 130 of the bit line is completely etched, and CH 3 F, CH 2 F 2 , CHF 3 and CxHyFz gas. Etch characteristics of the contact holes are improved by using a mixture of C 2 H 2 F 5 gas and CO, O 2 and Ar gas.
따라서, 상기한 바와 같이, 본 발명에 따른 반도체 소자의 비트라인 콘택 형성방법을 이용하게 되면, 금속 콘택 식각 공정을 두단계로 나누어 진행함에 있어서, 제 1단계에서는 절연막의 식각 특성과 감광막 마스크에 대한 선택비가 높은 조건으로 식각 정지막 전까지 식각한 후, 제 2 단계로 하드 마스크 질화막의 식각 특성이 우수한 조건으로 식각하여 콘택 형성 시 식각이 멈추는 것을 방지하도록 하는 매우 유용하고 효과적인 발명이다.Therefore, as described above, when the bit line contact forming method of the semiconductor device according to the present invention is used, the metal contact etching process is divided into two steps. In the first step, the etching characteristics of the insulating film and the photoresist mask are After etching to the etch stop layer under a high selectivity condition, the second step is a very useful and effective invention for etching the hard mask nitride layer under excellent etching characteristics to prevent the etch stop when forming a contact.
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