KR20040001127A - Method for manufacturing gate of nonvolatile semiconductor memory device - Google Patents
Method for manufacturing gate of nonvolatile semiconductor memory device Download PDFInfo
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- KR20040001127A KR20040001127A KR1020020036227A KR20020036227A KR20040001127A KR 20040001127 A KR20040001127 A KR 20040001127A KR 1020020036227 A KR1020020036227 A KR 1020020036227A KR 20020036227 A KR20020036227 A KR 20020036227A KR 20040001127 A KR20040001127 A KR 20040001127A
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- 239000004065 semiconductor Substances 0.000 title claims abstract description 25
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 9
- 238000000034 method Methods 0.000 title abstract description 8
- 239000000758 substrate Substances 0.000 claims abstract description 10
- 150000004767 nitrides Chemical class 0.000 claims abstract description 7
- 238000009832 plasma treatment Methods 0.000 claims abstract description 7
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 claims abstract description 4
- 239000001301 oxygen Substances 0.000 claims abstract description 4
- 229910052760 oxygen Inorganic materials 0.000 claims abstract description 4
- 229910052581 Si3N4 Inorganic materials 0.000 claims description 16
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 claims description 16
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims description 14
- 229920005591 polysilicon Polymers 0.000 claims description 14
- 125000004430 oxygen atom Chemical group O* 0.000 claims description 6
- 230000014759 maintenance of location Effects 0.000 abstract description 3
- 239000010410 layer Substances 0.000 description 11
- 238000005229 chemical vapour deposition Methods 0.000 description 4
- 238000002955 isolation Methods 0.000 description 4
- 230000003647 oxidation Effects 0.000 description 3
- 238000007254 oxidation reaction Methods 0.000 description 3
- IJGRMHOSHXDMSA-UHFFFAOYSA-N Atomic nitrogen Chemical compound N#N IJGRMHOSHXDMSA-UHFFFAOYSA-N 0.000 description 2
- 230000007547 defect Effects 0.000 description 1
- 238000005530 etching Methods 0.000 description 1
- 239000011229 interlayer Substances 0.000 description 1
- 229910052757 nitrogen Inorganic materials 0.000 description 1
- 238000004544 sputter deposition Methods 0.000 description 1
Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66833—Unipolar field-effect transistors with an insulated gate, i.e. MISFET with a charge trapping gate insulator, e.g. MNOS transistors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66825—Unipolar field-effect transistors with an insulated gate, i.e. MISFET with a floating gate
Abstract
Description
본 발명은 반도체 메모리 장치의 제조방법에 관한 것으로 보다 상세하는 불휘발성 반도체 메모리 장치의 플로팅 게이트와 콘트롤 게이트 사이에 위치하는 층간유전막 제조방법에 관한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of manufacturing a semiconductor memory device, and more particularly, to a method of manufacturing an interlayer dielectric film positioned between a floating gate and a control gate of a nonvolatile semiconductor memory device.
일반적으로 DRAM(Dynamic Random Access Memory) 혹은 불휘발성 메모리 소자인 NVM(Non-Volatile Memory)과 같은 반도체 메모리 소자의 유전체막으로 ONO(Oxide/Nitride/Oxide) 구조의 유전체막을 사용한다. 즉 유전체막으로 산화막/질화막/산화막이 순차적으로 적층된 구조를 사용한다.In general, a dielectric film having an ONO (Oxide / Nitride / Oxide) structure is used as a dielectric film of a semiconductor memory device, such as a DRAM (Dynamic Random Access Memory) or a non-volatile memory (NVM). That is, a structure in which an oxide film / nitride film / oxide film is sequentially stacked as a dielectric film is used.
도 1은 종래 반도체 메모리 장치의 유전체막을 설명하기 위해 나타낸 단면도이다.1 is a cross-sectional view illustrating a dielectric film of a conventional semiconductor memory device.
도 1에 도시된 바와 같이, 아이솔레이션 영역(12), 예컨대 STI(Shallow Trench Isolation) 영역에 의해 반도체기판 내에 액티브 영역이 한정된다. 상기 STI 영역은 반도체기판(12) 내에 일정 깊이까지 형성되고, 동시에 반도체기판(10) 표면 위로 일정 높이까지 돌출되도록 형성된다.As shown in FIG. 1, an active region is defined within the semiconductor substrate by an isolation region 12, for example, a shallow trench isolation (STI) region. The STI region is formed to a predetermined depth in the semiconductor substrate 12 and at the same time protrudes to a predetermined height above the surface of the semiconductor substrate 10.
상기 액티브 영역 위에는 터널 산화막(14)이 일정 두께로 형성되며, 이 터널 산화막(14) 위에는 플로팅 게이트 도전층으로 사용되는 제 1 폴리실리콘막(16)이 형성된다.A tunnel oxide film 14 is formed to a predetermined thickness on the active region, and a first polysilicon film 16 used as a floating gate conductive layer is formed on the tunnel oxide film 14.
상기 제 1 폴리실리콘막(16)은 반도체기판 표면 위로 돌출된 STI 영역(12)의일부 상부 표면 위에도 형성되며, 인접한 단위 셀내의 다른 제 1 폴리실리콘막(16)과 일정 간격 이격된다.The first polysilicon film 16 is also formed on a portion of the upper surface of the STI region 12 protruding above the surface of the semiconductor substrate and spaced apart from other first polysilicon films 16 in adjacent unit cells.
그리고, 상기 제 1 폴리실리콘막(16) 위에는 유전체막(20)이 형성되는데, 이 유전체막(20)은 하부 산화막(21), 질화실리콘막(22) 및 상부 산화막(23)이 순차적으로 적층되어 형성된다.A dielectric film 20 is formed on the first polysilicon film 16, and the dielectric film 20 is formed by sequentially stacking a lower oxide film 21, a silicon nitride film 22, and an upper oxide film 23. It is formed.
이어, 상기 유전체막(20) 위에는 컨트롤 게이트 도전층으로 사용되는 제 2 폴리실리콘막(30)이 형성되며, 이 제 2 폴리실리콘막(30)은 모든 단위 셀에 공통되도록 형성된다.Subsequently, a second polysilicon film 30 used as a control gate conductive layer is formed on the dielectric film 20, and the second polysilicon film 30 is formed to be common to all unit cells.
상기 불휘발성 메모리 장치, 예컨대 NVM과 같이 DRAM에 비하여 상대적으로 높은 구동 전압을 갖는 반도체 메모리 장치의 경우, 상기 유전체막(20)을 구성하는 하부 및 상부 산화막(21,23)의 두께가 상대적으로 두꺼워야 한다는 제약이 있다.In the case of the nonvolatile memory device, for example, a semiconductor memory device having a driving voltage relatively higher than that of DRAM, the thicknesses of the lower and upper oxide films 21 and 23 constituting the dielectric film 20 are relatively thick. There is a constraint that it should.
따라서 이 경우, 하부 및 상부 산화막(21,23)으로서 화학 기상 증착법을 이용한 CVD 산화막을 사용하고 있으나, 상기 상부 산화막(23)으로 CVD 산화막을 사용할 경우, 하부의 질화실리콘막(22)과 "A"에 도시된 바와 같이 계면 특성으로 인하여, CVD 산화막 내에 각종 결함이 발생하며, 충분한 두께를 갖는 CVD 산화막을 형성시키기가 어려운 문제점이 있었다.Therefore, in this case, although the CVD oxide film using chemical vapor deposition is used as the lower and upper oxide films 21 and 23, when the CVD oxide film is used as the upper oxide film 23, the lower silicon nitride film 22 and "A" are used. As shown in FIG. 2, due to the interfacial properties, various defects occur in the CVD oxide film, and it is difficult to form a CVD oxide film having a sufficient thickness.
본 발명은 상기와 같은 문제점을 해결하기 위해 안출된 것으로, 본 발명의 목적은 불휘발성 반도체 메모리 장치의 ONO막을 형성함에 있어서, 하부 산화막과이 하부 산화막 위에 질화실리콘막을 형성하고, 이 질화실리콘막 상부에 산화를 위한 O2플라즈마 처리하여 산소 원자의 씨드(seed)를 형성한 후, 이 씨드를 바탕으로 상부 산화막을 형성함으로써, ONO막의 전하 보유 특성이 향상되도록 하는 불휘발성 반도체 메모리 장치의 게이트 제조방법을 제공하는데 있다.SUMMARY OF THE INVENTION The present invention has been made to solve the above problems, and an object of the present invention is to form a silicon nitride film on the lower oxide film and the lower oxide film in forming the ONO film of the nonvolatile semiconductor memory device, and on the silicon nitride film. A method of manufacturing a gate of a nonvolatile semiconductor memory device in which a seed of oxygen atoms is formed by O 2 plasma treatment for oxidation, and an upper oxide film is formed based on the seed, thereby improving charge retention characteristics of the ONO film. To provide.
도 1은 종래 반도체 메모리 장치의 유전체막을 설명하기 위해 나타낸 단면도이다.1 is a cross-sectional view illustrating a dielectric film of a conventional semiconductor memory device.
도 2a 내지 도 2c는 본 발명의 바람직한 실시예에 따른 불휘발성 반도체 메모리 장치의 게이트 제조방법을 설명하기 위해 순차적으로 나타낸 단면도이다.2A through 2C are cross-sectional views sequentially illustrating a method of manufacturing a gate of a nonvolatile semiconductor memory device according to an exemplary embodiment of the present invention.
-- 도면의 주요부분에 대한 부호의 설명 ---Explanation of symbols for the main parts of the drawing-
100 : 반도체기판 102 : 필드산화막100: semiconductor substrate 102: field oxide film
104 : 터널 산화막 106 : 플로팅 게이트104 tunnel oxide film 106 floating gate
110 : ONO막 111 : 제 1 산화막110: ONO film 111: first oxide film
112 : 질화실리콘막 113 : 제 2 산화막112: silicon nitride film 113: second oxide film
120 : 컨트롤 게이트120: control gate
상기 목적을 달성하기 위하여, 본 발명은 불휘발성 반도체 메모리 장치의 게이트 제조방법에 있어서, 반도체기판 상부에 게이트 절연막 및 플로팅 게이트로서 가능하는 제 1 폴리실리콘막을 형성하는 단계와, 상기 질화막이 상부에 고유전막의 하부산화막으로서 가능하는 제1산화막 및 질화실리콘막을 형성하는 단계와, 상기 질화실리콘막의 상부 표면에 O2플라즈마 처리하여 산소 원자 씨드(seed)를 형성한 후 이를 바탕으로 제2산화막을 형성하는 단계와, 상기 제2산화막의 상부에 콘트롤 게이트로서 기능하는 제 2 폴리실리콘막을 형성하는 단계를 포함하여 이루어진 것을 특징으로 한다.In order to achieve the above object, the present invention provides a method of manufacturing a gate of a nonvolatile semiconductor memory device, the method comprising: forming a first polysilicon film on the semiconductor substrate, the first polysilicon film serving as a gate insulating film and a floating gate; Forming a first oxide film and a silicon nitride film, which can be used as a lower oxide film of the entire film, and forming an oxygen atom seed by O 2 plasma treatment on an upper surface of the silicon nitride film, and then forming a second oxide film based thereon And forming a second polysilicon film functioning as a control gate on the second oxide film.
이하, 첨부한 도면을 참조하여 본 발명의 바람직한 실시예에 대해 상세히 설명하고자 한다. 다음에 설명되는 실시예는 여러 가지 다른 형태로 변형될 수 있으며, 본 발명의 범위가 아래에서 상술되는 실시예에 한정되는 것은 아니다.Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings. The embodiments described below may be modified in many different forms, and the scope of the present invention is not limited to the embodiments described below.
도 2a 내지 도 2c는 본 발명의 바람직한 실시예에 따른 불휘발성 반도체 메모리 장치의 게이트 제조방법을 설명하기 위해 순차적으로 나타낸 단면도이다.2A through 2C are cross-sectional views sequentially illustrating a method of manufacturing a gate of a nonvolatile semiconductor memory device according to an exemplary embodiment of the present invention.
도 2a에 도시된 바와 같이, 아이솔레이션 영역, 예컨대 STI(Shallow Trench Isolation) 영역에 의해 반도체기판 상부에 필드산화막(102)을 형성함으로써, 반도체기판(100)을 액티브 영역과 필드 영역으로 구분한 후, 상기 액티브 영역의 상부에 산화막 또는 산질화막(oxynitride)을 약 70 ~ 100Å의 두께로 얇게 성장시킴으로써 메모리 셀의 터널 산화막(104)을 형성한다.As shown in FIG. 2A, after the field oxide film 102 is formed on the semiconductor substrate by an isolation region, for example, a shallow trench isolation (STI) region, the semiconductor substrate 100 is divided into an active region and a field region. An oxide film or an oxynitride is thinly grown on the active region to a thickness of about 70 to about 100 GPa to form the tunnel oxide film 104 of the memory cell.
그리고, 상기 터널 산화막(104)이 형성된 결과물의 상부에 플로팅 게이트(106)로서, 예컨대 폴리실리콘층을 약 1000~1500Å이 두께로 화학기상증착 방법 또는 스퍼터링 방법을 이용하여 증착하고 사진 및 식각 공정으로 셀 어레이 영역의 필드 산화막(102) 상부의 플로팅 게이트(미도시함)를 제거함으로서, 비트라인을 따라 이웃한 메모리 셀 간의 플로팅 게이트(106)를 서로 분리시킨다.Then, as the floating gate 106, a polysilicon layer is deposited to a thickness of about 1000 to 1500 Å by using a chemical vapor deposition method or a sputtering method as a floating gate 106 on the resultant, in which the tunnel oxide film 104 is formed. By removing the floating gates (not shown) on the field oxide layer 102 in the cell array region, the floating gates 106 between neighboring memory cells along the bit lines are separated from each other.
이어서, 상기 플로팅 게이트(106)가 형성되어 있는 결과물의 상부에 열산화공정 또는 화학기상증착공정을 실시하여 약 20~80Å 두께의 산화막을 증착하여 ONO막(110) 중의 하부 산화막인 제 1 산화막(111)을 형성한다.Subsequently, a thermal oxidation process or a chemical vapor deposition process is performed on the resultant on which the floating gate 106 is formed to deposit an oxide film having a thickness of about 20 to 80 kV to form a first oxide film as a lower oxide film in the ONO film 110. 111).
도 2b에 도시된 바와 같이, 상기 제 1 산화막(111) 상부에 화학기상증착법을 실시하여 20~100Å 두께의 질화실리콘막(112)을 형성하며, 상기 질화실리콘막(112)은 ONO막(110) 중의 가운데에 위치하는 질화막이다.As shown in FIG. 2B, a silicon nitride film 112 having a thickness of 20 to 100 Å is formed by performing chemical vapor deposition on the first oxide film 111, and the silicon nitride film 112 is an ONO film 110. It is a nitride film located in the middle of).
그리고, 상기 질화실리콘막(112)이 형성되어 있는 결과물 상부에 O2플라즈마 처리 공정을 실시하여 질화실리콘막(112) 표면의 질소(N)을 산소(O)로 치환함으로써, 질화실리콘막(112) 표면에 산소 원자의 씨드(seed)를 형성한다.Then, the silicon nitride film 112 is formed by performing an O 2 plasma treatment process on the resultant on which the silicon nitride film 112 is formed to replace nitrogen (N) on the surface of the silicon nitride film 112 with oxygen (O). ) Seeds of oxygen atoms are formed on the surface.
도 2c에 도시된 바와 같이, 상기 O2플라즈마 처리된 질화실리콘막(112) 상부에 산소 원자의 씨드(seed)를 바탕으로 하여 ONO막(110)의 상부 산화막인 제 2 산화막(113)을 형성하므로 상부 산화막의 성질을 향상시킨다.As illustrated in FIG. 2C, a second oxide layer 113 is formed on the O 2 plasma-treated silicon nitride layer 112 based on a seed of oxygen atoms, which is an upper oxide layer of the ONO layer 110. Therefore, the properties of the upper oxide film are improved.
그 후, 상기 제 2 산화막(113) 상부에 컨트롤 게이트(120)로서, 예컨대 폴리실리콘층을 약 1500~3000Å이 두께로 증착한 후, 사진 및 식각 공정을 통해 상기 컨트롤 게이트(120), ONO막(110) 및 플로팅 게이트(106)를 차례로 식각하여 메모리 셀의 스택형 게이트 전극(미도시함)을 형성한다.Subsequently, as a control gate 120 on the second oxide layer 113, for example, a polysilicon layer is deposited to a thickness of about 1500 to 3000 μm, and then the control gate 120 and the ONO layer are formed by a photo and etching process. The 110 and the floating gate 106 are sequentially etched to form a stacked gate electrode (not shown) of the memory cell.
상술한 바와 같이, 본 발명의 바람직한 실시예를 참조하여 설명하였지만 해당 기술 분야의 숙련된 당업자라면 하기의 특허청구범위에 기재된 본 발명의 사상 및 영역으로부터 벗어나지 않는 범위 내에서 본 발명을 다양하게 수정 및 변경시킬 수 있음을 이해할 수 있을 것이다.As described above, although described with reference to a preferred embodiment of the present invention, those skilled in the art will be variously modified and modified within the scope of the present invention without departing from the spirit and scope of the invention described in the claims below. It will be appreciated that it can be changed.
따라서, 상기한 바와 같이, 본 발명에 따른 불휘발성 반도체 메모리 장치의 ONO막을 형성함에 있어서, 질화 실리콘막 상부에 산화를 위한 O2플라즈마 처리하여 산소 원자의 씨드(seed)를 형성한 후, 이 씨드를 바탕으로 상부 산화막을 형성함으로써, ONO막의 전하 보유 특성이 향상되어 반도체 장치의 전체적인 동작특성이 향상되는 효과를 얻게 된다.Therefore, as described above, in forming the ONO film of the nonvolatile semiconductor memory device according to the present invention, the seed of oxygen atoms is formed by performing O 2 plasma treatment for oxidation on the silicon nitride film. By forming the upper oxide film on the basis of the above, the charge retention characteristic of the ONO film is improved, and thus the overall operating characteristic of the semiconductor device is improved.
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