KR20040079172A - Method for forming dielectric layer of semiconductor device - Google Patents
Method for forming dielectric layer of semiconductor device Download PDFInfo
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- KR20040079172A KR20040079172A KR1020030014114A KR20030014114A KR20040079172A KR 20040079172 A KR20040079172 A KR 20040079172A KR 1020030014114 A KR1020030014114 A KR 1020030014114A KR 20030014114 A KR20030014114 A KR 20030014114A KR 20040079172 A KR20040079172 A KR 20040079172A
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- film
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- oxide film
- semiconductor device
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- 238000000034 method Methods 0.000 title claims abstract description 23
- 239000004065 semiconductor Substances 0.000 title claims abstract description 16
- 150000004767 nitrides Chemical class 0.000 claims abstract description 30
- 125000004433 nitrogen atom Chemical group N* 0.000 claims abstract description 13
- 230000014759 maintenance of location Effects 0.000 abstract description 5
- 239000000758 substrate Substances 0.000 abstract description 4
- 238000000151 deposition Methods 0.000 abstract description 3
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 8
- 229920005591 polysilicon Polymers 0.000 description 8
- 229910018557 Si O Inorganic materials 0.000 description 4
- 238000002955 isolation Methods 0.000 description 4
- LIVNPJMFVYWSIS-UHFFFAOYSA-N silicon monoxide Inorganic materials [Si-]#[O+] LIVNPJMFVYWSIS-UHFFFAOYSA-N 0.000 description 4
- 229910007991 Si-N Inorganic materials 0.000 description 3
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 3
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 3
- 229910006294 Si—N Inorganic materials 0.000 description 3
- 238000009832 plasma treatment Methods 0.000 description 3
- 229910052710 silicon Inorganic materials 0.000 description 3
- 239000010703 silicon Substances 0.000 description 3
- 229910052814 silicon oxide Inorganic materials 0.000 description 3
- 125000004430 oxygen atom Chemical group O* 0.000 description 2
- 230000015572 biosynthetic process Effects 0.000 description 1
- 230000010354 integration Effects 0.000 description 1
Classifications
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B41/00—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates
- H10B41/40—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the peripheral circuit region
- H10B41/42—Simultaneous manufacture of periphery and memory cells
- H10B41/43—Simultaneous manufacture of periphery and memory cells comprising only one type of peripheral transistor
- H10B41/48—Simultaneous manufacture of periphery and memory cells comprising only one type of peripheral transistor with a tunnel dielectric layer also being used as part of the peripheral transistor
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B41/00—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates
- H10B41/40—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the peripheral circuit region
- H10B41/42—Simultaneous manufacture of periphery and memory cells
- H10B41/43—Simultaneous manufacture of periphery and memory cells comprising only one type of peripheral transistor
- H10B41/47—Simultaneous manufacture of periphery and memory cells comprising only one type of peripheral transistor with a floating-gate layer also being used as part of the peripheral transistor
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
- H01L21/28008—Making conductor-insulator-semiconductor electrodes
- H01L21/28017—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon
- H01L21/28158—Making the insulator
- H01L21/28167—Making the insulator on single crystalline silicon, e.g. using a liquid, i.e. chemical oxidation
- H01L21/28194—Making the insulator on single crystalline silicon, e.g. using a liquid, i.e. chemical oxidation by deposition, e.g. evaporation, ALD, CVD, sputtering, laser deposition
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- Engineering & Computer Science (AREA)
- Manufacturing & Machinery (AREA)
- Non-Volatile Memory (AREA)
Abstract
Description
본 발명은 반도체 소자의 유전체막 형성 방법에 관한 것으로, 보다 상세하게는 비휘발성 메모리 제품에 이용되는 N 원자의 씨드을 이용하여 질화막을 성장시킴으로써 결정질 우수한 질화막으로 구성되는 ONO 막을 형성함하고, 이에따라 유전체막의 특성을 향상시킬 수 있도록 하는 반도체 소자의 유전체막 형성 방법에 관한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for forming a dielectric film of a semiconductor device, and more particularly, to form an ONO film composed of an excellent crystalline nitride film by growing a nitride film by using a seed of N atoms used in a nonvolatile memory product. The present invention relates to a method for forming a dielectric film of a semiconductor device capable of improving characteristics.
일반적으로 DRAM(Dynamic Random Access Memory) 혹은 비휘발성 메모리 소자인 NVM(Non-Volatile Memory)과 같은 반도체 메모리 소자의 유전체막으로 ONO(Oxide/Nitride/Oxide) 구조의 유전체막을 사용한다. 즉 유전체막으로서 산화막/질화막/산화막이 순차적으로 적층된 구조를 사용한다.In general, a dielectric film of ONO (Oxide / Nitride / Oxide) structure is used as a dielectric film of a semiconductor memory device, such as a DRAM (Dynamic Random Access Memory) or a non-volatile memory (NVM). That is, a structure in which an oxide film / nitride film / oxide film is sequentially stacked is used as the dielectric film.
특히, 비휘발성 메모리 소자인 EPROM 또는 FLASH EPROM 에서는 소형, 대용량, 저소비 전력을 특징으로 하기 때문에 메모리를 저전압으로 장기간에 걸쳐 안정하게 구동하기 위해서는 리텐션(Retention) 특성이 뛰어난 ONO막이 필요하다. 이러한 ONO막의 리텐션(Retention)특성은 ONO 각각의 층인 하부 산화막, 질화막, 상부 산화막의 각각의 층에 의한 영향을 받지만 그 중에서도 질화막의 영향을 가장 많이 받는다.In particular, since the EPROM or FLASH EPROM, which is a nonvolatile memory device, is characterized by small size, large capacity, and low power consumption, an ONO film having excellent retention characteristics is required to drive the memory stably over a long period of time at low voltage. The retention characteristic of the ONO film is influenced by the respective layers of the lower oxide film, the nitride film, and the upper oxide film, which are each of the ONO layers, but most of them are affected by the nitride film.
이와 같은 종래 기술에 의한 반도체 소자의 유전체막 형성시의 문제점을 아래에 도시된 도면을 통해 설명하면 다음과 같다.The problem at the time of forming the dielectric film of the semiconductor device according to the prior art will be described with reference to the drawings shown below.
도1a 내지 도1f는 종래 기술에 의한 반도체 소자의 유전체막 형성 방법을 나타낸 공정 단면도이다.1A to 1F are cross-sectional views showing a method of forming a dielectric film of a semiconductor device according to the prior art.
먼저, 도1a에 도시된 바와 같이 실리콘 기판(100) 상에 소자 분리 영역, 예컨대 STI(Shallow Trench Isolation : 미도시함)에 의해 액티브 영역을 정의한다. 그리고, 액티브 영역에 실리콘 산화막을 일정 두께로 성장시켜 터널 산화막(102)을 형성한다.First, as shown in FIG. 1A, an active region is defined on a silicon substrate 100 by an isolation region, for example, shallow trench isolation (STI). The silicon oxide film is grown to a predetermined thickness in the active region to form the tunnel oxide film 102.
이어서, 도1b에 도시된 바와 같이 상기 터널 산화막(102)의 상부에 플로팅 게이트 도전층으로 제 1 폴리실리콘막(104)을 증착한다.Subsequently, as illustrated in FIG. 1B, a first polysilicon film 104 is deposited as a floating gate conductive layer on the tunnel oxide film 102.
그럼 다음, 도1c에 도시된 바와 같이 폴리실리콘층 표면을 산화시키거나, 증착 방식을 이용하여 하부 산화막(106)을 형성한다. 이때, 하부 산화막(106) 표면에는 제 1 폴리실리콘막(104)의 실리콘과 하부 산화막의 옥사이드의 결합으로 A 부위와 같이 Si-O로 결합되어 있다.Then, as shown in FIG. 1C, the surface of the polysilicon layer is oxidized, or the lower oxide film 106 is formed using a deposition method. At this time, the silicon oxide of the first polysilicon film 104 and the oxide of the lower oxide film are bonded to the surface of the lower oxide film 106 by Si-O like the A portion.
그리고 나서, 도1d에 도시된 바와 같이 상기 하부 산화막(106) 상부에 질화막(108)을 증착하고, 도1e에 도시된 바와 같이 상부 산화막(110)을 증착하여 ONO 유전체막(112)을 형성한다.Then, as illustrated in FIG. 1D, a nitride film 108 is deposited on the lower oxide film 106, and an upper oxide film 110 is deposited as shown in FIG. 1E to form an ONO dielectric film 112. .
그런 다음, 도1f에 도시된 바와 같이 컨트롤 게이트 도전층으로 제 2 폴리실리콘막(114)을 증착한다.Then, as shown in FIG. 1F, a second polysilicon film 114 is deposited as the control gate conductive layer.
이와 같이 종래 기술에 의해 유전체막을 형성할 경우, 리텐션(Retetion) 특성에 가장 중요한 변수로 작용하는 질화막의 성질이 우수하지 못하여 누설 전류를억제하기 위해서는 ONO막의 두께가 필요 이상으로 두꺼워 져야하는 문제점이 있었다.As described above, in the case of forming the dielectric film by the prior art, there is a problem that the thickness of the ONO film needs to be thicker than necessary in order to suppress leakage current because the nitride film, which is the most important parameter in retention characteristics, is not excellent. there was.
결국, 절연막의 두께가 두꺼워지면 메모리 소자의 기입 및 소거 전압이 필연적으로 증가하여 그 결과 터널 산화막이 고전압에 견디기 위해 상대적으로 두꺼워 져야하는 문제점이 있었다.As a result, when the thickness of the insulating layer becomes thick, the write and erase voltages of the memory device inevitably increase, and as a result, the tunnel oxide film has to be relatively thick to withstand the high voltage.
상기와 같은 문제점을 해결하기 위한 본 발명은 하부 산화막을 형성하고, 하부 산화막 표면에 N2플라즈마 처리를 하여 하부 산화막 표면의 O 원자를 N 원자로 치환하고 이를 씨드층으로 이용하여 질화막을 형성함으로써, 결정질이 우수한 질화막을 형성할 수 있도록 하는 반도체 소자의 유전체막 형성 방법을 제공하기 위한 것이다.In order to solve the above problems, the present invention forms a lower oxide film, and a N 2 plasma treatment on the lower oxide film surface to replace the O atoms of the lower oxide film surface with N atoms to form a nitride film using the seed layer, It is an object of the present invention to provide a method for forming a dielectric film of a semiconductor device capable of forming this excellent nitride film.
도1a 내지 도1f는 종래 기술에 의한 반도체 소자의 유전체막 형성 방법을 나타낸 공정 단면도이다.1A to 1F are cross-sectional views showing a method of forming a dielectric film of a semiconductor device according to the prior art.
도2a 내지 도2g는 본 발명에 의한 반도체 소자의 유전체막 형성 방법을 나타낸 공정 단면도들이다.2A to 2G are cross-sectional views illustrating a method of forming a dielectric film of a semiconductor device according to the present invention.
- 도면의 주요부분에 대한 부호의 설명 --Explanation of symbols for the main parts of the drawings-
100 : 실리콘 기판 102 : 터널 산화막100 silicon substrate 102 tunnel oxide film
104 : 제 1 폴리실리콘막 106 : 하부 산화막104: first polysilicon film 106: lower oxide film
106' : 플라즈마 처리된 하부 산화막 108 : 질화막106 ': plasma-treated lower oxide film 108: nitride film
110 : 상부 산화막 112 : ONO막110: upper oxide film 112: ONO film
A : Si-O 결합 B : Si-N 결합A: Si-O bond B: Si-N bond
상기와 같은 목적을 실현하기 위한 본 발명은 ONO 구조를 이용한 반도체 소자의 유전체막 형성 방법에 있어서, 하부 산화막을 형성한 후 하부 산화막 표면에 N 원자 씨드층을 형성하는 단계와, 상기 하부 산화막 상부에 질화막을 성장시키는 단계와, 상기 질화막 상부에 상부 산화막을 형성하는 단계를 포함하는 것을 특징으로 하는 반도체 소자의 유전체막 형성 방법에 관한 것이다.In order to achieve the above object, the present invention provides a method for forming a dielectric film of a semiconductor device using an ONO structure, the method comprising: forming an N atom seed layer on a surface of a lower oxide film after forming a lower oxide film; And growing an nitride film and forming an upper oxide film on the nitride film.
이와 같은 본 발명의 반도체 소자의 유전체막 형성 방법에 의하면, 하부 산화막 표면에 N2플라즈마 공정을 진행하여 O 원자를 N 원자로 치환시켜 이 N 원자를 씨드층으로 이용하여 질화막을 성장시킴으로써 우수한 결정질의 질화막을 형성하여 ONO막의 특성을 향상시킬 수 있다.According to the method for forming a dielectric film of the semiconductor device of the present invention, an excellent crystalline nitride film is formed by performing an N 2 plasma process on the surface of the lower oxide film to replace O atoms with N atoms and growing a nitride film using the N atoms as seed layers. Can be formed to improve the characteristics of the ONO film.
상기와 같은 본 발명의 반도체 소자의 유전체막 형성 방법에 있어서, 상기 N 원자 씨드층은 N2플라즈마 공정을 실시함으로써 형성하는 것이 바람직하다.In the method for forming a dielectric film of a semiconductor device of the present invention as described above, the N atom seed layer is preferably formed by performing an N 2 plasma process.
이하, 본 발명의 바람직한 실시예를 첨부된 도면을 참조하여 설명한다. 또한 본 실시예는 본 발명의 권리범위를 한정하는 것은 아니고, 단지 예시로 제시된 것이며 종래 구성과 동일한 부분은 동일한 부호 및 명칭을 사용한다.Hereinafter, exemplary embodiments of the present invention will be described with reference to the accompanying drawings. In addition, the present embodiment is not intended to limit the scope of the present invention, but is presented by way of example only and the same parts as in the conventional configuration using the same reference numerals and names.
도2a 내지 도2g는 본 발명에 의한 반도체 소자의 유전체막 형성 방법을 나타낸 공정 단면도들이다.2A to 2G are cross-sectional views illustrating a method of forming a dielectric film of a semiconductor device according to the present invention.
우선, 도2a에 도시된 바와 같이 실리콘 기판(100) 상에 소자 분리 영역, 예컨대 STI(Shallow Trench Isolation : 미도시함)에 의해 액티브 영역을 정의한다. 그리고, 액티브 영역에 실리콘 산화막을 일정 두께로 성장시켜 터널 산화막(102)을 형성한다.First, as shown in FIG. 2A, an active region is defined on the silicon substrate 100 by an isolation region, for example, shallow trench isolation (STI). The silicon oxide film is grown to a predetermined thickness in the active region to form the tunnel oxide film 102.
이어서, 도2b에 도시된 바와 같이 상기 터널 산화막(102)의 상부에 플로팅 게이트 도전층으로 제 1 폴리실리콘막(104)을 증착하고, 도2c에 도시된 바와 같이 폴리실리콘층 표면을 산화시키거나, 증착 방식을 이용하여 하부 산화막(106)을 형성한다.Subsequently, a first polysilicon film 104 is deposited as a floating gate conductive layer on the tunnel oxide film 102 as shown in FIG. 2B, and the surface of the polysilicon layer is oxidized as shown in FIG. 2C. The lower oxide film 106 is formed using a deposition method.
그리고 나서, 도2d에 도시된 바와 같이 상기 하부 산화막(106) 표면에 N2가스를 이용한 플라즈마 처리를 함으로써 하부 산화막(106) 표면의 Si-O 결합이 Si-N 결합으로 치환되도록 하여 후속 N 원자를 질화막 성장 공정시의 씨드(seed)로 작용하도록 한다.Then, as shown in FIG. 2D, the surface of the lower oxide film 106 is subjected to plasma treatment using N 2 gas so that the Si—O bond on the surface of the lower oxide film 106 is replaced with a Si—N bond, thereby replacing subsequent N atoms. It serves as a seed during the nitride film growth process.
상기의 씨드를 이용하여 도2e에 도시된 바와 같이 상기 플라즈마 처리된 하부 산화막(106') 상부에 N 원자의 씨드를 이용하여 질화막(108)을 성장시킨다. 이때 상기 플라즈마 공정에 의해 N 씨드층을 형성한 후 질화막을 성장시키기 때문에 우수한 막질의 결정질 질화막이 형성된다.As shown in FIG. 2E, the nitride film 108 is grown using a seed of N atoms on the plasma-treated lower oxide film 106 ′ using the seed. At this time, since the nitride film is grown after the N seed layer is formed by the plasma process, an excellent crystalline nitride film is formed.
상기의 질화막(108)을 성장시킨 후 도2f에 도시된 바와 같이 상부 산화막(110)을 증착하여 ONO 유전체막(112)한다.After the nitride film 108 is grown, the upper oxide film 110 is deposited as shown in FIG. 2F to form the ONO dielectric film 112.
그런 다음, 도2g에 도시된 바와 같이 컨트롤 게이트 도전층으로 제 2 폴리실리콘막(114)을 증착한다.Then, a second polysilicon film 114 is deposited as the control gate conductive layer as shown in FIG. 2G.
이와 같은 본 발명에 의하면, 유전체막으로 이용되는 ONO막 형성 방법에 있어서, 하부 산화막을 형성한 후 N2가스를 이용한 플라즈마 처리에 의해 하부 산화막 표면의 Si-O 결합이 Si-N 결합으로 치환되도록 하여, 하부 산화막 표면의 N 원자를 씨드층으로 이용하여 질화막을 형성함으로써, 막질이 우수한 결정질의 질화막을 형성하여 ONO 유전체막의 특성을 향상시킬 수 있다.According to the present invention, in the method of forming the ONO film used as the dielectric film, after forming the lower oxide film, the Si-O bond on the surface of the lower oxide film is replaced by the Si-N bond by plasma treatment using N 2 gas. Thus, by forming a nitride film using N atoms on the lower oxide film surface as a seed layer, a crystalline nitride film having excellent film quality can be formed to improve the characteristics of the ONO dielectric film.
상기한 바와 같이 본 발명은 ONO 유전체막 형성시 질화막을 증착하기전 씨드층을 형성하여 씨드층을 바탕으로 우수한 결정질의 질화막을 형성함으로써 ONO 유전체막의 리텐션(Retion)특성을 향상시켜, 결국 소자의 신뢰성을 향상시킬 수 있는 이점이 있다.As described above, the present invention improves the retention characteristics of the ONO dielectric film by forming a seed layer before forming the nitride film during the formation of the ONO dielectric film, thereby forming an excellent crystalline nitride film based on the seed layer. There is an advantage to improve the reliability.
또한, ONO막의 질화막을 우수한 특성을 갖도록 형성함으로써 ONO막의 두께를 증가시키지 않고도, 유전체막의 특성을 향상시킴으로써 소자의 집적도를 향상시킬 수 있는 이점이 있다.In addition, since the nitride film of the ONO film is formed to have excellent characteristics, there is an advantage that the degree of integration of the device can be improved by improving the characteristics of the dielectric film without increasing the thickness of the ONO film.
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| KR100928372B1 (en) * | 2007-01-25 | 2009-11-23 | 가부시끼가이샤 도시바 | Nonvolatile Semiconductor Memory and Manufacturing Method Thereof |
| KR101396253B1 (en) * | 2011-09-30 | 2014-05-16 | 가부시키가이샤 히다치 고쿠사이 덴키 | Method of manufacturing semiconductor device, method of processing substrate, substrate processing apparatus and non-transitory computer-readable recording medium |
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| Publication number | Priority date | Publication date | Assignee | Title |
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| KR100928372B1 (en) * | 2007-01-25 | 2009-11-23 | 가부시끼가이샤 도시바 | Nonvolatile Semiconductor Memory and Manufacturing Method Thereof |
| KR101396253B1 (en) * | 2011-09-30 | 2014-05-16 | 가부시키가이샤 히다치 고쿠사이 덴키 | Method of manufacturing semiconductor device, method of processing substrate, substrate processing apparatus and non-transitory computer-readable recording medium |
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