KR20040079172A - Method for forming dielectric layer of semiconductor device - Google Patents

Method for forming dielectric layer of semiconductor device Download PDF

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Publication number
KR20040079172A
KR20040079172A KR1020030014114A KR20030014114A KR20040079172A KR 20040079172 A KR20040079172 A KR 20040079172A KR 1020030014114 A KR1020030014114 A KR 1020030014114A KR 20030014114 A KR20030014114 A KR 20030014114A KR 20040079172 A KR20040079172 A KR 20040079172A
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KR
South Korea
Prior art keywords
film
forming
oxide film
semiconductor device
lower oxide
Prior art date
Application number
KR1020030014114A
Other languages
Korean (ko)
Inventor
전재규
Original Assignee
주식회사 하이닉스반도체
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 주식회사 하이닉스반도체 filed Critical 주식회사 하이닉스반도체
Priority to KR1020030014114A priority Critical patent/KR20040079172A/en
Publication of KR20040079172A publication Critical patent/KR20040079172A/en

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Classifications

    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L27/00Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
    • H01L27/04Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body
    • H01L27/10Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including a plurality of individual components in a repetitive configuration
    • H01L27/105Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including a plurality of individual components in a repetitive configuration including field-effect components
    • H01L27/112Read-only memory structures [ROM] and multistep manufacturing processes therefor
    • H01L27/115Electrically programmable read-only memories; Multistep manufacturing processes therefor
    • H01L27/11517Electrically programmable read-only memories; Multistep manufacturing processes therefor with floating gate
    • H01L27/11526Electrically programmable read-only memories; Multistep manufacturing processes therefor with floating gate characterised by the peripheral circuit region
    • H01L27/11531Simultaneous manufacturing of periphery and memory cells
    • H01L27/11534Simultaneous manufacturing of periphery and memory cells including only one type of peripheral transistor
    • H01L27/11541Simultaneous manufacturing of periphery and memory cells including only one type of peripheral transistor with a floating-gate layer also being used as part of the peripheral transistor
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L27/00Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
    • H01L27/04Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body
    • H01L27/10Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including a plurality of individual components in a repetitive configuration
    • H01L27/105Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including a plurality of individual components in a repetitive configuration including field-effect components
    • H01L27/112Read-only memory structures [ROM] and multistep manufacturing processes therefor
    • H01L27/115Electrically programmable read-only memories; Multistep manufacturing processes therefor
    • H01L27/11517Electrically programmable read-only memories; Multistep manufacturing processes therefor with floating gate
    • H01L27/11526Electrically programmable read-only memories; Multistep manufacturing processes therefor with floating gate characterised by the peripheral circuit region
    • H01L27/11531Simultaneous manufacturing of periphery and memory cells
    • H01L27/11534Simultaneous manufacturing of periphery and memory cells including only one type of peripheral transistor
    • H01L27/11543Simultaneous manufacturing of periphery and memory cells including only one type of peripheral transistor with a tunnel dielectric layer also being used as part of the peripheral transistor
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/28Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
    • H01L21/28008Making conductor-insulator-semiconductor electrodes
    • H01L21/28017Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon
    • H01L21/28158Making the insulator
    • H01L21/28167Making the insulator on single crystalline silicon, e.g. using a liquid, i.e. chemical oxidation
    • H01L21/28194Making the insulator on single crystalline silicon, e.g. using a liquid, i.e. chemical oxidation by deposition, e.g. evaporation, ALD, CVD, sputtering, laser deposition

Abstract

The present invention provides a dielectric of a semiconductor device for forming a nitride film having excellent crystallinity by performing N 2 plasma treatment on the lower oxide film surface to replace O atoms on the lower oxide film surface with N atoms and growing the nitride film using the seed layer. A method of forming a dielectric film of a semiconductor device using an ONO structure, comprising: forming an N atom seed layer on a lower oxide film surface after forming a lower oxide film, and growing a nitride film on the lower oxide film; And forming an upper oxide film on the nitride film.

Description

METHODS FOR FORMING DIELECTRIC LAYER OF SEMICONDUCTOR DEVICE

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for forming a dielectric film of a semiconductor device, and more particularly, to form an ONO film composed of an excellent crystalline nitride film by growing a nitride film by using a seed of N atoms used in a nonvolatile memory product. The present invention relates to a method for forming a dielectric film of a semiconductor device capable of improving characteristics.

In general, a dielectric film of ONO (Oxide / Nitride / Oxide) structure is used as a dielectric film of a semiconductor memory device, such as a DRAM (Dynamic Random Access Memory) or a non-volatile memory (NVM). That is, a structure in which an oxide film / nitride film / oxide film is sequentially stacked is used as the dielectric film.

In particular, since the EPROM or FLASH EPROM, which is a nonvolatile memory device, is characterized by small size, large capacity, and low power consumption, an ONO film having excellent retention characteristics is required to drive the memory stably over a long period of time at low voltage. The retention characteristic of the ONO film is influenced by the respective layers of the lower oxide film, the nitride film, and the upper oxide film, which are each of the ONO layers, but most of them are affected by the nitride film.

The problem at the time of forming the dielectric film of the semiconductor device according to the prior art will be described with reference to the drawings shown below.

1A to 1F are cross-sectional views showing a method of forming a dielectric film of a semiconductor device according to the prior art.

First, as shown in FIG. 1A, an active region is defined on a silicon substrate 100 by an isolation region, for example, shallow trench isolation (STI). The silicon oxide film is grown to a predetermined thickness in the active region to form the tunnel oxide film 102.

Subsequently, as illustrated in FIG. 1B, a first polysilicon film 104 is deposited as a floating gate conductive layer on the tunnel oxide film 102.

Then, as shown in FIG. 1C, the surface of the polysilicon layer is oxidized, or the lower oxide film 106 is formed using a deposition method. At this time, the silicon oxide of the first polysilicon film 104 and the oxide of the lower oxide film are bonded to the surface of the lower oxide film 106 by Si-O like the A portion.

Then, as illustrated in FIG. 1D, a nitride film 108 is deposited on the lower oxide film 106, and an upper oxide film 110 is deposited as shown in FIG. 1E to form an ONO dielectric film 112. .

Then, as shown in FIG. 1F, a second polysilicon film 114 is deposited as the control gate conductive layer.

As described above, in the case of forming the dielectric film by the prior art, there is a problem that the thickness of the ONO film needs to be thicker than necessary in order to suppress leakage current because the nitride film, which is the most important parameter in retention characteristics, is not excellent. there was.

As a result, when the thickness of the insulating layer becomes thick, the write and erase voltages of the memory device inevitably increase, and as a result, the tunnel oxide film has to be relatively thick to withstand the high voltage.

In order to solve the above problems, the present invention forms a lower oxide film, and a N 2 plasma treatment on the lower oxide film surface to replace the O atoms of the lower oxide film surface with N atoms to form a nitride film using the seed layer, It is an object of the present invention to provide a method for forming a dielectric film of a semiconductor device capable of forming this excellent nitride film.

1A to 1F are cross-sectional views showing a method of forming a dielectric film of a semiconductor device according to the prior art.

2A to 2G are cross-sectional views illustrating a method of forming a dielectric film of a semiconductor device according to the present invention.

-Explanation of symbols for the main parts of the drawings-

100 silicon substrate 102 tunnel oxide film

104: first polysilicon film 106: lower oxide film

106 ': plasma-treated lower oxide film 108: nitride film

110: upper oxide film 112: ONO film

A: Si-O bond B: Si-N bond

In order to achieve the above object, the present invention provides a method for forming a dielectric film of a semiconductor device using an ONO structure, the method comprising: forming an N atom seed layer on a surface of a lower oxide film after forming a lower oxide film; And growing an nitride film and forming an upper oxide film on the nitride film.

According to the method for forming a dielectric film of the semiconductor device of the present invention, an excellent crystalline nitride film is formed by performing an N 2 plasma process on the surface of the lower oxide film to replace O atoms with N atoms and growing a nitride film using the N atoms as seed layers. Can be formed to improve the characteristics of the ONO film.

In the method for forming a dielectric film of a semiconductor device of the present invention as described above, the N atom seed layer is preferably formed by performing an N 2 plasma process.

Hereinafter, exemplary embodiments of the present invention will be described with reference to the accompanying drawings. In addition, the present embodiment is not intended to limit the scope of the present invention, but is presented by way of example only and the same parts as in the conventional configuration using the same reference numerals and names.

2A to 2G are cross-sectional views illustrating a method of forming a dielectric film of a semiconductor device according to the present invention.

First, as shown in FIG. 2A, an active region is defined on the silicon substrate 100 by an isolation region, for example, shallow trench isolation (STI). The silicon oxide film is grown to a predetermined thickness in the active region to form the tunnel oxide film 102.

Subsequently, a first polysilicon film 104 is deposited as a floating gate conductive layer on the tunnel oxide film 102 as shown in FIG. 2B, and the surface of the polysilicon layer is oxidized as shown in FIG. 2C. The lower oxide film 106 is formed using a deposition method.

Then, as shown in FIG. 2D, the surface of the lower oxide film 106 is subjected to plasma treatment using N 2 gas so that the Si—O bond on the surface of the lower oxide film 106 is replaced with a Si—N bond, thereby replacing subsequent N atoms. It serves as a seed during the nitride film growth process.

As shown in FIG. 2E, the nitride film 108 is grown using a seed of N atoms on the plasma-treated lower oxide film 106 ′ using the seed. At this time, since the nitride film is grown after the N seed layer is formed by the plasma process, an excellent crystalline nitride film is formed.

After the nitride film 108 is grown, the upper oxide film 110 is deposited as shown in FIG. 2F to form the ONO dielectric film 112.

Then, a second polysilicon film 114 is deposited as the control gate conductive layer as shown in FIG. 2G.

According to the present invention, in the method of forming the ONO film used as the dielectric film, after forming the lower oxide film, the Si-O bond on the surface of the lower oxide film is replaced by the Si-N bond by plasma treatment using N 2 gas. Thus, by forming a nitride film using N atoms on the lower oxide film surface as a seed layer, a crystalline nitride film having excellent film quality can be formed to improve the characteristics of the ONO dielectric film.

As described above, the present invention improves the retention characteristics of the ONO dielectric film by forming a seed layer before forming the nitride film during the formation of the ONO dielectric film, thereby forming an excellent crystalline nitride film based on the seed layer. There is an advantage to improve the reliability.

In addition, since the nitride film of the ONO film is formed to have excellent characteristics, there is an advantage that the degree of integration of the device can be improved by improving the characteristics of the dielectric film without increasing the thickness of the ONO film.

Claims (2)

  1. In the method of forming a dielectric film of a semiconductor device using an ONO structure,
    Forming an N atom seed layer on the surface of the lower oxide layer after forming the lower oxide layer;
    Growing a nitride film on the lower oxide film;
    Forming an upper oxide film on the nitride film
    A method of forming a dielectric film of a semiconductor device, comprising.
  2. The method of claim 1,
    And the N atom seed layer is formed by performing an N 2 plasma process.
KR1020030014114A 2003-03-06 2003-03-06 Method for forming dielectric layer of semiconductor device KR20040079172A (en)

Priority Applications (1)

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Publications (1)

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Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100928372B1 (en) * 2007-01-25 2009-11-23 가부시끼가이샤 도시바 Nonvolatile Semiconductor Memory and Manufacturing Method Thereof
KR101396253B1 (en) * 2011-09-30 2014-05-16 가부시키가이샤 히다치 고쿠사이 덴키 Method of manufacturing semiconductor device, method of processing substrate, substrate processing apparatus and non-transitory computer-readable recording medium

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100928372B1 (en) * 2007-01-25 2009-11-23 가부시끼가이샤 도시바 Nonvolatile Semiconductor Memory and Manufacturing Method Thereof
KR101396253B1 (en) * 2011-09-30 2014-05-16 가부시키가이샤 히다치 고쿠사이 덴키 Method of manufacturing semiconductor device, method of processing substrate, substrate processing apparatus and non-transitory computer-readable recording medium

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