KR20030097343A - Method for forming the Isolation Layer of Semiconductor Device - Google Patents

Method for forming the Isolation Layer of Semiconductor Device Download PDF

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KR20030097343A
KR20030097343A KR1020020034663A KR20020034663A KR20030097343A KR 20030097343 A KR20030097343 A KR 20030097343A KR 1020020034663 A KR1020020034663 A KR 1020020034663A KR 20020034663 A KR20020034663 A KR 20020034663A KR 20030097343 A KR20030097343 A KR 20030097343A
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nitride
trench
forming
layer
film
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KR1020020034663A
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Korean (ko)
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박효식
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주식회사 하이닉스반도체
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Publication of KR20030097343A publication Critical patent/KR20030097343A/en

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76—Making of isolation regions between components
    • H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
    • H01L21/76224—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using trench refilling with dielectric materials
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02041—Cleaning
    • H01L21/02057—Cleaning during device manufacture
    • H01L21/0206—Cleaning during device manufacture during, before or after processing of insulating layers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/302—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
    • H01L21/306—Chemical or electrical treatment, e.g. electrolytic etching
    • H01L21/308—Chemical or electrical treatment, e.g. electrolytic etching using masks
    • H01L21/3083—Chemical or electrical treatment, e.g. electrolytic etching using masks characterised by their size, orientation, disposition, behaviour, shape, in horizontal or vertical plane
    • H01L21/3086—Chemical or electrical treatment, e.g. electrolytic etching using masks characterised by their size, orientation, disposition, behaviour, shape, in horizontal or vertical plane characterised by the process involved to create the mask, e.g. lift-off masks, sidewalls, or to modify the mask, e.g. pre-treatment, post-treatment
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
    • H01L21/8232—Field-effect technology
    • H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
    • H01L21/823481—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type isolation region manufacturing related aspects, e.g. to avoid interaction of isolation region with adjacent structure

Abstract

PURPOSE: A method for fabricating an isolation layer of a semiconductor device is provided to prevent a liner nitride layer from being lost by a phosphoric acid solution in removing a pad nitride layer by forming a nitride spacer on the sidewall of a trench by a shallow trench isolation process. CONSTITUTION: After a pad oxide layer(210) and a pad nitride layer are sequentially deposited on a silicon substrate(200) having a predetermined underlying structure, a photoresist layer pattern is formed. The first trench is formed by using the photoresist layer pattern as a mask. After a nitride layer is deposited on the resultant structure, a blanket etch process is performed to form the nitride spacer(250). The second trench is formed by using the nitride spacer as a hard mask. After a sacrificial oxide layer is formed on the sidewall of the second trench, the liner nitride layer(280) is formed. A buried oxide layer is deposited on the resultant structure to fill the trench. A planarization process is performed on the resultant structure so that the thickness of a nitride material left in a vertical direction is the same as that in a horizontal direction. The nitride materials left in the vertical and horizontal directions are removed by using a phosphoric acid solution to form an isolation layer(300).

Description

반도체 소자의 소자분리막 형성방법{Method for forming the Isolation Layer of Semiconductor Device}Method for forming the isolation layer of semiconductor device

본 발명은 반도체 소자의 소자분리막 형성방법에 관한 것으로, 보다 상세하게는, 트렌치를 이용한 소자분리막 형성 공정에 있어서, 트렌치 측벽 상부에 질화스페이서를 형성함으로써, 후속 패드 질화막 제거 시, 라이너(liner) 나이트라이드막이 인산용액으로 인하여 손실되는 것을 방지하고, 소자분리막 모서리 부분의 모우트를 형성을 방지하여 반도체 소자의 전기적 열화를 방지하는 것을 특징으로 하는 반도체 소자의 소자분리막 형성방법에 관한 것이다.The present invention relates to a method of forming a device isolation film of a semiconductor device, and more particularly, in a device isolation film formation process using a trench, by forming a nitride spacer on the upper sidewall of the trench, a liner knight is removed when the subsequent pad nitride film is removed. The present invention relates to a method of forming a device isolation film of a semiconductor device, characterized in that the film is prevented from being lost due to a phosphate solution and prevents the formation of a moat at the corner of the device isolation film to prevent electrical degradation of the semiconductor device.

일반적으로, 실리콘기판 상에 트렌지스터와 커패시터등을 형성하기 위하여 실리콘기판에는 전기적으로 통전이 가능한 활성영역과 전기적으로 통전되는 것을 방지하고 소자를 서로 분리하도록 하는 소자분리영역을 형성하게 된다.In general, in order to form transistors, capacitors, and the like on a silicon substrate, an silicon isolation region is formed in the silicon substrate to prevent electrically conduction from an electrically conductable active region and to separate devices from each other.

이와 같이, 실리콘기판에 일정한 깊이를 갖는 트렌치를 형성한 후, 이 트렌치에 산화막을 증착시킨 후 화학기계적연마공정으로 이 산화막의 불필요한 부분을 식각하므로 소자분리영역을 반도체 기판에 형성시키는 STI(Shallow Trench Isolation)공정이 최근에 많이 이용되고 있다.As such, after forming a trench having a predetermined depth in the silicon substrate and depositing an oxide film on the trench, an unnecessary portion of the oxide film is etched by a chemical mechanical polishing process to form an isolation region in the semiconductor substrate. Isolation) has been widely used in recent years.

도 1은 종래 반도체소자의 소자분리막 형성방법에 의해 형성된 소자분리막의 문제점을 설명하기 위해 나타낸 단면도이며, 도 2는 도 1의 종래 반도체소자의 소자분리막 형성방법에 의해 형성된 소자분리막의 문제점을 더 구체화하여 설명하기 위해 나타낸 사진이다.1 is a cross-sectional view illustrating a problem of a device isolation film formed by a device isolation film forming method of a conventional semiconductor device, and FIG. 2 further illustrates a problem of device isolation film formed by a device isolation film forming method of the conventional semiconductor device of FIG. 1. The picture is shown to explain.

도 1에 도시된 바와 같이, 반도체기판(100) 상에 패드산화막(110)과 패드질화막(미도시함)을 순차적으로 적층한 후 노광 및 식각 공정이 진행되어 반도체기판 내에 트렌치(미도시함) 가 형성되었다.As shown in FIG. 1, after the pad oxide layer 110 and the pad nitride layer (not shown) are sequentially stacked on the semiconductor substrate 100, exposure and etching processes are performed to form trenches in the semiconductor substrate (not shown). Was formed.

이어서, 상기 결과물에 라이너(Liner) 나이트라이드막(130)을 증착하고, 고밀도 플라즈마 산화막(미도시함)을 증착하여 트렌치를 매립한 후, 평탄화 공정을 진행함으로써서 트렌치와 트렌치 간이 분리되었다.Subsequently, a liner nitride film 130 was deposited on the resultant, a high density plasma oxide film (not shown) was deposited to fill the trench, and the trench and the trench were separated by a planarization process.

그리고, 상기 결과물 상의 패드 질화막(미도시함)을 인산용액을 사용하여 오버(over) 식각하여 제거함으로써, 소자분리막(140)이 형성되었다.In addition, the device isolation layer 140 was formed by over-etching the pad nitride layer (not shown) on the resultant using a phosphoric acid solution.

그런데, 상기와 같은 종래 반도체소자의 소자분리막 형성방법을 이용하게 되면, 상기 패드 질화막 제거 시, 패드 질화막을 완전하게 제거하기 위해 오버 식각을 진행하는데 이때, 86%의 인산용액(H3PO4)이 라이너 나이트라이드막을 따라 트렌치 내에 침투되어 "A"와 같이, 라이너 나이트라이드막을 식각하는 문제점이 있었다. 상기 "A"와 같이 라이너 나이트라이드막이 식각된 부위를 도 2의 TEM 사진을 통하여 더욱 구체화하여 나타내었다.However, when the device isolation film forming method of the conventional semiconductor device as described above is used, when the pad nitride film is removed, the over etching is performed to completely remove the pad nitride film. At this time, 86% of a phosphate solution (H 3 PO 4 ) is used. This penetrates into the trench along the liner nitride film to etch the liner nitride film, such as "A". The portion where the liner nitride film was etched as shown in "A" was further shown through the TEM photograph of FIG. 2.

그 결과, 소자분리막 모서리 부분에 모우트(moat)를 형성하여 반도체소자의 전기적 특성 및 신뢰성을 저하시키는 문제점이 있었다.As a result, there is a problem in that a moat is formed at the corners of the device isolation layer, thereby deteriorating the electrical characteristics and the reliability of the semiconductor device.

본 발명은 상기와 같은 문제점을 해결하기 위해 안출된 것으로, 본 발명의 목적은 얕은 트렌치 소자격리(Sallow Trench Isolation; 이하 "STI"라 한다)공정에의해 트렌치를 이용한 소자분리막 형성 공정에 있어서, 트렌치 측벽 상부에 질화스페이서를 형성함으로써, 후속 패드 질화막 제거 시, 라이너(liner) 나이트라이드막이 인산용액으로 인하여 손실되는 것을 방지하고, 소자분리막 모서리 부분의 모우트를 형성을 방지하여 반도체 소자의 전기적 열화를 방지하도록 하는 반도체 소자의 소자분리막 형성방법을 제공하는 것에 있다.The present invention has been made to solve the above problems, an object of the present invention is to trench in the device isolation film forming process using a trench by a shallow trench isolation (STI) process; By forming a nitride spacer on the upper sidewall, the liner nitride film is prevented from being lost due to the phosphate solution during the subsequent removal of the pad nitride film, and the formation of a moor at the edge of the device isolation film is prevented to prevent electrical degradation of the semiconductor device. The present invention provides a method for forming a device isolation film of a semiconductor device to prevent it.

도 1은 종래 반도체소자의 소자분리막 형성방법에 의해 형성된 소자분리막의 문제점을 설명하기 위해 나타낸 단면도이다.1 is a cross-sectional view illustrating a problem of a device isolation film formed by a device isolation film formation method of a conventional semiconductor device.

도 2는 도 1의 종래 반도체소자의 소자분리막 형성방법에 의해 형성된 소자분리막의 문제점을 더 구체화하여 설명하기 위해 나타낸 사진이다.FIG. 2 is a photograph for explaining the problem of the device isolation film formed by the device isolation film formation method of the conventional semiconductor device of FIG. 1.

도 3a 내지 도 3f는 본 발명에 따른 반도체 소자의 소자분리막 형성방법을 설명하기 위해 순차적으로 나타낸 단면도이다.3A to 3F are cross-sectional views sequentially illustrating a method of forming a device isolation film of a semiconductor device according to the present invention.

-- 도면의 주요부분에 대한 부호의 설명 ---Explanation of symbols for the main parts of the drawing-

200 : 반도체기판 210 : 패드산화막200: semiconductor substrate 210: pad oxide film

220 : 패드질화막 230 : 감광막220: pad nitride film 230: photosensitive film

240 : 제1트렌치 250 : 질화스페이서240: first trench 250: nitride spacer

260 : 제2트렌치 270 : 라이너 산화막260: second trench 270: liner oxide film

280 : 라이너 나이트라이드막 290 : 고밀도 플라즈마 산화막280: liner nitride film 290: high density plasma oxide film

300 : 소자분리막300: device isolation film

상기 목적을 달성하기 위하여, 본 발명은 소정의 하부구조를 가지고 있는 실리콘 기판 상에 패드산화막과 패드질화막을 순차적으로 증착한 후 감광막 패턴을 형성하는 단계와, 상기 감광막 패턴을 마스크로 하여 제1 트렌치를 형성하는 단계와, 상기 결과물 전체에 질화막을 증착한 후, 전면식각 공정을 진행하여 질화스페이서를 형성하는 단계와, 상기 질화스페이서를 하드마스크로 이용하여 제2 트렌치를 형성하는 단계와, 상기 트렌치 측벽에 희생산화막을 형성한 후, 라이너 나이트라이드막을 형성하는 단계와, 상기 결과물 상에 매립산화막을 증착하여 트렌치를 매립한 후, 수직방향으로 남은 질화물과 수평방향으로 남은 질화물의 두께가 동일하도록 결과물을 평탄화 시키는 단계와, 상기 수직방향과 수평방향으로 동일하게 잔류된 질화물을 인산용액을 사용하여 제거하여 소자분리막을 형성하는 단계를 포함하여 이루어진 것을 특징으로 하는 반도체 소자의 소자분리막 형성방법을 제공한다.In order to achieve the above object, the present invention is a step of sequentially depositing a pad oxide film and a pad nitride film on a silicon substrate having a predetermined substructure and forming a photoresist pattern, the first trench using the photoresist pattern as a mask Forming a nitride layer, depositing a nitride film on the entire product, and performing a front etching process to form a nitride spacer; forming a second trench using the nitride spacer as a hard mask; and forming the trench. After the sacrificial oxide film is formed on the sidewalls, a liner nitride film is formed, and the buried oxide film is deposited on the resultant to fill the trench, and the resulting nitride has the same thickness as the nitride remaining in the vertical direction. Planarizing the phosphorus and phosphate the remaining nitride in the vertical and horizontal directions Comprising the step of removing by using a liquid to form a device isolation film to provide a device isolation method for forming a semiconductor device characterized in that is made.

또한 바람직하게는, 상기 제1트렌치 형성 시, 실리콘기판 상부로부터100~200Å 깊이로 형성하며, 상기 질화스페이서는 100~200Å의 질화물을 증착한 후, 이를 전면식각하여 형성하는 것을 특징으로 한다.Also preferably, the first trench may be formed to a depth of 100 to 200 microseconds from an upper portion of the silicon substrate, and the nitride spacer may be formed by etching the entire surface after depositing 100 to 200 microns of nitride.

이하, 첨부한 도면을 참조하여 본 발명의 바람직한 실시예에 대해 상세히 설명하고자 한다.Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings.

도 3a 내지 도 3f는 본 발명에 따른 반도체 소자의 소자분리막 형성방법을 순차적으로 나타낸 단면도이다.3A through 3F are cross-sectional views sequentially illustrating a method of forming an isolation layer in a semiconductor device according to the present invention.

도 3a에 도시된 바와 같이, 소정의 하부구조를 가지고 있는 실리콘 기판(200) 상에 패드산화막(210)과 패드질화막(220)을 순차적으로 증착한 후 패드질화막(220) 상에 트렌치를 형성하기 위한 감광막(230) 패턴을 형성한다.As shown in FIG. 3A, after the pad oxide film 210 and the pad nitride film 220 are sequentially deposited on the silicon substrate 200 having a predetermined substructure, the trench is formed on the pad nitride film 220. A photoresist film 230 pattern is formed.

그리고, 상기 감광막(230) 패턴을 마스크로 하여 트렌치영역(미도시함)의 패드질화막(220)과 패드산화막(210) 및 실리콘기판(200)을 건식식각해서 제1트렌치(240)를 형성한다.The first trench 240 may be formed by dry etching the pad nitride layer 220, the pad oxide layer 210, and the silicon substrate 200 in the trench region (not shown) using the photoresist pattern 230 as a mask. .

이때, 상기 제1트렌치(240)는 실리콘기판(200) 상부로부터 100~200Å 깊이정도까지 식각하여 형성한다.In this case, the first trench 240 is formed by etching to the depth of 100 ~ 200200 from the top of the silicon substrate 200.

이어서, 도 3b에 도시된 바와 같이, 상기 감광막(230)을 제거한 후, 결과물 전체에 100~200Å 정도의 질화물(미도시함)을 증착한 후, 이를 전면식각하여 제1트렌치(240) 내부 측벽에 질화스페이서(250)를 형성한다.Subsequently, as shown in FIG. 3B, after removing the photoresist layer 230, nitride (not shown) of about 100 to about 200 에 is deposited on the entire resultant, and then, the entire surface is etched to form an inner sidewall of the first trench 240. The nitride spacer 250 is formed on the substrate.

그리고, 도 3c에 도시된 바와 같이, 상기 질화스페이서(250)을 하드마스크로 식각공정을 진행하여 제2트렌치(260)를 형성한다.As illustrated in FIG. 3C, the nitride spacer 250 is etched with a hard mask to form a second trench 260.

그 후, 도 3d에 도시된 바와 같이, 상기 제2트렌치(260) 형성 식각 공정에 의해 손상된 실리콘 표면의 격자구조를 보상하기 위해 실리콘 표면을 희생산화시켜서 희생산화막(270)을 형성한 후, 라이너 나이트라이드막(280)을 증착하여 후속 열처리 공정이나 다른 공정 진행 시, 스트레스를 완화하여 소자의 신뢰성과 전하보존 시간을 향상시킨다.Thereafter, as shown in FIG. 3D, the sacrificial oxide film 270 is formed by sacrificial oxidation of the silicon surface to compensate for the lattice structure of the silicon surface damaged by the second trench 260 formation etching process. The nitride film 280 is deposited to reduce stress during subsequent heat treatment or other processes, thereby improving reliability and charge retention time of the device.

그리고, 상기 결과물 상에 매립산화막(290)으로 고밀도플라즈마-화학기상증착(HDP-CVD) 산화막을 이용하여 제2트렌치(미도시함)를 매립한다.Then, a second trench (not shown) is buried in the resultant buried oxide film 290 using a high density plasma-chemical vapor deposition (HDP-CVD) oxide film.

이어, 도 3e에 도시된 바와 같이, 상기 결과물 상에 수직방향으로 남은 패드질화막(220)의 두께와 수평방향으로 남은 질화스페이서(250) 및 라이너 나이트라이드막(280)의 두께가 동일하도록 결과물을 화학기계적연마 공정을 진행하여 평탄화 시킨다.As shown in FIG. 3E, the resultant is formed such that the thickness of the pad nitride layer 220 remaining in the vertical direction and the thickness of the nitride spacer 250 and the liner nitride layer 280 remaining in the horizontal direction are the same. The chemical mechanical polishing process is performed to planarize.

그 후, 도 3f에 도시된 바와 같이, 상기 수직방향으로 남은 패드질화막(220)과 수평방향으로 남은 질화스페이서(250) 및 라이너 나이트라이드막(280)인 질화물을 인산용액을 사용하여 제거하여 소자분리막(300)을 형성한다.After that, as shown in FIG. 3F, the nitrides of the pad nitride film 220 remaining in the vertical direction and the nitride spacer 250 and the liner nitride film 280 remaining in the horizontal direction are removed using a phosphoric acid solution. The separator 300 is formed.

이때, 상기 수직방향으로 남은 패드질화막(220)과 수평방향으로 남은 질화스페이서(250) 및 라이너 나이트라이드막(280)의 두께가 동일하므로, 인산용액에 의한 제거 시, 식각율이 동일하여 나이트라이드막(280)의 손실되지 않아 소자분리막(300)의 모서리에 모우트 형상이 발생하는 것을 방지된다.At this time, since the thicknesses of the pad nitride film 220 remaining in the vertical direction and the nitride spacer 250 and the liner nitride film 280 remaining in the horizontal direction are the same, when the removal is performed by the phosphate solution, the etching rate is the same. Since the film 280 is not lost, a moat shape is prevented from occurring at the edge of the device isolation film 300.

따라서, 상기한 바와 같이, 본 발명에 따른 반도체 소자의 소자분리막 형성방법을 이용하게 되면, 얕은 트렌치 소자격리(Sallow Trench Isolation; 이하 "STI"라 한다)공정에 의해 반도체기판에 소자분리막 프로파일(profile)을 구현하는 과정에서 트렌치 측벽 상부에 질화스페이서를 형성함으로써, 후속 패드 질화막 제거 시, 라이너(liner) 나이트라이드막이 인산용액으로 인하여 손실되는 것을 방지하고, 소자분리막 모서리 부분의 모우트를 형성을 방지하여 반도체 소자의 전기적 열화를 방지하도록 하는 효과가 있다.Therefore, as described above, when the device isolation film forming method of the semiconductor device according to the present invention is used, a device isolation film profile is formed on the semiconductor substrate by a shallow trench isolation (STI) process. By forming a nitride spacer on the trench sidewalls in the process of implementing a), the liner nitride film is prevented from being lost due to the phosphate solution during the subsequent removal of the pad nitride film, and the formation of the grooves at the corners of the device isolation layer is prevented. Therefore, there is an effect to prevent electrical deterioration of the semiconductor device.

Claims (3)

소정의 하부구조를 가지고 있는 실리콘 기판 상에 패드산화막과 패드질화막을 순차적으로 증착한 후 감광막 패턴을 형성하는 단계와;Sequentially depositing a pad oxide film and a pad nitride film on a silicon substrate having a predetermined substructure and forming a photoresist pattern; 상기 감광막 패턴을 마스크로 하여 제1 트렌치를 형성하는 단계와;Forming a first trench using the photoresist pattern as a mask; 상기 결과물 전체에 질화막을 증착한 후, 전면식각 공정을 진행하여 질화스페이서를 형성하는 단계와;Depositing a nitride film on the entirety of the resultant, and performing a front etching process to form a nitride spacer; 상기 질화스페이서를 하드마스크로 이용하여 제2 트렌치를 형성하는 단계와;Forming a second trench using the nitride spacer as a hard mask; 상기 제2 트렌치 측벽에 희생산화막을 형성한 후, 라이너 나이트라이드막을 형성하는 단계와;Forming a sacrificial oxide film on the sidewalls of the second trenches, and then forming a liner nitride film; 상기 결과물 상에 매립산화막을 증착하여 트렌치를 매립한 후, 수직방향으로 남은 질화물과 수평방향으로 남은 질화물의 두께가 동일하도록 결과물을 평탄화 시키는 단계와;Depositing the buried oxide film on the resultant to fill the trench, and then planarizing the resultant to have the same thickness of the nitride remaining in the vertical direction and the nitride remaining in the horizontal direction; 상기 수직방향과 수평방향으로 동일하게 잔류된 질화물을 인산용액을 사용하여 제거하여 소자분리막을 형성하는 단계를 포함하여 이루어진 것을 특징으로 하는 반도체 소자의 소자분리막 형성방법.And forming a device isolation film by removing the nitride which remains the same in the vertical direction and the horizontal direction by using a phosphate solution. 제 1항에 있어서, 상기 제1트렌치 형성 시, 실리콘기판 상부로부터 100~200Å 깊이로 형성되는 것을 특징으로 반도체 소자의 소자분리막 형성방법.The method of claim 1, wherein the first trenches are formed to a depth of 100 to 200 Å from an upper portion of the silicon substrate. 제 1항에 있어서, 상기 질화스페이서는 100~200Å의 질화물을 증착한 후, 이를 전면식각하여 형성되는 것을 특징으로 하는 반도체 소자의 소자분리막 형성방법.The method of claim 1, wherein the nitride spacer is formed by depositing 100 to 200 μm of nitride and then etching the entire surface.
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Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US9679935B2 (en) 2015-01-14 2017-06-13 Samsung Electronics Co., Ltd. Image sensors

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