KR20030081897A - Method of fabricating a semiconductor device with a silicon nitride having a high extinction coefficient - Google Patents
Method of fabricating a semiconductor device with a silicon nitride having a high extinction coefficient Download PDFInfo
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- KR20030081897A KR20030081897A KR1020020020345A KR20020020345A KR20030081897A KR 20030081897 A KR20030081897 A KR 20030081897A KR 1020020020345 A KR1020020020345 A KR 1020020020345A KR 20020020345 A KR20020020345 A KR 20020020345A KR 20030081897 A KR20030081897 A KR 20030081897A
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- 229910052581 Si3N4 Inorganic materials 0.000 title claims abstract description 54
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 title claims abstract description 54
- 239000004065 semiconductor Substances 0.000 title claims abstract description 22
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 17
- 230000008033 biological extinction Effects 0.000 title abstract 2
- 238000000034 method Methods 0.000 claims abstract description 36
- 229920002120 photoresistant polymer Polymers 0.000 claims abstract description 22
- 239000000758 substrate Substances 0.000 claims abstract description 7
- 238000005530 etching Methods 0.000 claims abstract description 6
- 238000010521 absorption reaction Methods 0.000 claims description 14
- 239000007789 gas Substances 0.000 claims description 10
- XLYOFNOQVPJJNP-UHFFFAOYSA-N water Substances O XLYOFNOQVPJJNP-UHFFFAOYSA-N 0.000 claims description 6
- 239000012159 carrier gas Substances 0.000 claims description 2
- 239000006117 anti-reflective coating Substances 0.000 abstract 1
- 239000011248 coating agent Substances 0.000 abstract 1
- 238000000576 coating method Methods 0.000 abstract 1
- 238000002955 isolation Methods 0.000 description 5
- 238000000059 patterning Methods 0.000 description 4
- 230000015572 biosynthetic process Effects 0.000 description 3
- QGZKDVFQNNGYKY-UHFFFAOYSA-N Ammonia Chemical compound N QGZKDVFQNNGYKY-UHFFFAOYSA-N 0.000 description 2
- 229910004205 SiNX Inorganic materials 0.000 description 1
- BLRPTPMANUNPDV-UHFFFAOYSA-N Silane Chemical compound [SiH4] BLRPTPMANUNPDV-UHFFFAOYSA-N 0.000 description 1
- 229910021529 ammonia Inorganic materials 0.000 description 1
- 230000003667 anti-reflective effect Effects 0.000 description 1
- 238000005229 chemical vapour deposition Methods 0.000 description 1
- 238000000151 deposition Methods 0.000 description 1
- 230000008021 deposition Effects 0.000 description 1
- 238000004518 low pressure chemical vapour deposition Methods 0.000 description 1
- 238000000206 photolithography Methods 0.000 description 1
- 229910000077 silane Inorganic materials 0.000 description 1
- 229910052710 silicon Inorganic materials 0.000 description 1
- 239000010703 silicon Substances 0.000 description 1
- 238000004088 simulation Methods 0.000 description 1
- 239000007787 solid Substances 0.000 description 1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/027—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34
- H01L21/033—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising inorganic layers
- H01L21/0334—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising inorganic layers characterised by their size, orientation, disposition, behaviour, shape, in horizontal or vertical plane
- H01L21/0337—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising inorganic layers characterised by their size, orientation, disposition, behaviour, shape, in horizontal or vertical plane characterised by the process involved to create the mask, e.g. lift-off masks, sidewalls, or to modify the mask, e.g. pre-treatment, post-treatment
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02107—Forming insulating materials on a substrate
- H01L21/02109—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates
- H01L21/02112—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer
- H01L21/02123—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon
- H01L21/0217—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon the material being a silicon nitride not containing oxygen, e.g. SixNy or SixByNz
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/027—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34
- H01L21/0271—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising organic layers
- H01L21/0273—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising organic layers characterised by the treatment of photoresist layers
- H01L21/0274—Photolithographic processes
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3105—After-treatment
- H01L21/311—Etching the insulating layers by chemical or physical means
- H01L21/31144—Etching the insulating layers by chemical or physical means using masks
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Abstract
Description
본 발명은 반도체 소자의 제조 방법에 관한 것이다. 더욱 상세하게, 본 발명은 높은 흡수율을 갖는 실리콘 질화막을 구비하는 반도체 소자의 제조 방법에 관한 것이다.The present invention relates to a method for manufacturing a semiconductor device. In more detail, this invention relates to the manufacturing method of the semiconductor element provided with the silicon nitride film which has a high water absorption.
반도체 제조 공정에 있어서 패터닝 공정은 필수적이다. 반도체 소자가 고집적화 됨에 따라, 패턴 간격이 0.1㎛이하의 미세한 패터닝이 요구된다. 실리콘 질화막을 마스크 층으로 사용하는 공정에서, 통상적으로 사용되는 실리콘 질화막은 흡수율이 0.01~0.1로 낮아 난반사가 심하다. 따라서, 실리콘 질화막 위에 통상적으로, 반사방지막(Anti-Refractive Layer, ARL)을 형성하여 난반사를 방지하고 미세한 패터닝이 가능케 한다.The patterning process is essential in the semiconductor manufacturing process. As semiconductor devices are highly integrated, fine patterning of pattern intervals of 0.1 m or less is required. In the process of using a silicon nitride film as a mask layer, a silicon nitride film that is commonly used has a low water absorption of 0.01 to 0.1, resulting in severe diffuse reflection. Therefore, an anti-reflective layer (ARL) is typically formed on the silicon nitride film to prevent diffuse reflection and enable fine patterning.
종래 기술의 한 예로, 도 1에서 종래의 얕은 트렌치(Shallow Trench Isolation, STI) 형성 과정 중에서 본 발명과 비교하기 위한 특징적인 부분만을 나타낸 공정단면도이다. 반도체 기판(1) 위에 버퍼 산화막(3)과 실리콘 질화막(5)을 적층한다. 상기 실리콘 질화막(5) 위에 반사방지막(7)을 적층하고 그 위에 포토레지스트를 도포하고 노광 및 현상 공정을 사용하여 포토레지스트 패턴(9)를 형성한다. 도시하지는 않았지만, 상기 포토 레지스트 패턴(9)를 이용하여 상기 반사방지막(7)과 상기 실리콘 질화막(5)를 차례대로 식각하여 반사 방지막 패턴과 실리콘 질화막 패턴을 형성한다. 상기 포토레지스트 패턴(9)를 제거하고 상기 반사방지막 패턴과 상기 실리콘 질화막 패턴을 식각 마스크로 사용하여 하부의 상기 버퍼산화막(3)과 상기 반도체 기판(1)을 차례대로 식각하여 트랜치를 형성한다. 후속 공정으로, 상기 반사방지막 패턴을 제거하고, 트랜치 내벽에 산화막을 형성하고 CVD 산화막을 전면에 형성하여 트랜치를 채운 후, CMP 공정을 통해 버퍼 산화막과 트랜치 안에 CVD 산화막을 남긴다.As an example of the prior art, FIG. 1 is a process cross-sectional view showing only a characteristic portion for comparison with the present invention in the conventional shallow trench formation process (STI). The buffer oxide film 3 and the silicon nitride film 5 are laminated on the semiconductor substrate 1. An antireflection film 7 is laminated on the silicon nitride film 5, a photoresist is applied thereon, and the photoresist pattern 9 is formed using an exposure and development process. Although not shown, the anti-reflection film 7 and the silicon nitride film 5 are sequentially etched using the photoresist pattern 9 to form an anti-reflection film pattern and a silicon nitride film pattern. The photoresist pattern 9 is removed, and the lower portion of the buffer oxide layer 3 and the semiconductor substrate 1 are sequentially etched using the anti-reflection layer pattern and the silicon nitride layer pattern as etch masks to form trenches. In a subsequent process, the anti-reflection film pattern is removed, an oxide film is formed on the trench inner wall, a CVD oxide film is formed on the entire surface to fill the trench, and the CVD oxide film is left in the buffer oxide film and the trench through the CMP process.
위의 종래 기술의 일 예에서 알 수 있듯이, 반사방지막을 추가로 형성하고 후에 제거해야하는 공정이 필요하기에 전체 공정이 복잡해지고, 이에 따른 생산비를 증가시키는 단점이 있다. 따라서 반사방지막이 필요치 않는 높은 흡수율을 갖는실리콘 질화막을 단일막으로서 사용하는 공정이 요구된다.As can be seen in the above example of the prior art, the overall process is complicated because it requires a process to additionally form and then remove the anti-reflection film, there is a disadvantage that increases the production cost accordingly. Therefore, there is a need for a process of using a silicon nitride film having a high absorption rate, which does not require an antireflection film, as a single film.
통상적으로, 상기와 같이 낮은 흡수율을 갖는 실리콘 질화막은 주로 반응로형(furnace-type) 설비내에서 LPCVD 방법으로 0.1~3 Torr의 낮은 압력에서 증착 형성되며, 증착시, 소스 가스로는 SiH2Cl2와 NH3등이 사용된다. 하지만 상기 반응로형 설비에서는 웨이퍼 뒷면에도 실리콘 질화막이 형성되며 이는 후속공정에서 웨이퍼 에지(edge)쪽으로 열뒤틀림(warpage)이 일어나 슬립(slip) 현상을 발생시킬 수 있다. 따라서 추가적으로 웨어퍼 뒷면의 실리콘 질화막을 제거해야 하는 단점이 있다.Typically, a silicon nitride film having a low water absorption as described above is mainly deposited by a LPCVD method at a low pressure of 0.1 to 3 Torr in a furnace-type apparatus, and during deposition, SiH 2 Cl 2 as a source gas. And NH 3 and the like are used. However, in the reactor type device, a silicon nitride film is formed on the back surface of the wafer, which may cause a thermal warpage toward the wafer edge in a subsequent process, thereby causing a slip phenomenon. Therefore, there is a disadvantage in that the silicon nitride film on the back side of the wafer is additionally removed.
따라서, 상기 문제점을 해결하기 위하여, 본 발명이 이루고자 하는 기술적 과제는 높은 흡수율을 갖는 실리콘 질화막을 구비하는 반도체 소자의 제조 방법을 제공하는데 있다.Accordingly, in order to solve the above problems, the present invention is to provide a method for manufacturing a semiconductor device having a silicon nitride film having a high absorption rate.
도 1은 종래의 얕은 트렌치 격리(Shallow Trench Isolation, STI) 형성 과정중 본 발명과 비교하기 위한 특징적인 부분을 나타낸 공정단면도이다.FIG. 1 is a cross-sectional view illustrating a characteristic portion of the conventional shallow trench isolation (STI) forming process for comparison with the present invention.
도 2는 본 발명의 바람직한 실시예에 의한 얕은 트렌치 격리 형성 방법의 특징적인 부분을 나타낸 공정 단면도이다.2 is a process cross-sectional view showing a characteristic portion of the shallow trench isolation formation method according to a preferred embodiment of the present invention.
도 3는 NH3/SiH4의 공급 유량비에 따라 형성되는 본발명의 실리콘 질화막의 흡수율을 나타내는 그래프이다.3 is a graph showing the water absorption rate of the silicon nitride film of the present invention formed according to the supply flow rate ratio of NH 3 / SiH 4.
상기 기술적 과제를 달성하기 위하여, 본 발명에 따른 반도체 소자의 제조 방법은 하부막질위에 형성되며, 마스크 층으로 쓰이며, 흡수율이 높은 실리콘 질화막 바로 위에, 반사방지막을 형성하지 않고 포토레지스트 패턴을 덮고 패터닝을 진행하는 단계를 포함하는 것을 특징으로 한다.In order to achieve the above technical problem, the method of manufacturing a semiconductor device according to the present invention is formed on the lower film quality, and used as a mask layer, directly on the silicon nitride film having a high absorption rate, covering the photoresist pattern without forming an antireflection film and patterning It characterized in that it comprises a step of proceeding.
본 발명의 일 예에 따르면, 실리콘 질화막을 포함하는 반도체 소자의 제조 방법은 하부 막질 위에 실리콘 질화막을 형성하고, 상기 실리콘 질화막의 바로 위에 포토레지스트를 도포하고 노광 및 현상하여 포토레지스트 패턴을 형성하고, 상기 포토레지스트 패턴을 이용하여 하부의 상기 실리콘 질화막을 식각하여 하드 마스크를 형성하고 상기 포토 레지스트 패턴을 제거하고, 그리고 상기 실리콘 질화막의 하드 마스크를 사용하여 상기 하부 막질을 식각하는 것을 구비한다. 상기 실리콘 질화막은 매엽식 설비에서, 소스가스로서 NH3와 SiH4를, 그리고 캐리어 가스로서 N2가스를 공급하여 형성된다.According to an embodiment of the present invention, in the method of manufacturing a semiconductor device including a silicon nitride film, a silicon nitride film is formed on a lower film quality, a photoresist is applied directly on the silicon nitride film, and exposed and developed to form a photoresist pattern. Etching the lower silicon nitride layer using the photoresist pattern to form a hard mask, removing the photoresist pattern, and etching the lower layer quality using the hard mask of the silicon nitride layer. The silicon nitride film is formed by supplying NH 3 and SiH 4 as a source gas and N 2 gas as a carrier gas in a sheet type facility.
상기 일 예에서, 상기 하부 막질은 버퍼 산화막이며, 상기 하부 막질 아래에 반도체 기판이 위치한다. 상기 실리콘 질화막은 흡수율이 0.25~0.65이며, 두께는 1000~1200Å이다. 상기 소스가스인 NH3와 SiH4의 공급비율은 NH3/SiH4가 1~20이다. 상기 실리콘 질화막은 주로 온도는 700~900℃, 압력은 240~310 Torr에서 CVD 방법을 이용하여 형성된다.In the above example, the lower layer is a buffer oxide layer, and a semiconductor substrate is positioned below the lower layer. The silicon nitride film has a water absorption of 0.25-0.65 and a thickness of 1000-1200 kPa. Feed rate of the source gas of NH 3 and SiH 4 is a NH 3 / SiH 4 1 ~ 20 . The silicon nitride film is mainly formed by using a CVD method at a temperature of 700 ~ 900 ℃, pressure is 240 ~ 310 Torr.
본 발명의 공정 조건 중 NH3/SiH4의 공급 유량비는 진행하고자 하는 공정의 디자인 룰에 따라서 결정된다. 즉, 실리콘 질화막이 필요한 공정에 있어서, 하부 막질의 종류와 두께, 실리콘 질화막의 두께, 포토레지스트의 종류와 두께, 굴절률등의 데이타를 입력값으로 하여 Solid C등의 시뮬레이션 툴(simulation tool)을 이용하여 반사율이 5%이하에 해당하는 적합한 흡수율을 구한다. 그리고, NH3/SiH4의 공급 유량비 대 형성된 실리콘 질화막의 흡수율과의 관계를 통해 적합한 NH3/SiH4의 공급 유량비를 구해낸다. 이렇게 구한 NH3/SiH4의 공급 유량비를 공정에 적용하여원하는 실리콘 질화막을 형성할 수 있다.The supply flow rate ratio of NH 3 / SiH 4 in the process conditions of the present invention is determined according to the design rule of the process to proceed. That is, in a process requiring a silicon nitride film, a simulation tool such as Solid C is used using data such as the type and thickness of the lower film quality, the thickness of the silicon nitride film, the type and thickness of the photoresist, and the refractive index as input values. Find the appropriate absorption, whose reflectance is less than 5%. Then, a suitable supply flow rate ratio of NH 3 / SiH 4 is determined through the relationship between the supply flow rate ratio of NH 3 / SiH 4 to the absorption rate of the formed silicon nitride film. The desired flow rate ratio of NH 3 / SiH 4 thus obtained can be applied to the process to form a desired silicon nitride film.
이하, 첨부한 도면들을 참조하여 본 발명의 바람직한 실시예를 상세히 설명하기로 한다. 바람직한 실시예로서 여러가지 반도체 제조 공정중에서 얕은 트렌치 격리 형성 방법을 예로 들고자 한다. 그러나, 본 발명은 여기서 설명되어지는 실시예에 한정되지 않고 실리콘 질화막을 포함하는 전반적인 반도체 제조 공정에 적용가능한 것은 당업자에게 명백할 것이다.Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings. As a preferred embodiment, a shallow trench isolation formation method in various semiconductor fabrication processes is taken as an example. However, it will be apparent to those skilled in the art that the present invention is not limited to the embodiments described herein and is applicable to the overall semiconductor manufacturing process including the silicon nitride film.
도 2는 본 발명의 바람직한 일 실시예에 의한 얕은 트렌치 격리 형성 방법의 특징적인 부분을 나타낸 공정 단면도이다. 도 2를 참고하여, 반도체 기판(10)위에 버퍼산화막(20)과 실리콘 질화막(30)을 순차적을 적층한다. 상기 실리콘 질화막(30)의 바로 위에 포토레지스트(40)을 도포하고 사진식각공정을 실시하여 상기 실리콘 질화막(30)을 패터닝한다. 포토레지스트를 제거하고, 패터닝된 상기 실리콘 질화막(30)을 하드마스크 층으로 사용하여 하부의 버퍼산화막(20)과 반도체 기판(10)을 순차적으로 식각하여 트렌치(50)를 형성한다. 후속 공정은 종래기술과 같다.2 is a process cross-sectional view showing a characteristic portion of the method for forming a shallow trench isolation in accordance with one preferred embodiment of the present invention. Referring to FIG. 2, the buffer oxide film 20 and the silicon nitride film 30 are sequentially stacked on the semiconductor substrate 10. The silicon nitride layer 30 is patterned by applying the photoresist 40 directly on the silicon nitride layer 30 and performing a photolithography process. The photoresist is removed, and the trench 50 is formed by sequentially etching the lower buffer oxide layer 20 and the semiconductor substrate 10 using the patterned silicon nitride layer 30 as a hard mask layer. The subsequent process is the same as in the prior art.
상기 실리콘 질화막(30)을 형성하는 방법의 일 예로, 상기 실리콘의 두께가 1000~1200Å이고, 굴절률이 2.5일때, 흡수율 0.4에 대해 도 3을 이용하여 NH3/SiH4의 공급 유량비를 구한다. 도 3은 소스가스로 암모니아(NH3)와 실레인(SiH4) 가스가 공급되었을때, NH3/SiH4의 공급 유량비에 따라 형성되는 실리콘 질화막의 흡수율 k를 실험적으로 구한 그래프이다. 이렇게 구해진 NH3/SiH4의 공급 유량비는 3.6정도이다. 매엽식 설비에서, 이러한 비율로 소스가스를 공급하고, 275Torr, 800℃에서 CVD방법으로 상기 실리콘 질화막(30)을 형성할 수 있었다. 여기서 구해진 실리콘 질화막의 구조식 SiNx에서 X는 대략 1.09이었다.As an example of a method of forming the silicon nitride film 30, when the thickness of the silicon is 1000 ~ 1200Å, the refractive index is 2.5, the supply flow rate ratio of NH 3 / SiH 4 to obtain the absorption rate 0.4 using FIG. 3 is a graph obtained by experimentally calculating the absorption rate k of the silicon nitride film formed according to the supply flow rate ratio of NH 3 / SiH 4 when ammonia (NH 3 ) and silane (SiH 4 ) gas are supplied as the source gas. The supply flow rate ratio of NH 3 / SiH 4 thus obtained is about 3.6. In the sheet type equipment, the source gas was supplied at this ratio, and the silicon nitride film 30 could be formed by CVD at 275 Torr and 800 ° C. X was approximately 1.09 in the structural formula SiNx of the silicon nitride film obtained here.
본 발명의 실리콘 질화막은 상기 얕은 트렌치 격리 형성 방법 외에도 게이트 전극, 비트라인등을 형성하는 공정등, 여러 공정에서 사용될 수 있다.The silicon nitride film of the present invention may be used in various processes, such as a process of forming a gate electrode, a bit line, etc., in addition to the shallow trench isolation method.
본 발명에 따르면, 높은 흡수율을 갖는 실리콘 질화막을 하드마스크 층으로 사용하여 반사방지막 사용 없이 반도체 소자의 제조과정을 단순화할 수 있으며 그에 따라 생산비를 절감할 수 있다.According to the present invention, by using a silicon nitride film having a high absorption rate as a hard mask layer, it is possible to simplify the manufacturing process of the semiconductor device without the use of an anti-reflection film, thereby reducing the production cost.
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