KR20030058615A - Method of fabricating thin film transistor - Google Patents
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- KR20030058615A KR20030058615A KR1020010089129A KR20010089129A KR20030058615A KR 20030058615 A KR20030058615 A KR 20030058615A KR 1020010089129 A KR1020010089129 A KR 1020010089129A KR 20010089129 A KR20010089129 A KR 20010089129A KR 20030058615 A KR20030058615 A KR 20030058615A
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- 239000010409 thin film Substances 0.000 title claims abstract description 24
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 14
- 238000000034 method Methods 0.000 claims abstract description 15
- 239000010408 film Substances 0.000 claims abstract description 10
- 239000011521 glass Substances 0.000 claims abstract description 8
- 239000000758 substrate Substances 0.000 claims abstract description 8
- 238000005530 etching Methods 0.000 claims abstract description 7
- 239000007772 electrode material Substances 0.000 claims abstract description 3
- 239000011241 protective layer Substances 0.000 claims description 32
- 239000010410 layer Substances 0.000 claims description 30
- 238000000151 deposition Methods 0.000 claims description 17
- 238000009832 plasma treatment Methods 0.000 claims description 10
- 238000000059 patterning Methods 0.000 claims description 8
- 239000007789 gas Substances 0.000 claims description 4
- IJGRMHOSHXDMSA-UHFFFAOYSA-N Atomic nitrogen Chemical compound N#N IJGRMHOSHXDMSA-UHFFFAOYSA-N 0.000 claims description 3
- XYFCBTPGUUZFHI-UHFFFAOYSA-N Phosphine Chemical compound P XYFCBTPGUUZFHI-UHFFFAOYSA-N 0.000 claims description 3
- 125000004435 hydrogen atom Chemical class [H]* 0.000 claims description 3
- 239000001257 hydrogen Substances 0.000 claims description 2
- 229910052739 hydrogen Inorganic materials 0.000 claims description 2
- 229910052757 nitrogen Inorganic materials 0.000 claims 1
- 229910000073 phosphorus hydride Inorganic materials 0.000 claims 1
- 239000004973 liquid crystal related substance Substances 0.000 abstract description 4
- 238000002161 passivation Methods 0.000 abstract 3
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 description 5
- 239000001301 oxygen Substances 0.000 description 5
- 229910052760 oxygen Inorganic materials 0.000 description 5
- 229910021417 amorphous silicon Inorganic materials 0.000 description 4
- 230000008021 deposition Effects 0.000 description 4
- 238000005137 deposition process Methods 0.000 description 3
- 239000000463 material Substances 0.000 description 2
- 230000002411 adverse Effects 0.000 description 1
- 230000000903 blocking effect Effects 0.000 description 1
- 238000012790 confirmation Methods 0.000 description 1
- 238000009826 distribution Methods 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 238000002474 experimental method Methods 0.000 description 1
- 239000011159 matrix material Substances 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 125000004430 oxygen atom Chemical group O* 0.000 description 1
- 230000000149 penetrating effect Effects 0.000 description 1
- 230000035515 penetration Effects 0.000 description 1
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- G—PHYSICS
- G02—OPTICS
- G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
- G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
- G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour
- G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour based on liquid crystals, e.g. single liquid crystal display cells
- G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
- G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
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- G—PHYSICS
- G02—OPTICS
- G02B—OPTICAL ELEMENTS, SYSTEMS OR APPARATUS
- G02B1/00—Optical elements characterised by the material of which they are made; Optical coatings for optical elements
- G02B1/10—Optical coatings produced by application to, or surface treatment of, optical elements
- G02B1/14—Protective coatings, e.g. hard coatings
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- G—PHYSICS
- G02—OPTICS
- G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
- G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
- G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour
- G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour based on liquid crystals, e.g. single liquid crystal display cells
- G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
- G02F1/1333—Constructional arrangements; Manufacturing methods
- G02F1/1343—Electrodes
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/302—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
- H01L21/306—Chemical or electrical treatment, e.g. electrolytic etching
- H01L21/3065—Plasma etching; Reactive-ion etching
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- G—PHYSICS
- G02—OPTICS
- G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
- G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
- G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour
- G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour based on liquid crystals, e.g. single liquid crystal display cells
- G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
- G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
- G02F1/1362—Active matrix addressed cells
- G02F1/13625—Patterning using multi-mask exposure
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- Thin Film Transistor (AREA)
Abstract
Description
본 발명은 박막 트랜지스터(thin film transistor; TFT)의 제조 방법에 관한 것으로서, 보다 구체적으로는 액티브 매트릭스 액정 디스플레이(active matrix liquid crystal display; AMLCD)의 화소 스위칭 소자로서 사용되는 박막 트랜지스터의 제조 방법에 관한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of manufacturing a thin film transistor (TFT), and more particularly to a method of manufacturing a thin film transistor used as a pixel switching element of an active matrix liquid crystal display (AMLCD). will be.
활성층으로 비정질 실리콘(amorphous silicon)을 이용하는 박막 트랜지스터의 일반적인 구조가 도 1에 도시되어 있다. 도 1을 참조하면, 유리 기판(10) 위에 게이트 전극(11)이 형성되며, 그 위에 게이트 절연막(12)과 비정질 실리콘으로 이루어진 활성층(13)이 존재한다. 그리고 활성층(13) 위에 데이터 전극(14)이 형성되며 보호층(15)으로 덮이게 된다. 보호층(15)의 일부에 비아 홀(16)이 형성되고, 보호층(15) 상부에 화소 전극(17)이 형성되어 비아 홀(16)을 통하여 데이터 전극(14)과 연결된다.A general structure of a thin film transistor using amorphous silicon as the active layer is shown in FIG. 1. Referring to FIG. 1, a gate electrode 11 is formed on a glass substrate 10, and an active layer 13 made of amorphous silicon is formed thereon. The data electrode 14 is formed on the active layer 13 and covered with the protective layer 15. The via hole 16 is formed in a portion of the protective layer 15, and the pixel electrode 17 is formed on the protective layer 15 and connected to the data electrode 14 through the via hole 16.
박막 트랜지스터가 온(on) 상태일 경우, 활성층(13) 내부에는 채널 영역이 형성된다. 이 영역은 게이트 전극(11)에 걸린 전압에 의해 채널부가 반전되어 형성된다. 이 채널 영역을 통해 데이터 전극(14)으로부터 전하가 이동하여 반대편 전극을 거쳐 화소 전극까지 가게 된다. 데이터 전극(14)과 활성층(13) 사이에는 오믹 접촉을 만들어 주기 위해 n+ 비정질 실리콘이 형성되어 전류의 흐름을 보다 원활하게 해 준다.When the thin film transistor is in an on state, a channel region is formed in the active layer 13. This region is formed by inverting the channel portion by the voltage applied to the gate electrode 11. The charge moves from the data electrode 14 through this channel region to the pixel electrode via the opposite electrode. An n + amorphous silicon is formed between the data electrode 14 and the active layer 13 to make an ohmic contact, so that the current flows more smoothly.
이러한 구조의 박막 트랜지스터는 다음과 같은 과정을 거쳐 제조된다. 먼저, 유리 기판(10) 위에 게이트 전극(11)을 증착하고 패터닝한 후, 게이트 절연막(12)과 활성층(13)을 연속적으로 증착한다. 이어서, 활성층(13)을 패터닝하며, 데이터 전극(14) 물질을 증착하고, 소스/드레인을 패터닝한다. 또한, 백 채널 식각(back channel etch; BCE), 보호층(15) 증착, 비아 홀(16) 식각, 화소 전극(17)의 증착 및 패터닝이 순차적으로 진행된다.The thin film transistor having this structure is manufactured through the following process. First, after the gate electrode 11 is deposited and patterned on the glass substrate 10, the gate insulating layer 12 and the active layer 13 are successively deposited. The active layer 13 is then patterned, the data electrode 14 material is deposited, and the source / drain is patterned. In addition, a back channel etch (BCE), a protective layer 15 is deposited, a via hole 16 is etched, and a pixel electrode 17 is deposited and patterned sequentially.
이러한 과정에 따라 박막 트랜지스터 제조 공정을 완료하였을 때, 오프(off) 전류의 크기는 일반적으로 10pA 정도이다. 이와 같이 오프 전류의 크기가 상승하는 이유는 보호층(15)의 증착 온도와 관련이 깊다.According to this process, when the thin film transistor manufacturing process is completed, the magnitude of the off current is generally about 10 pA. The reason why the magnitude of the off current rises is deeply related to the deposition temperature of the protective layer 15.
대개 보호층(15)의 증착 온도는 게이트 절연막(12)을 증착할 때의 온도에 비하여 상당히 낮은 편이다. 높은 온도에서 보호층(15)을 증착하게 되면 소자 특성에 악영향을 주기 때문에 보호층(15)은 게이트 절연막(12)에 비하여 상대적으로 낮은 온도에서 증착을 진행하여야 한다. 따라서, 보호층(15)의 막 밀도(film density)가 낮아지게 되며, 이로 인하여 이후 화소 전극(17)의 증착 공정에서 발생하는 산소나 다른 원소들이 백 채널에 영향을 주는 것을 효과적으로 차단하지 못하여 오프 전류가 상승하게 된다. 화소 전극(17)의 증착시 산소 원자가 보호층(15)을 관통하여 백 채널에 이르게 되면, 백 채널 표면에 있는 수소 원자와 결합하여 댕글링 본드(dangling bond)수를 증가시키고, 이로 인하여 오프 전류가 상승하게 된다.Usually, the deposition temperature of the protective layer 15 is considerably lower than the temperature at which the gate insulating layer 12 is deposited. Since the deposition of the protective layer 15 at a high temperature adversely affects device characteristics, the protective layer 15 should be deposited at a relatively lower temperature than the gate insulating layer 12. Accordingly, the film density of the protective layer 15 is lowered, and thus, the film density of the protective layer 15 may not be effectively blocked because oxygen or other elements generated during the deposition process of the pixel electrode 17 may not effectively affect the back channel. The current rises. When the oxygen atoms penetrate the protective layer 15 and reach the back channel during deposition of the pixel electrode 17, the number of dangling bonds increases by combining with hydrogen atoms on the surface of the back channel, thereby off current. Will rise.
본 발명은 상술한 종래기술에서의 현안 문제점을 해결하기 위하여 안출된 것으로서, 본 발명의 목적은 박막 트랜지스터의 오프 전류를 감소시켜 고성능 액정 디스플레이를 구현하기 위한 것이다.The present invention has been made to solve the above-mentioned problems in the prior art, an object of the present invention is to implement a high-performance liquid crystal display by reducing the off current of the thin film transistor.
도 1은 종래기술에 따른 박막 트랜지스터를 나타내는 단면도이다.1 is a cross-sectional view showing a thin film transistor according to the prior art.
도 2는 본 발명에 따른 방법에 의하여 제조된 박막 트랜지스터를 나타내는 단면도이다.2 is a cross-sectional view showing a thin film transistor manufactured by the method according to the present invention.
<도면의 주요 부분에 대한 부호의 설명><Explanation of symbols for the main parts of the drawings>
10: 유리 기판11: 게이트 전극10 glass substrate 11: gate electrode
12: 게이트 절연막13: 활성층12 gate insulating film 13: active layer
14: 데이터 전극15: 보호층14: data electrode 15: protective layer
16: 비아 홀17: 화소 전극16: Via Hole 17 Pixel Electrode
20: 표면 경화층20: surface hardened layer
이러한 목적을 달성하기 위하여, 본 발명은 보호층에 비아 홀을 형성한 후 플라즈마 처리를 통하여 보호층의 표면에 막 밀도가 높은 표면 경화층을 형성함으로써 후속 공정에서 산소나 다른 원소들의 침투를 방지하여 오프 전류를 감소시킬 수 있는 박막 트랜지스터의 제조 방법을 제공한다.In order to achieve the above object, the present invention forms a via hole in the protective layer and then forms a surface hardened layer having a high film density on the surface of the protective layer through plasma treatment to prevent penetration of oxygen or other elements in a subsequent process. A method of manufacturing a thin film transistor capable of reducing off current is provided.
본 발명에 따른 박막 트랜지스터의 제조 방법은, 유리 기판 위에 게이트 전극을 증착하고 패터닝하는 단계와, 게이트 절연막과 활성층을 연속적으로 증착하는 단계와, 활성층을 패터닝하는 단계와, 데이터 전극 물질을 증착한 후 소스/드레인을 패터닝하고 백 채널 식각을 진행하는 단계와, 보호층을 증착하고 비아 홀을 식각하는 단계와, 화소 전극을 증착하고 패터닝하는 단계로 이루어지며, 특히 보호층을 증착하고 비아 홀을 식각하는 단계 이후에 플라즈마 처리 공정을 진행하여 보호층 표면에 표면 경화층을 형성하는 단계를 포함하는 것을 특징으로 한다.A method of manufacturing a thin film transistor according to the present invention includes depositing and patterning a gate electrode on a glass substrate, successively depositing a gate insulating film and an active layer, patterning the active layer, and depositing a data electrode material. Patterning the source / drain and back channel etching, depositing a protective layer and etching via holes, depositing and patterning pixel electrodes, in particular depositing a protective layer and etching via holes After the step of performing a plasma treatment process comprising the step of forming a surface hardened layer on the surface of the protective layer.
이하, 첨부 도면을 참조하여 본 발명의 바람직한 실시예를 보다 상세하게 설명하도록 한다. 첨부 도면에서 각 층 또는 막은 도면의 명확한 이해를 돕기 위해 다소 과장되거나 개략적으로 도시되었음을 밝혀둔다.Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings. In the accompanying drawings, it is to be noted that each layer or film is shown somewhat exaggerated or schematically in order to facilitate a clear understanding of the drawings.
도 2는 본 발명에 따른 방법에 의하여 제조된 박막 트랜지스터를 나타내는 단면도이다. 도 2를 참조하면, 유리 기판(10) 위에 순차적으로 형성된 게이트 전극(11), 게이트 절연막(12), 비정질 실리콘 활성층(13), 데이터 전극(14), 보호층(15), 비아 홀(16), 화소 전극(17)으로 이루어지는 박막 트랜지스터의 구성은 기존의 구성과 동일하다.2 is a cross-sectional view showing a thin film transistor manufactured by the method according to the present invention. 2, the gate electrode 11, the gate insulating layer 12, the amorphous silicon active layer 13, the data electrode 14, the protective layer 15, and the via hole 16 sequentially formed on the glass substrate 10. ), The structure of the thin film transistor composed of the pixel electrode 17 is the same as the conventional structure.
본 발명의 박막 트랜지스터는 보호층(15)의 표면에 표면 경화층(20, surface hardening layer)이 형성된다는 점에 특징이 있다. 표면 경화층(20)은 막 밀도(film density)가 높기 때문에 화소 전극(17)의 증착 공정에서 산소나 다른 원소들이 보호층(15)을 관통하지 못하도록 하여 백 채널에 영향을 주는 것을 효과적으로 차단할 수 있다.The thin film transistor of the present invention is characterized in that a surface hardening layer 20 is formed on the surface of the protective layer 15. Since the surface hardened layer 20 has a high film density, oxygen or other elements do not penetrate the protective layer 15 in the deposition process of the pixel electrode 17, thereby effectively blocking the influence on the back channel. have.
표면 경화층(20)은 보호층(15)에 비아 홀(16)을 형성한 후 화소 전극(17)을 증착하기 전에 플라즈마 처리를 통하여 형성한다. 본 발명에 따른 박막 트랜지스터의 제조 방법을 설명하면, 먼저 유리 기판(10) 위에 게이트 전극(11)을 증착하고 패터닝한 후, 게이트 절연막(12)과 활성층(13)을 연속적으로 증착하고, 활성층(13)을 패터닝한다. 이어서, 데이터 전극(14) 물질을 증착하고, 소스/드레인을 패터닝한 다음, 백 채널 식각(back channel etch; BCE)을 진행한다. 계속해서, 결과물 전면에 보호층(15)을 증착하고, 보호층(15) 일부를 식각하여 비아 홀(16)을 형성한 후, 플라즈마 처리에 의하여 보호층(15) 표면에 표면 경화층(20)을 형성한다. 이어서, 화소 전극(17)을 증착하고 패터닝한다.The surface hardened layer 20 is formed through the plasma treatment after the via hole 16 is formed in the protective layer 15 and before the pixel electrode 17 is deposited. Referring to the method of manufacturing the thin film transistor according to the present invention, first, the gate electrode 11 is deposited and patterned on the glass substrate 10, and then the gate insulating layer 12 and the active layer 13 are successively deposited, and the active layer ( Pattern 13). The data electrode 14 material is then deposited, the source / drain is patterned, followed by a back channel etch (BCE). Subsequently, the protective layer 15 is deposited on the entire surface of the resultant, and a portion of the protective layer 15 is etched to form the via holes 16, and then the surface hardened layer 20 is formed on the surface of the protective layer 15 by plasma treatment. ). Subsequently, the pixel electrode 17 is deposited and patterned.
플라즈마 처리 공정에서 사용되는 플라즈마 가스는 예컨대 질소(N2), 수소(H2), 포스핀(PH3) 등이 가능하다. 플라즈마 처리 공정에 있어서, 전력은 50~3000W, 압력은 10~5000mTorr, 배치간격은 100~3000mils, 가스유량은 10~15000sccm, 시간은 10~6000초, 온도는 150~4000℃가 바람직하다.The plasma gas used in the plasma treatment process may be, for example, nitrogen (N 2 ), hydrogen (H 2 ), phosphine (PH 3 ), or the like. In the plasma treatment process, the power is 50 to 3000 W, the pressure is 10 to 5000 mTorr, the batch interval is 100 to 3000 mils, the gas flow rate is 10 to 15000 sccm, the time is 10 to 6000 seconds, the temperature is preferably 150 to 4000 ° C.
플라즈마 처리 방법 외에도 보호층(15)의 두께를 증가시켜 이후 공정에서 백 채널 쪽에 영향을 주는 것을 차단하는 방법도 고려할 수 있으나, 이러한 경우에는 보호층(15)의 두께를 최소한 1㎛ 이상 증착하여야 하므로 실제 공정 적용에는 불가능한 실정이다.In addition to the plasma treatment method, a method of increasing the thickness of the protective layer 15 to block the influence on the back channel side in a subsequent process may be considered, but in this case, the thickness of the protective layer 15 should be deposited at least 1 μm or more. This is not possible in practical application.
이상 설명한 바와 같이, 본 발명에 따른 박막 트랜지스터 제조 방법은 보호층에 비아 홀을 형성한 후 플라즈마 처리를 통하여 보호층의 표면에 막 밀도가 높은 표면 경화층을 형성함으로써 화소 전극의 증착 공정에서 산소나 다른 원소들이 보호층을 관통하지 못하도록 하여 백 채널에 영향을 주는 것을 효과적으로 차단할 수 있다. 따라서, 박막 트랜지스터의 오프 전류를 효과적으로 감소시킬 수 있으며, 고성능 액정 디스플레이를 구현할 수 있다.As described above, the thin film transistor manufacturing method according to the present invention forms a via hole in the protective layer, and then forms a surface hardened layer having a high film density on the surface of the protective layer through plasma treatment, thereby forming oxygen or oxygen in the deposition process of the pixel electrode. By preventing other elements from penetrating the protective layer, it can effectively block the effect on the back channel. Therefore, the off current of the thin film transistor can be effectively reduced, and a high performance liquid crystal display can be realized.
실험에 의하여 직접 확인한 결과, 종래의 제조 방법에 있어서 8.89~8.99pA의 분포를 보이던 박막 트랜지스터의 오프 전류가 본 발명의 제조 방법을 적용하면 3.96~4.04pA로 감소하였다.As a result of direct confirmation by experiment, the off current of the thin film transistor which showed 8.89-8.99 pA distribution in the conventional manufacturing method was reduced to 3.96-44.0 pA by applying the manufacturing method of this invention.
본 명세서와 도면에는 본 발명의 바람직한 실시예에 대하여 개시하였으며, 비록 특정 용어들이 사용되었으나, 이는 단지 본 발명의 기술 내용을 쉽게 설명하고 발명의 이해를 돕기 위한 일반적인 의미에서 사용된 것이지, 본 발명의 범위를 한정하고자 하는 것은 아니다. 여기에 개시된 실시예 외에도 본 발명의 기술적 사상에 바탕을 둔 다른 변형예들이 실시 가능하다는 것은 본 발명이 속하는 기술분야에서 통상의 지식을 가진 자에게 자명한 것이다.In the present specification and drawings, preferred embodiments of the present invention have been disclosed, and although specific terms have been used, these are merely used in a general sense to easily explain the technical contents of the present invention and to help the understanding of the present invention. It is not intended to limit the scope. It is apparent to those skilled in the art that other modifications based on the technical idea of the present invention can be carried out in addition to the embodiments disclosed herein.
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH04257826A (en) * | 1991-02-13 | 1992-09-14 | Sharp Corp | Manufacture of active matrix substrate |
| KR19990043145A (en) * | 1997-11-28 | 1999-06-15 | 구자홍 | Substrate of liquid crystal display device and manufacturing method thereof |
| KR19990076545A (en) * | 1998-03-31 | 1999-10-15 | 다니구찌 이찌로오, 기타오카 다카시 | Manufacturing method of thin film transistor and liquid crystal display device using same |
| JPH11337973A (en) * | 1998-05-28 | 1999-12-10 | Sharp Corp | Production of active matrix substrate |
| KR20000018367A (en) * | 1998-09-01 | 2000-04-06 | 구본준, 론 위라하디락사 | Fabricating method of liquid crystal display |
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Patent Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH04257826A (en) * | 1991-02-13 | 1992-09-14 | Sharp Corp | Manufacture of active matrix substrate |
| KR19990043145A (en) * | 1997-11-28 | 1999-06-15 | 구자홍 | Substrate of liquid crystal display device and manufacturing method thereof |
| KR19990076545A (en) * | 1998-03-31 | 1999-10-15 | 다니구찌 이찌로오, 기타오카 다카시 | Manufacturing method of thin film transistor and liquid crystal display device using same |
| JPH11337973A (en) * | 1998-05-28 | 1999-12-10 | Sharp Corp | Production of active matrix substrate |
| KR20000018367A (en) * | 1998-09-01 | 2000-04-06 | 구본준, 론 위라하디락사 | Fabricating method of liquid crystal display |
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