KR20030058308A - Method of forming isolation of semiconductor device - Google Patents
Method of forming isolation of semiconductor device Download PDFInfo
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- KR20030058308A KR20030058308A KR1020010088724A KR20010088724A KR20030058308A KR 20030058308 A KR20030058308 A KR 20030058308A KR 1020010088724 A KR1020010088724 A KR 1020010088724A KR 20010088724 A KR20010088724 A KR 20010088724A KR 20030058308 A KR20030058308 A KR 20030058308A
- Authority
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- South Korea
- Prior art keywords
- trench
- rpm
- semiconductor device
- oxide film
- silicon substrate
- Prior art date
Links
- 238000000034 method Methods 0.000 title claims abstract description 28
- 238000002955 isolation Methods 0.000 title claims abstract description 7
- 239000004065 semiconductor Substances 0.000 title claims abstract description 5
- 239000000758 substrate Substances 0.000 claims abstract description 16
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims abstract description 10
- 229910052710 silicon Inorganic materials 0.000 claims abstract description 10
- 239000010703 silicon Substances 0.000 claims abstract description 10
- 238000001039 wet etching Methods 0.000 claims abstract description 9
- 238000005530 etching Methods 0.000 claims abstract description 5
- 238000000151 deposition Methods 0.000 claims description 2
- 239000011810 insulating material Substances 0.000 claims description 2
- 150000004767 nitrides Chemical class 0.000 abstract description 12
- 238000004519 manufacturing process Methods 0.000 abstract description 4
- 238000005498 polishing Methods 0.000 abstract description 2
- 229920002120 photoresistant polymer Polymers 0.000 description 7
- 230000007547 defect Effects 0.000 description 3
- 238000005137 deposition process Methods 0.000 description 3
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 238000000059 patterning Methods 0.000 description 1
- 229910052814 silicon oxide Inorganic materials 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/76—Making of isolation regions between components
- H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
- H01L21/76224—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using trench refilling with dielectric materials
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3105—After-treatment
- H01L21/311—Etching the insulating layers by chemical or physical means
- H01L21/31105—Etching inorganic layers
- H01L21/31111—Etching inorganic layers by chemical means
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- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Physics & Mathematics (AREA)
- Power Engineering (AREA)
- Chemical & Material Sciences (AREA)
- Chemical Kinetics & Catalysis (AREA)
- General Chemical & Material Sciences (AREA)
- Inorganic Chemistry (AREA)
- Element Separation (AREA)
Abstract
Description
본 발명은 반도체소자의 STI(shallow trench isolation) 형성방법에 관한 것으로, 특히 단순화된 공정으로 STI를 형성함으로써 비용을 절감하고 생산성을 증대시키며 결함발생을 최소화할 수 있도록 하는 방법에 관한 것이다.The present invention relates to a method for forming shallow trench isolation (STI) of a semiconductor device, and more particularly, to a method for reducing cost, increasing productivity and minimizing defects by forming STI in a simplified process.
현재 반도체소자 제조공정중 STI공정에는 패드산화막고 질화막의 적층구조를사용하고 있다. 즉, 도1a에 나타낸 바와 같이 실리콘기판(1)상에 패드산화막(2)과 패드질화막(3)을 차례로 증착한 후, 그 위에 포토레지스트(4)를 도포하고 사진공정을 통해 소정의 소자분리영역패턴으로 패터닝한 다음, 이 포토레지스트(4) 패턴을 마스크로 이용하여 패드질화막(3)과 패드산화막(2)을 식각하고, 이에 따라 노출되는 기판부위를 소정깊이로 식각하여 트렌치(5)를 형성한다.Currently, a stacked structure of a pad oxide film and a nitride film is used in the STI process of the semiconductor device manufacturing process. That is, as shown in FIG. 1A, the pad oxide film 2 and the pad nitride film 3 are sequentially deposited on the silicon substrate 1, and then a photoresist 4 is applied thereon, and a predetermined device is separated by a photo process. After patterning the region pattern, the pad nitride film 3 and the pad oxide film 2 are etched using the photoresist 4 pattern as a mask, and the exposed substrate portion is etched to a predetermined depth to form the trench 5. To form.
이어서 도1b에 나타낸 바와 같이 포토레지스트(4) 패턴을 제거한 후, 산화막(6)을 증착하여 트렌치를 매립한 다음, CMP공정을 진행하고 패드질화막(3)과 패드산화막(2)을 제거함으로써 도1c에 도시된 바와 같은 산화막(6a)으로 된 STI구조를 얻는다.Subsequently, after removing the photoresist 4 pattern as shown in FIG. 1B, the oxide film 6 is deposited to fill the trench, and then the CMP process is performed to remove the pad nitride film 3 and the pad oxide film 2. An STI structure of the oxide film 6a as shown in 1c is obtained.
상기한 종래기술은 패드산화막과 패드질화막의 증착공정과 CMP 및 질화막 제거공정을 진행할 때 발생하는 결함과 양산시의 비용 및 생산성 측면에서 상당히 불리하다.The prior art is disadvantageous in terms of defects and cost and productivity in mass production during the deposition process of the pad oxide film and the pad nitride film and the removal of the CMP and nitride films.
본 발명은 상기 문제점을 해결하기 위한 것으로써, 패드산화막 및 패드질화막을 사용하지 않고 STI구조의 소자분리막의 형성 방법을 제공하는데 목적이 있다.SUMMARY OF THE INVENTION The present invention has been made to solve the above problems, and an object of the present invention is to provide a method for forming a device isolation film having an STI structure without using a pad oxide film and a pad nitride film.
도1a 내지 도1c는 종래기술에 의한 STI공정을 나타낸 공정순서도.Figures 1a to 1c is a process flow chart showing the STI process according to the prior art.
도2a 내지 도2c는 본 발명에 의한 STI공정을 나타낸 공정순서도.Figure 2a to 2c is a process flow chart showing the STI process according to the present invention.
* 도면의 주요부분에 대한 부호의 설명* Explanation of symbols for main parts of the drawings
11 : 실리콘기판 12 : 포토레지스트11 silicon substrate 12 photoresist
13 : 트렌치 14, 14a : 산화막13: trench 14, 14a: oxide film
상기 목적을 달성하기 위한 본 발명은, 실리콘기판을 선택적으로 식각하여 트렌치를 형성하는 단계와, 상기 트렌치를 포함한 기판 전면에 절연막을 증착하는단계 및 HF계열의 습식식각액을 스핀 RPM방식으로 사용하여 상기 절연막을 식각하는 단계를 포함하여 구성된 것을 특징으로 한다.The present invention for achieving the above object, by selectively etching the silicon substrate to form a trench, the step of depositing an insulating film on the front surface of the substrate including the trench and using a wet etching solution of HF series in the spin RPM method And etching the insulating film.
이하, 본 발명이 속하는 기술분야에서 통상의 지식을 가진 자가 본 발명의 기술적 사상을 용이하게 실시할 수 있을 정도로 상세히 설명하기 위하여, 본 발명의 가장 바람직한 실시예를 첨부된 도면을 참조하여 설명하기로 한다.DETAILED DESCRIPTION Hereinafter, exemplary embodiments of the present invention will be described with reference to the accompanying drawings so that those skilled in the art may easily implement the technical idea of the present invention. do.
본 발명은 STI공정시 종래와 같이 패드산화막과 패드질화막을 사용하지 않고, 실리콘기판을 직접 식각한 후, 절연막을 매립한 후 HF계열의 습식식각액을 스핀 RPM방식으로 사용하여 기판표면의 절연막을 제거하는 것이다.In the STI process, the silicon oxide substrate is directly etched without using the pad oxide film and the pad nitride film as in the prior art, and the insulating film is buried, and then the HF-based wet etchant is used as the spin RPM method to remove the insulating film on the substrate surface. It is.
도2a 내지 도 2c에 본 발명에 의한 STI 형성방법을 공정순서에 따라 도시하였다.2A to 2C show the STI forming method according to the present invention according to the process sequence.
먼저, 도2a에 나타낸 바와 같이 실리콘기판(11)상에 포토레지스트(12)를 도포하고 소정의 소자분리영역 패턴으로 패터닝한 후, 이 포토레지스트(12) 패턴을 마스크로 이용하여 노출된 실리콘기판(11) 부위를 식각하여 트렌치(13)를 형성한다.First, as shown in FIG. 2A, the photoresist 12 is applied onto the silicon substrate 11 and patterned into a predetermined device isolation region pattern. The exposed silicon substrate is then exposed using the photoresist 12 pattern as a mask. (11) The portion is etched to form the trench 13.
이어서 도2b에 나타낸 바와 같이 상기 포토레지스트(12) 패턴을 제거한 후, 트렌치(13)를 포함한 기판 전면에 절연물질로서, 예컨대 산화막(14)을 증착한다.Subsequently, as shown in FIG. 2B, the photoresist 12 pattern is removed, and then, for example, an oxide film 14 is deposited on the entire surface of the substrate including the trench 13 as an insulating material.
다음에 도2c에 나타낸 바와 같이 HF계열의 습식식각액을 스핀 RPM방식으로 사용하여 상기 산화막(14)을 식각한다. 이때, 스핀 RPM방식으로 습식식각액을 사용하는 이유는 실리콘기판(11) 표면에 증착된 산화막(14)만을 선택적으로 제거하고트렌치(13) 안에 매립된 산화막(14a)은 남겨 두기 위해서이다. 스핀 RPM으로 습식식각액을 사용하는 경우 RPM은 50~200으로 하는 것이 바람직하다.Next, as shown in FIG. 2C, the oxide film 14 is etched by using a wet etching solution of HF series in a spin RPM method. At this time, the reason why the wet etching solution is used as the spin RPM method is to selectively remove only the oxide film 14 deposited on the surface of the silicon substrate 11 and leave the oxide film 14a embedded in the trench 13. When using the wet etching solution as the spin RPM RPM is preferably set to 50 ~ 200.
이와 같이 본 발명은 습식식각액을 스핀 RPM방식으로 적용하여 트렌치내의 산화막의 손실없이 실리콘기판 표면의 산화막을 선택적으로 제거함으로써 STI구조를 형성할 수 있다.As described above, the present invention can form the STI structure by selectively applying the wet etching solution to the spin RPM method and selectively removing the oxide film on the surface of the silicon substrate without losing the oxide film in the trench.
본 발명의 기술 사상은 상기 바람직한 실시예에 따라 구체적으로 기술되었으나, 상기한 실시예는 그 설명을 위한 것이며 그 제한을 위한 것이 아님을 주의하여야 한다. 또한, 본 발명의 기술 분야의 통상의 전문가라면 본 발명의 기술 사상의 범위내에서 다양한 실시예가 가능함을 이해할 수 있을 것이다.Although the technical idea of the present invention has been described in detail according to the above preferred embodiment, it should be noted that the above-described embodiment is for the purpose of description and not of limitation. In addition, those skilled in the art will understand that various embodiments are possible within the scope of the technical idea of the present invention.
본 발명은 STI공정시 CMP의 연마정지층으로 사용되고 있는 질화막 증착공정을 생략함으로써 양산시 비용을 절감할 수 있고 생산성 측면에서도 상당한 효과를 얻을 수 있다. 또한, 질화막 증착공정과 질화막 제거공정을 진행할 경우 발생할 수 있는 결함을 최소화할 수 있으므로 소자개발 측면에서도 유리하다.In the present invention, the cost of mass production can be reduced and a significant effect can be obtained in terms of productivity by omitting the nitride film deposition process used as the polishing stop layer of the CMP during the STI process. In addition, since defects that may occur when the nitride film deposition process and the nitride film removal process are performed are minimized, the device development is also advantageous.
Claims (3)
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| KR1020010088724A KR100798802B1 (en) | 2001-12-31 | 2001-12-31 | Method of forming isolation of semiconductor device |
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|---|---|---|---|
| KR1020010088724A KR100798802B1 (en) | 2001-12-31 | 2001-12-31 | Method of forming isolation of semiconductor device |
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| KR20030058308A true KR20030058308A (en) | 2003-07-07 |
| KR100798802B1 KR100798802B1 (en) | 2008-01-29 |
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Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR200453416Y1 (en) * | 2009-06-09 | 2011-05-03 | 이진섭 | Massage vibration sporting goods capable of controlling the height and rotation thereof |
| CN117317067A (en) * | 2023-11-28 | 2023-12-29 | 晶科能源(海宁)有限公司 | Solar cell manufacturing method and solar cell |
Family Cites Families (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR100359858B1 (en) * | 1998-12-30 | 2003-01-15 | 주식회사 하이닉스반도체 | Method of forming device isolation film in semiconductor device |
| KR100327571B1 (en) * | 1998-12-30 | 2002-04-17 | 박종섭 | Method of forming device isolation film in semiconductor device |
| KR20010063307A (en) * | 1999-12-22 | 2001-07-09 | 박종섭 | Method for forming isolation layer of semiconductor device |
| KR20010061122A (en) * | 1999-12-28 | 2001-07-07 | 박종섭 | A method for forming a field oxide of semiconductor device |
| KR20010061041A (en) * | 1999-12-28 | 2001-07-07 | 박종섭 | Forming method for a field oxide of semiconductor device |
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2001
- 2001-12-31 KR KR1020010088724A patent/KR100798802B1/en not_active IP Right Cessation
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR200453416Y1 (en) * | 2009-06-09 | 2011-05-03 | 이진섭 | Massage vibration sporting goods capable of controlling the height and rotation thereof |
| CN117317067A (en) * | 2023-11-28 | 2023-12-29 | 晶科能源(海宁)有限公司 | Solar cell manufacturing method and solar cell |
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| KR100798802B1 (en) | 2008-01-29 |
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