KR20000060583A - Fabricating method of semiconductor device - Google Patents
Fabricating method of semiconductor device Download PDFInfo
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- KR20000060583A KR20000060583A KR1019990009001A KR19990009001A KR20000060583A KR 20000060583 A KR20000060583 A KR 20000060583A KR 1019990009001 A KR1019990009001 A KR 1019990009001A KR 19990009001 A KR19990009001 A KR 19990009001A KR 20000060583 A KR20000060583 A KR 20000060583A
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- semiconductor substrate
- semiconductor device
- locos
- nitride film
- film
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- 239000004065 semiconductor Substances 0.000 title claims abstract description 40
- 238000000034 method Methods 0.000 title claims abstract description 15
- 150000004767 nitrides Chemical class 0.000 claims abstract description 33
- 239000000758 substrate Substances 0.000 claims abstract description 23
- 238000005530 etching Methods 0.000 claims abstract description 14
- 238000004519 manufacturing process Methods 0.000 claims abstract description 12
- 229920002120 photoresistant polymer Polymers 0.000 claims abstract description 12
- 239000000126 substance Substances 0.000 claims abstract description 10
- 238000004140 cleaning Methods 0.000 claims abstract description 6
- KRHYYFGTRYWZRS-UHFFFAOYSA-N Fluorane Chemical compound F KRHYYFGTRYWZRS-UHFFFAOYSA-N 0.000 claims description 3
- 229920000642 polymer Polymers 0.000 abstract description 11
- 230000002950 deficient Effects 0.000 abstract description 2
- 230000003647 oxidation Effects 0.000 abstract 4
- 238000007254 oxidation reaction Methods 0.000 abstract 4
- 229910052710 silicon Inorganic materials 0.000 abstract 1
- 239000010703 silicon Substances 0.000 abstract 1
- 230000007547 defect Effects 0.000 description 3
- 230000007257 malfunction Effects 0.000 description 3
- 238000007796 conventional method Methods 0.000 description 2
- 238000000206 photolithography Methods 0.000 description 2
- 230000000903 blocking effect Effects 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 238000002955 isolation Methods 0.000 description 1
Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/302—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
- H01L21/306—Chemical or electrical treatment, e.g. electrolytic etching
- H01L21/308—Chemical or electrical treatment, e.g. electrolytic etching using masks
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02041—Cleaning
- H01L21/02057—Cleaning during device manufacture
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3105—After-treatment
- H01L21/311—Etching the insulating layers by chemical or physical means
- H01L21/31105—Etching inorganic layers
- H01L21/31111—Etching inorganic layers by chemical means
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- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Physics & Mathematics (AREA)
- Power Engineering (AREA)
- Chemical & Material Sciences (AREA)
- Chemical Kinetics & Catalysis (AREA)
- General Chemical & Material Sciences (AREA)
- Inorganic Chemistry (AREA)
- Local Oxidation Of Silicon (AREA)
Abstract
Description
본 발명은 반도체소자의 제조방법에 관한 것으로, 특히 소자격리 공정인 피지아이(profiled grooved isolation : PGI) 공정에서 발생하는 이물질을 효과적으로 제거하기에 적당하도록 한 반도체소자의 제조방법에 관한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a semiconductor device, and more particularly, to a method for manufacturing a semiconductor device suitable for effectively removing foreign substances generated in a profiled grooved isolation (PGI) process.
종래 반도체소자의 제조방법을 도1a 내지 도1e에 도시한 수순단면도를 참조하여 상세시 설명하면 다음과 같다.A method of manufacturing a conventional semiconductor device will now be described in detail with reference to the procedure cross-sectional view shown in FIGS. 1A to 1E.
먼저, 도1a에 도시한 바와같이 반도체기판(1)의 상부에 순차적으로 버퍼산화막(2)과 질화막(3)을 형성한다.First, as shown in FIG. 1A, a buffer oxide film 2 and a nitride film 3 are sequentially formed on the semiconductor substrate 1.
그리고, 도1b에 도시한 바와같이 상기 질화막(3)의 상부에 감광막(PR1)을 도포한 후, 로코스(LOCOS) 사진식각공정을 통해 패터닝하여 감광막(PR1) 패턴을 형성한다.As shown in FIG. 1B, the photoresist film PR1 is coated on the nitride film 3 and then patterned through a LOCOS photolithography process to form a photoresist film PR1 pattern.
그리고, 도1c에 도시한 바와같이 상기 감광막(PR1) 패턴을 적용하여 질화막(3)을 식각한다. 이때, 질화막(3)의 과도식각으로 인해 버퍼산화막(2)뿐만 아니라 반도체기판(1)의 일부도 식각되며, 그 식각된 표면에는 미설명부호 '4'로 도시한 바와같이 식각시에 발생한 폴리머 또는 반도체기판(1)의 불량 시드(seed)가 형성된다.As illustrated in FIG. 1C, the nitride film 3 is etched by applying the photosensitive film PR1 pattern. At this time, due to the excessive etching of the nitride film 3, not only the buffer oxide film 2 but also a part of the semiconductor substrate 1 is etched, and the polymer generated during the etching as shown by the reference numeral '4' on the etched surface. Alternatively, a poor seed of the semiconductor substrate 1 is formed.
그리고, 도1d에 도시한 바와같이 상기 감광막(PR1) 패턴을 제거하고, 질화막(3) 식각시에 생성된 폴리머와 이물질을 제거하기 위한 세정을 실시한다.As shown in FIG. 1D, the photoresist film PR1 pattern is removed, and a cleaning is performed to remove the polymer and foreign substances generated during the etching of the nitride film 3.
그리고, 도1e에 도시한 바와같이 상기 잔류하는 질화막(3)을 하드마스크로 적용하여 반도체기판(1)을 식각한다. 이때, 반도체기판(1)의 식각깊이와 식각된 홈의 각도를 관리하는 것이 피지아이(PGI)공정의 핵심적인 기술사항이다.As shown in FIG. 1E, the remaining nitride film 3 is applied as a hard mask to etch the semiconductor substrate 1. At this time, managing the etch depth and the angle of the etched groove of the semiconductor substrate 1 is a key technical matter of the PGI process.
한편, 미설명부호 '5'은 반도체기판(1)의 식각 후, 발생한 불량을 나타낸다.On the other hand, reference numeral '5' represents a defect generated after etching the semiconductor substrate 1.
상술한 바와같이 종래 반도체소자의 제조방법은 감광막 패턴을 이용하여 질화막을 식각할 때, 생성된 폴리머 및 이물질이 후속 반도체기판의 식각저지층으로 작용하여 피지아이공정의 불량을 유발하는데, 이를 세정에 의해 완전히 차단하지 못함에 따라 반도체소자의 누설전류를 형성하여 반도체소자의 동작불량을 야기시키는 문제점이 있었다.As described above, in the conventional method of manufacturing a semiconductor device, when the nitride film is etched by using a photoresist pattern, the produced polymer and foreign substances act as an etch stop layer of a subsequent semiconductor substrate, causing defects in the PIG process. As a result, the leakage current of the semiconductor device may not be completely blocked, thereby causing a malfunction of the semiconductor device.
본 발명은 상기한 바와같은 종래의 문제점을 해결하기 위하여 창안한 것으로, 본 발명의 목적은 질화막을 식각할 때, 생성된 폴리머 및 이물질을 효과적으로 제거하여 반도체소자의 동작불량을 최소화할 수 있는 반도체소자의 제조방법을 제공하는데 있다.SUMMARY OF THE INVENTION The present invention has been made to solve the conventional problems as described above, and an object of the present invention is to remove the polymer and foreign substances effectively when etching the nitride film, thereby minimizing the malfunction of the semiconductor device. To provide a method of manufacturing.
도1a 내지 도1e는 종래 반도체소자의 제조방법을 보인 수순단면도.1A to 1E are cross-sectional views showing a conventional method for manufacturing a semiconductor device.
도2a 내지 도2g는 본 발명의 일 실시예를 보인 수순단면도.Figures 2a to 2g is a cross-sectional view showing an embodiment of the present invention.
***도면의 주요부분에 대한 부호의 설명****** Explanation of symbols for main parts of drawing ***
11:반도체기판 12:버퍼산화막11: semiconductor substrate 12: buffer oxide film
13:질화막 14:폴리머 또는 이물질13: Nitride film 14: Polymer or foreign substance
15:로코스 산화막 PR11:감광막15: locose oxide film PR11: photosensitive film
상기한 바와같은 본 발명의 목적을 달성하기 위한 반도체소자의 제조방법은 반도체기판 상에 순차적으로 버퍼산화막과 질화막을 형성하는 공정과; 상기 질화막의 상부에 로코스 감광막 패턴을 형성한 후, 이를 적용하여 질화막을 과도식각하는 공정과; 상기 감광막 패턴을 제거한 후, 세정을 실시하는 공정과; 상기 질화막의 과도식각으로 인해 노출된 반도체기판의 표면상에 로코스 산화막을 형성한 후, 이를 제거하는 공정과; 상기 잔류하는 질화막을 하드 마스크로 적용하여 반도체기판을 식각하는 공정을 구비하여 이루어지는 것을 특징으로 한다.A semiconductor device manufacturing method for achieving the object of the present invention as described above comprises the steps of sequentially forming a buffer oxide film and a nitride film on a semiconductor substrate; Forming a LOCOS photoresist pattern on the nitride film, and then applying the same to overetch the nitride film; Removing the photosensitive film pattern, and then performing cleaning; Forming a LOCOS oxide film on the surface of the semiconductor substrate exposed by the overetching of the nitride film, and then removing the LOCOS oxide film; And etching the semiconductor substrate by applying the remaining nitride film as a hard mask.
이하, 상기한 바와같은 본 발명에 의한 반도체소자의 제조방법을 도2a 내지 2g에 도시한 수순단면도를 일 실시예로 하여 상세히 설명한다.Hereinafter, a method of manufacturing a semiconductor device according to the present invention as described above will be described in detail with reference to a cross-sectional view of the procedure shown in FIGS. 2A to 2G.
먼저, 도2a에 도시한 바와같이 반도체기판(11)의 상부에 순차적으로 버퍼산화막(12)과 질화막(13)을 형성한다.First, as shown in FIG. 2A, a buffer oxide film 12 and a nitride film 13 are sequentially formed on the semiconductor substrate 11.
그리고, 도2b에 도시한 바와같이 상기 질화막(13)의 상부에 감광막(PR11)을 도포한 후, 로코스 사진식각공정을 통해 패터닝하여 감광막(PR11) 패턴을 형성한다.As shown in FIG. 2B, the photoresist film PR11 is coated on the nitride film 13, and then patterned through a LOCOS photolithography process to form a photoresist film PR11 pattern.
그리고, 도2c에 도시한 바와같이 상기 감광막(PR11) 패턴을 적용하여 질화막(13)을 식각한다. 이때, 질화막(13)의 과도식각으로 인해 버퍼산화막(12)뿐만 아니라 반도체기판(11)의 일부도 식각되며, 그 식각된 표면에는 미설명부호 '14'로 도시한 바와같이 식각시에 발생한 폴리머 또는 반도체기판(11)의 불량 시드가 형성된다.As illustrated in FIG. 2C, the nitride film 13 is etched by applying the photosensitive film PR11 pattern. At this time, due to the excessive etching of the nitride film 13, not only the buffer oxide film 12 but also a part of the semiconductor substrate 11 is etched, and the polymer generated at the time of etching as shown by reference numeral '14' on the etched surface. Alternatively, a defective seed of the semiconductor substrate 11 is formed.
그리고, 도2d에 도시한 바와같이 상기 감광막(PR11) 패턴을 제거하고, 질화막(13) 식각시에 생성된 폴리머와 이물질을 제거하기 위한 세정을 실시한다.As shown in FIG. 2D, the photoresist film PR11 pattern is removed, and a cleaning is performed to remove the polymer and foreign substances generated during the etching of the nitride film 13.
그리고, 도2e에 도시한 바와같이 상기 질화막(13)의 과도식각으로 인해 노출된 반도체기판(11)의 표면에 로코스 산화막(15)을 형성한다. 이때, 상기 세정에 의해 완전히 제거되지 않은 폴리머와 이물질이 로코스 산화막(15) 내에서 같이 성장되며, 로코스 산화막(15)은 100Å∼500Å의 두께로 형성하는 것이 바람직하다.As shown in FIG. 2E, the LOCOS oxide film 15 is formed on the surface of the semiconductor substrate 11 exposed by the overetching of the nitride film 13. At this time, it is preferable that the polymer and the foreign matter not completely removed by the cleaning are grown together in the LOCOS oxide film 15, and the LOCOS oxide film 15 is formed to a thickness of 100 kPa to 500 kPa.
그리고, 도2f에 도시한 바와같이 상기 폴리머와 이물질이 같이 성장된 로코스 산화막(15)을 제거한다. 이때, 로코스 산화막(15)은 불산계열의 케미칼(chemical)을 이용하여 제거하는 것이 바람직하다.As shown in FIG. 2F, the LOCOS oxide film 15 having the polymer and the foreign matter grown together is removed. At this time, it is preferable to remove the LOCOS oxide film 15 using a chemical of hydrofluoric acid series.
그리고, 도2g에 도시한 바와같이 상기 잔류하는 질화막(13)을 하드 마스크로 적용하여 반도체기판(11)을 식각한다.2G, the semiconductor substrate 11 is etched by applying the remaining nitride film 13 as a hard mask.
상기한 바와같은 본 발명에 의한 반도체소자의 제조방법은 질화막의 식각에서 발생하는 폴리머 및 이물질이 세정 이후에도 잔류하는 것을 로코스 산화막의 성장시에 같이 성장시킨 후, 로코스 산화막을 제거하여 완전히 제거함에 따라 후속 반도체기판의 식각공정에서 발생할 수 있는 불량을 근본적으로 차단하여 반도체소자의 동작불량을 방지함으로써, 제품의 수율을 향상시킬 수 있는 효과가 있다.In the method of manufacturing a semiconductor device according to the present invention as described above, the polymer and the foreign substances generated in the etching of the nitride film are grown after the growth of the locose oxide film after the growth, and then completely removed by removing the locose oxide film. Accordingly, by fundamentally blocking the defects that may occur in the subsequent etching process of the semiconductor substrate to prevent the malfunction of the semiconductor device, there is an effect that can improve the yield of the product.
Claims (3)
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| KR1019990009001A KR100313507B1 (en) | 1999-03-17 | 1999-03-17 | Fabricating method of semiconductor device |
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| KR1019990009001A KR100313507B1 (en) | 1999-03-17 | 1999-03-17 | Fabricating method of semiconductor device |
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| KR20000060583A true KR20000060583A (en) | 2000-10-16 |
| KR100313507B1 KR100313507B1 (en) | 2001-11-07 |
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| KR1019990009001A KR100313507B1 (en) | 1999-03-17 | 1999-03-17 | Fabricating method of semiconductor device |
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| JPS559414A (en) * | 1978-07-05 | 1980-01-23 | Toshiba Corp | Manufacturing method of semiconductor device |
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