KR20030058196A - Liquid crystal display - Google Patents

Abstract

PURPOSE: A liquid crystal display device is provided to apply signals from data pads to data lines in spite of a short caused by cracking of a data pad link part by forming two data line patterns separated from each other to the data pad link part. CONSTITUTION: A liquid crystal display device includes an LCD panel formed of a thin film transistor substrate and a color filter substrate with a liquid crystal layer interposed between the substrates. The thin film transistor substrate is formed with image display parts aligned with liquid cells in the shape of matrix, and gate and data pads formed edge areas not to be overlapped with the color filter substrate and respectively connected to gate and data lines of the display parts. The data pad link parts(147), in which data pads(145) are connected with the data lines(143), are formed with a plurality of data lines.

Description

Liquid crystal display {LIQUID CRYSTAL DISPLAY}

The present invention relates to a liquid crystal panel and a liquid crystal display device having the same, and more particularly, to a liquid crystal panel and a liquid crystal display device having the same so as to maximize utilization efficiency of a mother substrate on which the liquid crystal panels are manufactured.

In general, a liquid crystal display device displays a desired image by individually supplying data signals according to image information to liquid crystal cells arranged in a matrix form, and adjusting a light transmittance of the liquid crystal cells. to be.

Accordingly, a liquid crystal display device includes: a liquid crystal panel in which liquid crystal cells in pixel units are arranged in a matrix form; A driver integrated circuit (IC) for driving the liquid crystal cells is provided.

The liquid crystal panel includes a color filter substrate and a thin film transistor array substrate facing each other, and a liquid crystal layer filled in a spaced interval between the color filter substrate and the thin film transistor array substrate.

Further, data lines for transmitting a data signal supplied from a data driver integrated circuit to the liquid crystal cells on the thin film transistor array substrate of the liquid crystal panel, and gate lines for transmitting a scan signal supplied from the gate driver integrated circuit to the liquid crystal cells. Are orthogonal to each other, and liquid crystal cells are defined at each intersection of these data lines and the gate lines. In addition, one end of the data lines and the gate lines may include a data pad and a gate pad to which a data signal and a scan signal are applied from the data driver integrated circuit and the gate driver integrated circuit.

The gate driver integrated circuit sequentially supplies scanning signals to the gate lines so that the liquid crystal cells arranged in a matrix form are sequentially selected one by one, and the selected one line of liquid crystal cells is selected from the data driver integrated circuit. The data signal is supplied.

Meanwhile, a common electrode and a pixel electrode are formed on opposite inner surfaces of the color filter substrate and the thin film transistor array substrate to apply an electric field to the liquid crystal layer. In this case, the pixel electrode is formed for each liquid crystal cell on the thin film transistor array substrate, while the common electrode is integrally formed on the entire surface of the color filter substrate. Therefore, by controlling the voltage applied to the pixel electrode in a state where a voltage is applied to the common electrode, it is possible to individually control the light transmittance of the liquid crystal cells.

Each liquid crystal cell is also provided with a thin film transistor used as a switching element. In the liquid crystal cells in which the scan signal is supplied to the gate electrode of the thin film transistor through the gate lines, a conductive channel is formed between the source electrode and the drain electrode of the thin film transistor, wherein the conductive line is supplied to the source electrode of the thin film transistor through the data lines. As the data signal is supplied to the pixel electrode via the drain electrode of the thin film transistor, an electric field is applied to the liquid crystal layer of the liquid crystal cell.

In the thin film transistor array substrate and the color filter substrate constituting the liquid crystal panel, a plurality of unit panels are formed on a large glass substrate, and in general, four or six units are formed at the same time, and each unit panel is cut to improve yield. have. A manufacturing process of such a liquid crystal display will be briefly described as follows.

First, unit pixels including a thin film transistor, a pixel electrode, and a storage capacitor are formed in a matrix form on a thin film transistor array substrate, and a black matrix, R, G, B color filters, and a common electrode are sequentially formed on a color filter substrate. do.

Next, an alignment layer is formed on the thin film transistor array substrate and the color filter substrate, and then rubbing is performed. At this time, rubbing is a process of rubbing the cloth with the surface of the alignment film at a uniform pressure and speed, by rubbing, the polymer chains on the surface of the alignment film are aligned in a predetermined direction to determine the initial alignment direction of the liquid crystal.

Then, a seal pattern is printed on the color filter substrate, and a spacer is spread on the thin film transistor array substrate. In this case, the seal pattern printing and the spacer spread may be performed in the reverse of the above depending on the process conditions, or may be simultaneously performed on any one substrate. The seal pattern provides a gap for injecting the liquid crystal together with the spacer and prevents leakage of the injected liquid crystal.

Then, the thin film transistor array substrate and the color filter substrate are bonded together.

Next, the bonded thin film transistor array substrate and the color filter substrate are cut into unit panels. In this case, the liquid crystal display device forms a plurality of thin film transistor array substrates on a large mother substrate, forms a plurality of color filter substrates on a separate mother substrate, and then joins the two mother substrates to simultaneously connect the plurality of liquid crystal panels. Since it forms and aims at improving a yield, it cuts into a unit panel.

In general, the cutting of the unit panel is performed by a scribe process of forming a cut line on the surface of a substrate using a diamond pen having a hardness higher than that of glass, and a break process of applying a mechanical force to cut the unit panel. .

Then, liquid crystal is injected into the cut unit panel, and the injection hole is sealed.

In general, in the manufacturing process of the initial liquid crystal display device, liquid crystals are injected into a plurality of liquid crystal panels and then cut into a unit panel. However, as the size of the unit panel increases, a method of cutting a unit panel and then injecting liquid crystals is used.

The unit liquid crystal panel as described above will be described in detail with reference to the accompanying drawings.

FIG. 1 is an exemplary view showing a schematic planar structure of a unit liquid crystal panel in which a thin film transistor array substrate and a color filter substrate of a liquid crystal display are bonded to each other.

Referring to FIG. 1, the liquid crystal panel 100 is connected through an image display unit 113 in which liquid crystal cells are arranged in a matrix, and gate lines and gate pad link units 118 of the image display unit 113. And a data pad 115 connected to the gate pad 114 and the data lines 107 and the data pad link 119. In this case, the gate pad part 114 and the data pad part 115 are formed in the edge region of the lower substrate 101 which does not overlap the upper substrate 102, and the gate pad part 114 is supplied from the gate driver integrated circuit. The gate signal to be supplied to the gate lines 108 of the image display unit 113, and the data pad unit 115 supplies the data signal supplied from the data driver integrated circuit to the data lines 107 of the image display unit 113. Supply.

Although not shown in detail in the drawing, data lines 107 to which image information is applied and gates 108 to which a gate signal is applied are vertically intersected on the lower substrate 101 of the image display unit 113. And a thin film transistor for switching the liquid crystal cells at the intersection thereof, a pixel electrode connected to the thin film transistor to drive the liquid crystal cell, and a protective film formed on the front surface to protect the electrode and the thin film transistor.

In addition, the upper substrate 102 of the image display unit 113 includes color filters separated and applied to each cell region by a black matrix, and a common transparent electrode serving as a counter electrode of the pixel electrode formed on the lower substrate 101. do.

The lower substrate 101 and the upper substrate 102 configured as described above are provided with a cell-gap by spacers and a sealing portion 116 coated with a sealing material on the outside of the image display portion 113. By the liquid crystal is filled in the cell gap.

FIG. 2 is an exemplary view showing a cross-sectional structure of a liquid crystal panel by combining a lower substrate 101 having a thin film transistor array fabricated as described above and an upper substrate 102 having a color filter formed thereon.

As shown in the figure, in the liquid crystal panel in which the lower substrate 101 and the upper substrate 102 are bonded by the sealing unit 116, the upper substrate on which the color filter is formed on the lower substrate 101 on which the thin film transistor array is formed. Since the gate pad part 114 and the data pad part 115 are formed at one edge not overlapping with the 102, the upper substrate 102 is connected to the gate pad part 114 and the gate pad link of the lower substrate 101. The portion 118, the data pad 115, and the data pad link portion have to be removed by a dummy region 170 corresponding to an area protruding therefrom.

After the lower substrate 101 and the upper substrate 102 are bonded together, the liquid crystal panels are individually cut through a scribe process and a break process. In this case, a dummy formed in an area where the upper substrate 102 of the lower substrate 101 is spaced apart from each other. Region 170 is removed.

However, during the scribe process along the cutting line 171, the dummy region 170 of the upper substrate 102 scribes on the link portion corresponding to the cutting line 171 and connected to the data pad and the data line. Cracks occur due to the impact applied to the lower substrate during the process.

3 illustrates a crack generated in the data pad link unit 119 to which the data line and the data pad corresponding to the scribe line of the upper substrate are connected as described above.

As shown in the figure, the crack 173 generated in the data line and the data pad link portion 119 along the upper cutting line of the upper substrate is gradually enlarged during the subsequent process, and eventually the data pad link portion 119 This results in disconnection of the data line 107.

In general, in the liquid crystal display device manufactured through the 5 mask process, the data pad is formed of a source / drain electrode layer formed on the gate insulating film. In the liquid crystal display device manufactured through the 4 mask process, the data pad is formed on the gate insulating film (not shown). The source / drain electrode layer is formed on the formed active layer. In this case, since the stress difference with the active layer is greater than that of the gate insulating layer due to the characteristics of the source / drain electrode material, the data pad link as described above in the liquid crystal display device manufactured by the four-mask process Negative disconnection is more likely to occur.

Accordingly, the present invention has been made to solve the conventional problems as described above, an object of the present invention is to form a plurality of data lines in the data pad portion corresponding to the cutting line of the upper substrate scribe on the cutting line of the upper substrate This is to prevent disconnection of the data pad due to cracks generated in the data pad due to the impact caused by the process.

FIG. 1 is an exemplary view showing a schematic planar structure of a unit liquid crystal panel in which a thin film transistor array substrate and a color filter substrate of a liquid crystal display are bonded to each other.

2 is an exemplary cross-sectional view of a liquid crystal panel in which a lower substrate on which thin film transistor array substrates are formed and an upper substrate on which color filters are formed are bonded to each other.

FIG. 3 is a view illustrating cracks occurring in a data pad link unit to which data pads and data pads corresponding to scribe lines of an upper substrate are connected;

4 illustrates a liquid crystal display according to the present invention.

FIG. 5 is an enlarged view of a data pad link unit to which a data pad and a data line are connected in FIG. 4; FIG.

6 illustrates another embodiment of the present invention.

FIG. 7 is a cross-sectional view taken along a cutting line A-A 'in FIG. 5. FIG.

8A to 8D are exemplary diagrams showing a sequential cross-sectional configuration for forming four masks formed on a substrate of a thin film transistor, a gate pad link portion, and a data pad link portion cut along a line B-B 'in FIG. 4.

9 illustrates another embodiment of the present invention.

*** Explanation of symbols for main parts of drawing ***

142: gate line 143: data line

144: gate pad 145: data pad

146: gate link unit 147: data link unit

The liquid crystal display device for achieving the object of the present invention as described above is a liquid crystal panel in which a lower substrate on which a thin film transistor array is formed and an upper substrate on which a color filter is formed are bonded by a seal, wherein the liquid crystal cells are formed in a matrix form on the lower substrate. A gate pad and a data pad formed in an edge region not overlapping with the upper substrate, the gate pad and a data pad arranged in the edge portion of the upper substrate. A plurality of data lines are formed in the cutout region or an area corresponding to the outside of the cutout region.

The gate pad supplies a scan signal supplied from a gate driver integrated circuit to gate lines of an image display unit, and the data pad supplies image information supplied from a data driver integrated circuit to data lines of an image display unit.

The liquid crystal display of the present invention having the features as described above will be described in detail with reference to the accompanying drawings.

4 illustrates a liquid crystal display of the present invention.

As shown in the drawing, a plurality of gate lines 142 are formed in parallel in the horizontal direction on the transparent insulating substrate 141 formed of a material such as glass, and the plurality of data lines 143 are arranged in parallel in the vertical direction. A gate pad 144 and a data pad connected to the gate line 142 and the data line 143 through the gate pad link unit 146 and the data pad link unit 147 to apply an external signal. 145 is formed at an end of each line, and the data line 143 is formed of a plurality of lines in a partial region connected to the data pad 145.

In addition, a thin film transistor, which is a switching element, is formed at an intersection of the gate line 142 and the data line 143. The thin film transistor 150 includes a gate electrode 151, a gate insulating layer (not shown), a semiconductor layer 155, a source electrode 152, and a drain electrode 153. The gate electrode 151 of the thin film transistor branches in the gate line 142, and the source electrode 152 branches in the data line 143. The drain electrode 153 of the thin film transistor is electrically connected to the pixel electrode 158 of the pixel defined by the respective gate line 142 and the data line 143.

The gate pad 144 is electrically connected to a gate driver integrated circuit (not shown) to supply a gate signal supplied from the gate driver integrated circuit to the gate lines 142, and the data pad 145 is a data driver integrated circuit. The image information, which is electrically connected to the data driver IC and is supplied from the data driver integrated circuit, is supplied to the data line 143.

As described above, a plurality of data lines connected to the data pad 145 are formed to connect the data pad and the data line due to an impact applied to the lower substrate during the scribing process for cutting the upper substrate on which the color filter is formed. Even if a crack occurs in the link part, an extra data line electrically connected to the data pad is formed, thereby preventing disconnection of the data pad and the data line.

Hereinafter, the present invention will be described in more detail with reference to an enlarged view of a link unit 147 in which the data pad 145 and the data line 143 are connected by a plurality of data lines.

5 is an enlarged view of the data pad link unit 147 to which the data pad 145 and the data line 143 are connected in the liquid crystal display of the present invention.

As shown in the drawing, a bifurcated data line 143 is connected to a data line 143 connection region connected to a data pad 145 corresponding to a cutting line for removing a dummy region of an upper substrate on which a color filter is formed. Formed.

Generally, cracks occur in the data line region of the lower substrate corresponding to the region outside the cut line, that is, the region in which the dummy portion of the upper substrate is removed, along the cutting line 171 of the upper substrate.

Therefore, the two-pronged data line 143 region preferably includes the cutting line 171 of the upper substrate or is formed in the outer region of the cutting line 171.

FIG. 6 illustrates an embodiment in which a two-prong data line 143 region is formed in an outer region of the cutting line 171 of the upper substrate.

As shown in Fig. 5 or 6, by forming a two-pronged data line in the lower or outer region 175 of the cutting break line of the upper substrate, the data due to the impact due to the cutting process of the upper substrate Even if a crack occurs in the data pad link unit 147 to which the pad 145 and the data line 143 are connected, and thus a disconnection occurs between the data pad 145 and the data line 143, a signal is received from the data pad through an extra data line. Can be authorized.

In addition, since the probability that a two-pronged data line is cracked at the same time is very low compared to the case where the two-pronged data line is connected, the disconnection defect between the data pad and the data line due to the crack generation can be reduced.

FIG. 7 is a cross-sectional view taken along a cutting line A-A 'of the upper substrate with respect to the data line formed in FIG. 6.

As shown in FIG. 5, the bifurcated data line shown in FIGS. 5 to 6 is fabricated through a four mask process of a liquid crystal display, and is patterned on the gate insulating layer 150 formed on the transparent substrate 141. The active layer 154 and the data line 143 are formed. The active layer 154 includes a semiconductor layer 154a and an n + doped ohmic contact layer 154b. A passivation layer 155 is formed on the substrate on which the active layer 154 and the data line 143 are formed.

Hereinafter, a method of forming the thin film transistor 150, the gate pad link unit 146, and the data pad link unit 147 by cutting along the BB ′ line in FIG. 1 is illustrated in FIGS. 8A to 8J. Referring to the sequential cross-sectional configuration shown in detail as follows.

First, as shown in FIG. 8A, a metal material is sputter deposited on the substrate 141 on which the thin film transistor region, the pixel region, the gate pad link portion, and the data pad link portion are defined, and patterned through a first mask to form the gate pad. The gate line 142 is formed on the substrate of the link portion, and the gate electrode 151 is formed on the substrate of the thin film transistor region.

8B, the gate insulating film 150, the active layer 154, and the metal film are sequentially deposited on the entire surface of the substrate 141 on which the gate line 04 and the gate insulating film 151 are formed. Patterning through the second mask to form an active layer and a source / drain electrode 153 to expose the semiconductor layer 154a in the thin film transistor region, and a data line on the gate insulating layer 150 on the data pad link portion. 143 is formed. In this case, the active layer 154 is formed by stacking an amorphous silicon semiconductor layer 154a and an ohmic contact layer 154b of phosphorous-doped amorphous silicon material, and a color filter formed on the data pad link part. The pair of active layers 154 and the data line 143 may be spaced apart from each other by a cut portion of the upper substrate or an area formed outside the cut portion. The data line 143 pattern is formed to be narrower than the width of the data line formed in the pixel area, and the data line formed in the pixel area due to a crack formed in the data line 143 due to the impact received during the cutting process of the cutout part. In order to reduce defects due to disconnection of the data pad part, two data line 143 patterns are formed.

As illustrated in FIG. 8C, the chemical vapor phase is formed on the entire surface of the gate insulating layer 150 including the exposed semiconductor layer 154a and the source electrode 153a, the drain electrode 153b, and the data line 143. After depositing a protective film 155 made of an inorganic insulating material such as SiNx through a deposition method, the drain contact hole 160 may be selectively etched through a third mask to expose a portion of the drain electrode 153 of the thin film transistor region. To form. Although not shown in the drawing, a gate pad contact hole exposing a part of the gate line and a data pad contact hole exposing a part of the data line are formed in the gate pad part and the data pad part, respectively.

As shown in FIG. 8D, the transparent electrode material is sputter deposited on the passivation layer 155 and then patterned through a fourth mask to form a drain electrode 153a through the drain contact hole 160 of the thin film transistor region. Although not shown in the drawing, a gate pad electrode electrically connected to a gate line through a gate pad contact hole of a gate pad part, and data electrically connected to a data line through a data pad contact hole of the data pad part, respectively. The pad electrode is formed.

In the liquid crystal display device manufactured by applying four masks as described above, the active layer 154 and the source / drain electrode 153 constituting the thin film transistor are simultaneously patterned by a diffraction mask (second mask).

As described above, the present invention forms two data line patterns by forming two data line patterns in a cut portion of a lower substrate on which a color filter is formed or a data pad corresponding to a data pad corresponding to an outer region of the cut portion and a data line. Even if a crack is formed and disconnected, a signal can be applied from the data pad to the data line through the other data line pattern.

In addition to the structure illustrated in FIG. 7, a pattern made of a metal, an insulator, or a material of semiconductors is formed between data line patterns formed at predetermined intervals, as shown in FIG. 9, and is transmitted to the link unit during the cutting process of the upper substrate. Can alleviate

As described above, the liquid crystal display of the present invention includes two data line patterns spaced apart at predetermined intervals from a cutout portion of a lower substrate on which a color filter is formed or a data pad link portion connected to a data pad corresponding to an outer region of the cutout portion and a data line. By forming a crack, a signal is applied from the data pad to the data line through the other data line pattern even when a crack is formed in the link portion.

Claims (6)

A liquid crystal panel in which a lower substrate on which a thin film transistor array is formed and an upper substrate on which a color filter is formed are bonded by a seal, wherein the lower substrate includes an image display unit in which liquid crystal cells are arranged in a matrix, and an edge region not overlapping with the upper substrate. A liquid crystal display device comprising: a gate pad connected to gate lines of an image display unit and a data pad connected to data lines, the data line being formed on a data pad link unit connected to the data pad and the data line; The liquid crystal display device, characterized in that a plurality. The gate driver integrated circuit of claim 1, further comprising: a gate driver integrated circuit connected to a gate pad for inputting a gate signal to the gate line to supply a gate signal to the gate pad, and a data pad to input a data signal to the data line; And a data driver integrated circuit for supplying a data signal to the data pad. The liquid crystal display of claim 1, wherein two data lines are formed on the data pad link unit. 2. The liquid crystal display device according to claim 1, wherein a plurality of data lines formed in the data pad link portion are formed in a region corresponding to a cutout portion of the upper substrate or an outer side of the cutout portion. The liquid crystal display of claim 1, wherein an impact buffer layer pattern is formed between the data lines formed in the data pad link portion. 6. The liquid crystal display device according to claim 5, wherein the impact buffer layer is a metal layer, an insulator layer or a semiconductor layer.