KR100467176B1 - Array pannel of liquid crystal display and fabricating method the same - Google Patents

Abstract

The present invention relates to a liquid crystal display device, and more particularly, in forming a gate shorting line and a data shorting line for the purpose of preventing destruction of a device due to static electricity by stacking two layers of metal films on an array substrate.

The upper Mo metal constituting the shorting line includes a neck-shaped Mo-bridge having a width of 3.5 to 4.5 ㎛ and a length of several ㎛ or less,

In the neck-shaped Mo-bridge, an inclined surface that forms a boundary between the neck-shaped Mo-bridge and an adjacent portion having a different width is between 70 and 80 degrees, and the inclined angle of the inclined surface opposite thereto is 100 to 110 degrees. ego,

The distance between the Al metals of the lower layer forming the neck-shaped Mo-bridge is several μm or less so that each shorting line can stably maintain a short circuit, and has a structure capable of effectively disconnecting in a subsequent disconnection process. A method for manufacturing a liquid crystal display device and a liquid crystal display device manufactured by the method.

Description

Array panel for liquid crystal display device and manufacturing method thereof {Array pannel of liquid crystal display and fabricating method the same}

The present invention relates to an image display device, and more particularly, to a method of manufacturing a liquid crystal display device (LCD) including a thin film transistor (TFT) and a liquid crystal display device according to the method. It is about.

Recently, as the information society has progressed rapidly, a display field for processing and displaying a large amount of information has been developed.

Recently, the need for a flat panel display (plate panel display) has emerged in order to meet the era of thinning, light weight, low power consumption. Accordingly, a thin film transistor-liquid crystal display (hereinafter referred to as TFT-LCD) having excellent color reproducibility has been developed.

In general, the driving principle of the liquid crystal display device uses the optical anisotropy and polarization of the liquid crystal. Since the liquid crystal is thin and long in structure, the liquid crystal has directivity in the arrangement of molecules, and the direction of the molecular arrangement can be controlled by artificially applying an electric field to the liquid crystal.

Accordingly, when the molecular arrangement direction of the liquid crystal is arbitrarily adjusted, the molecular arrangement of the liquid crystal is changed, and light polarized by optical anisotropy may be arbitrarily modulated to express image information.

Currently, the active matrix liquid crystal display (AM-LCD) in which the above-described thin film transistor and the pixel electrode connected to the thin film transistor are arranged in a matrix manner is attracting the most attention because of its excellent resolution and ability to implement video.

In general, the structure of a liquid crystal panel constituting a liquid crystal display is as follows.

1 is a cross-sectional view showing a part of a general liquid crystal panel.

In the liquid crystal panel 20, two substrates 2 and 4 having various kinds of elements are arranged to correspond to each other, and the liquid crystal layer 10 is sandwiched between the two substrates 2 and 4. .

The liquid crystal panel 20 includes a color filter substrate 4 having a color filter expressing color and an array panel 2 having a switching circuit capable of converting a molecular arrangement direction of the liquid crystal layer 10. .

The color filter substrate 4 has a color filter layer 8 for realizing color, and a common electrode 12 covering the color filter layer 8. The common electrode 12 serves as one electrode for applying a voltage to the liquid crystal layer 10. The array panel 2 includes a thin film transistor S serving as a switching role and a pixel electrode serving as an electrode to receive a signal from the thin film transistor S and apply a voltage to the liquid crystal layer 10. 14).

The portion where the pixel electrode 14 is formed is called the pixel portion P. FIG.

In addition, in order to prevent leakage of the liquid crystal 10 injected between the color filter substrate 4 and the array panel 2, the color filter substrate 4 and the array panel 2 have sealants coated at edges thereof. Sealed with (Sealant: 6).

A plurality of thin film transistors S is positioned in the array panel 2, and a plurality of pixel electrodes 14 connected to the thin film transistors are arranged.

The above-described liquid crystal display device adopts a method of fabricating an array panel in which color filter substrates and thin film transistors are arranged through different processes, and bonding them together.

The structure of the array panel for the liquid crystal display device is as shown in FIG.

In the conventional array panel of the liquid crystal display device, the gate shorting bar 36 and the gate shorting bar 36 branch from the left and right edge portions of the transparent substrate 1 to form a gate pad 35. A plurality of gate lines 30 connected to the gate pads 35 are integrally formed.

In addition, data shorting bars 46 are formed at upper and lower edge portions of the transparent substrate 1, and a plurality of data pads 45 are formed by branching from the data shorting bars 46. A data line 40 connected to 45 is formed in a matrix by crossing the gate line 30.

The data pad 45 and the data shorting bar 46 may be formed integrally by simultaneously patterning the data line 40 when forming the data line 40. However, in order to simplify the manufacturing process, the gate line 30 is generally formed. At the time of forming, the patterning bar 46 may be simultaneously patterned. In this case, the data shorting bar 46 may be in contact with the data line 40 through a contact hole (not shown) formed in the gate insulating layer.

A connection structure of the gate shorting bar 36, the gate line 30, and the gate pad 35 will be described in more detail with reference to FIG. 3 (an enlarged view of a portion of FIG. 2).

The plurality of gate lines 30a and 30b are divided into odd and even numbers, respectively, and the odd gate lines 30a are connected to the odd gate pads 35a and the first shorting bar 36a and the even gates. The gate line 30b is electrically connected to the even-numbered gate pad 35b and the second shorting bar 36b, respectively.

A pixel electrode 14 is formed in an area where the two adjacent gate lines 30a and 30b and the two adjacent data lines 40a and 40b cross each other, and are electrically connected to the pixel electrode 14. The thin film transistor S connected to the thin film transistor S is formed in the vicinity of an intersection area between the gate lines 30a and 30b and the data lines 40a and 40b.

In this case, the gate shorting bars 36a and 36b are formed to facilitate the operation test of the thin film transistor S, and the second gate shorting bar 36b is formed on the array substrate 2 in order to reduce the area occupied. Located on the outside of the side cutting line (solid line A), and after the color filter substrate is bonded after being cut along the side cutting line (solid line A) and separated, the first shorting bar ( 36a) is located inside the side cutting line (solid line A) of the array panel 2, and in particular, the internal device is destroyed by static electricity that may occur during the subsequent manufacturing process to manufacture the thin film transistor (S). In order to prevent the gate shorting line 50 is further included.

Although the above descriptions of the gate shorting bar, the gate pad, the gate shorting line, and the gate line are not shown in the drawings, the description also applies to the data shorting bar, the data pad, the data shorting line, and the data line.

In particular, the gate and data shorting lines are electrically disconnected in a process of forming a source electrode and a drain electrode, which will be described later. Each of the first shorting bars has completed the operation test of the thin film transistor after the shorting lines are disconnected. Electrical disconnection occurs in a proper process before bonding to the color filter substrate.

The manufacturing process of the above-described array panel 2 will be described in more detail with reference to FIGS. 3 and 4A to 4E (sectional views taken along the line II-II of FIG. 3).

As shown in FIG. 4A, the gate electrode 70 and the gate shorting line 50 may be formed by depositing a metal film on the transparent substrate 1 and then forming a positive photoresist on the metal film. (photo-resist) is applied, the first exposure mask having a predetermined pattern is positioned, the photoresist is exposed and developed, the metal film is etched using a predetermined etchant according to the developed pattern, and then the metal film It is made by removing the remaining photoresist from above.

At this time, the gate shorting bars 36a and 36b, the gate pads 35a and 35b, and the gate lines 30a and 30b branching from the gate pads 35a and 35b shown in FIG. 3 are formed in the above-described process.

In addition, in the above-described process, the data shortening bar, the data pad, and the data shorting line may be formed together as described above (not shown).

Subsequently, as shown in FIG. 4B, a gate insulating film 75 such as a silicon nitride film (SiNx) or a silicon oxide film (SiOx) is formed, and the semiconductor layer 80 made of amorphous silicon (a-Si: H) is formed on the gate insulating film of the gate electrode portion. And an ohmic contact layer 90 made of amorphous silicon (n + a-Si: H) doped with n + ions in succession to form an island shape.

Subsequently, a Mo metal film is deposited on the entire surface of the substrate on which the ohmic contact layer 90 is formed, a positive photoresist is applied on the Mo metal film, and then an exposure mask having a predetermined pattern is positioned. Thereafter, the photoresist is exposed and developed to form a photoresist pattern, and a metal layer of the lower layer is etched along the photoresist pattern to form a separate source electrode 95 and a drain electrode 96, and the source electrode and the drain electrode ( The ohmic contact layer 90 is etched using the masks 95 and 96 as a mask and separated from each other at predetermined intervals so that the ohmic contact layer 90a and the drain electrode 96 come into contact with the source electrode 95, respectively. ) And an ohmic contact layer 90b in contact with each other, and the remaining photoresist pattern is removed to form the same as in FIG. 4C.

In this case, a process of etching the gate insulating film 75 on the gate shorting line to expose a portion of the gate shorting line 50 and etching the gate shorting line 50 to electrically disconnect the gate shorting line 50.

The thin film transistor S is formed by forming the gate electrode 70, the semiconductor layer 80, the separated ohmic contact layers 90a and 90b, the source electrode 95, the drain electrode 96, and the like. The protective film 100 made of a silicon nitrate (SiNx) film, a silicon oxide (SiOx) film, BCB (benzocyclobutene), or the like is formed to cover the entire surface of the substrate.

The photoresist is spin-coated on the passivation layer 100, and the exposed portion 110 of the passivation layer 100 on the drain electrode 96 of the thin film transistor S is exposed by exposing using a mask having a predetermined pattern. A photoresist film 120 having is formed as shown in Fig. 4D.

Subsequently, the substrate on which the photoresist layer 120 is formed is placed in an etching chamber, and the protective layer of the exposed protective layer portion 110 is etched and etched to form a drain electrode contact hole 130 through which the drain electrode 96 is exposed. After removing the photoresist film, an Indium Tin Oxide (ITO) film is formed on the entire surface of the substrate as shown in FIG. 4E, and patterned into a predetermined shape through the drain electrode 96 and the drain electrode contact hole 130. The pixel electrode 14 in contact is constituted.

The lower array substrate of a conventional liquid crystal display device is manufactured through the process described so far, and especially in a large area and high resolution liquid crystal display device, which is caused by signal delay due to wiring resistance of the gate wiring (gate electrode). Low-resistance aluminum (Al) is used as the metal of the gate wiring in order to overcome the disadvantage that the quality deterioration due to cross-talk may occur.

However, aluminum has a weak chemical corrosion resistance, and may cause a wiring defect problem due to hillock formation in a subsequent high temperature process. In order to solve the above problem, Mo metal having high durability on aluminum is used as the gate wiring. The stacked structure is laminated, and the Mo metal is used again as a material constituting the source electrode and the drain electrode.

However, when the Al and Mo metal lamination structure described above is used as the gate wiring, the entire manufacturing process further includes the step of laminating the Mo metal on the upper portion of Al, and in the process of patterning and etching the gate wiring, The stacked Mo metal is subdivided into the process of patterning and etching, and the process of etching the lower Al metal, and the types of etchant used in each etching process are also different.

As a result, the stacking structure has a problem of increasing the production yield to increase the possibility of contaminating the substrate, the failure rate is higher.

Therefore, in order to solve the problem, when the stacked structure is used as a gate wiring, a Mo-bridge may be further included in a gate shorting line of an array substrate of a conventional liquid crystal display device.

The Mo-bridge will be described in detail with reference to FIG. 5 when forming the gate electrode and the gate shorting line using the stacked structure of Al metal and Mo metal as described above. When the upper layer portion 70a of the gate electrode and the upper layer portion 50a of the gate shorting line are formed by using the upper layer portion 50a of the gate shorting line, the neck-shaped Mo-bridge 45 is formed to be thinner than other portions. When the lower layer portion 70b of the gate electrode and the lower layer portion 50b of the gate shorting line are formed using an etchant capable of etching an Al metal, which is a lower layer, the lower layer portions 50b of the gate shorting line are separated from each other. To form.

That is, the metal layers of the upper and lower layers of the gate shorting line 50 and the gate electrode 70 are stacked in a chevron shape, and in particular, the lower layer portions 50b of the gate shorting line are etched to each other. Spaced at a distance of μm, the upper layer portion 50a of the gate shorting line is configured to include a neck-shaped Mo-bridge 45.

At this time, the length of the neck-shaped Mo-bridge 45 is usually several 10㎛ and even if the lower layer 50b of the gate shorting line is separated and spaced apart, the electrical flow of the gate shorting line 50 is the gate The upper layer portion 50a of the shorting line is made possible through the neck-shaped Mo-bridge 45 so that the gate shorting line 50 may serve to prevent static electricity.

Applying the neck-shaped Mo-bridge 45 described above, the neck-shaped Mo-bridge 45 is the same etchant in the process of etching and separating the source electrode and the drain electrode made of the same Mo metal by the etching process It is possible to simplify the disconnection process of the gate shorting line 50 by being etched and cut at the same time, and the neck-shaped Mo-bridge can also be applied to the data shorting line.

However, even when using the manufacturing method of the array substrate of the liquid crystal display device using the Mo-bridge, because the neck-shaped Mo-bridge is easily torn off by the physical impact applied in the subsequent process, the circuit is disconnected and the incidence rate of the defect is caused. There is still an increasing problem.

In addition, when the width of the neck-shaped Mo-bridge 45 is 4㎛ or more may occur a phenomenon that is not cut in the process of etching to separate the source and drain electrodes of the conventional, this may also be a cause of failure The problem is further included.

The present invention has been made to solve the above problems and provides a liquid crystal display device capable of stable short-circuit and separation of data and gate shorting lines.

1 is a cross-sectional view showing a part of a general liquid crystal panel.

2 is a schematic view showing a part of an array substrate for a general liquid crystal display device.

3 is an enlarged detailed view of a portion of FIG. 2;

4A to 4E are process cross-sectional views sequentially showing a manufacturing process of an array substrate of a general liquid crystal display device.

FIG. 5 is a cross-sectional view of a process of using a stacked structure as a gate wiring in a manufacturing process of an array substrate of a general liquid crystal display device.

6A through 6F are cross-sectional views sequentially illustrating a manufacturing process of an array substrate of a liquid crystal display device according to the present invention.

<Explanation of symbols for the main parts of the drawings>

150a: upper layer of the gate shorting line 150b: lower layer of the gate shorting line

160: neck-shaped Mo-bridge

The manufacturing process of the array substrate according to the present invention will be described in more detail with reference to FIGS. 6A to 6E.

First of all, Al is a low-resistance metal that can overcome the disadvantage of deterioration in image quality due to cross-talk caused by signal delay due to wiring resistance on the transparent substrate 101. The metal is deposited.

Thereafter, a durable Mo metal is laminated on the Al metal in order to solve a wiring defect problem due to hillock that may occur in a subsequent high temperature process, and a positive photoresist is applied on such a substrate as an example. After positioning the exposure mask having a predetermined shape, the photoresist is exposed to light to form a pattern of photoresist.

Subsequently, an upper layer portion 170a of the gate electrode and an upper layer portion 150a of the gate shorting line are formed using an etchant capable of etching the first Mo metal of the upper layer, in particular, the upper layer portion of the gate shorting line ( 150a) is formed to include a neck-shaped Mo-bridge 160 having a width of 3.5 to 4.5 µm and a length of several µm or less, as shown in K 'of FIG. 6 (an enlarged view of the K portion in plan view). .

In addition, the neck-shaped Mo-bridge 160 is formed such that the inclination angle of the inclined surface formed with the adjacent portions having different widths is between 70 degrees and 80 degrees, and the inclined angle of the inclined surface opposite thereto is formed between 100 degrees and 110 degrees.

Subsequently, etching is performed using an etchant capable of etching the lower Al metal to form a gate line including a gate electrode and the gate shorting line stacked in a chevron pattern.

In this case, in particular, the lower layer portion 170b of the gate shorting line is etched so that Al metals are separated from each other, and the upper layer portion 150a of the gate shorting line forms a neck-shaped Mo-bridge 160 structure and the neck-shaped Mo- The lower Al metal of the bridge is formed as shown in 6b so as to have a shape spaced apart from several micrometers or less.

When configured in accordance with the present invention, the electrical flow through the neck-shaped Mo-bridge 160 is possible, and thus can act as a gate shorting line to prevent internal devices from being destroyed by static electricity, which may occur in the process described below. Will be.

The gate shorting line having the neck-shaped Mo-bridge described above may be equally applied to the data pad and the data shorting bar and the data shorting line in the same process as the gate electrode and the gate shorting line. It will be self-evident to you.

Then, a gate insulating film 175 such as silicon nitrate (SiNx) or silicon oxide (SiOx) is formed on the substrate on which the gate wiring is formed, and amorphous silicon (a-Si :) is formed on the gate insulating film 175 of the gate electrode portion. The semiconductor layer 180 made of H) and the ohmic contact layer 190 made of amorphous silicon (n + a-Si: H) doped with n + ions are successively stacked to form an island shape.

After removing the gate insulating film 175 deposited on the gate shorting line 150, a second Mo metal is deposited on the substrate, a positive photoresist is applied on the second Mo metal film, and then Position the exposure mask having the pattern of.

Subsequently, the photoresist is exposed and developed to form a photoresist pattern, and the second Mo metal below is etched along the pattern of the photoresist, thereby separating the source electrode 195 and the drain electrode 196, and simultaneously A second Mo metal and a neck-shaped Mo-bridge 160 are also etched on the upper layer of the gate shorting line formed of the same material as the drain electrode, and the gate shorting line 150 is electrically cut.

Thereafter, the ohmic contact layer 190 is etched by using the source and drain electrodes 195 and 196 as a mask, and the ohmic contact layer 190a and the ohmic contact layer 190a are spaced apart from each other at predetermined intervals. The ohmic contact layer 190b in contact with the drain electrode 196 is formed, and the photoresist pattern remaining on the metal film is removed to form the same as 6d.

Thereafter, a protective film made of a silicon nitrate (SiNx) film, a silicon oxide (SiOx) film, BCB (benzocyclobutene), or the like is deposited to cover the thin film transistor, and a photoresist is coated by spin coating on the protective film as shown in FIG. 6E. By exposing using a mask having a predetermined pattern, a photoresist film 220 having a portion 210 where a protective film of a portion of the drain electrode 196 of the thin film transistor is exposed is formed.

The substrate formed in the above-described structure is placed in an etching chamber, and the protective film of the exposed protective film portion 210 is etched and etched.

After removing the remaining photoresist film, an indium tin oxide (ITO) film is formed on the entire surface of the substrate and patterned into a predetermined shape to electrically connect the pixel electrode contacted through the drain electrode 196 and the drain electrode contact hole 230. By connecting to each other, the array panel of the liquid crystal display device is completed as shown in FIG.

A process of forming the neck-shaped M0-bridges included in the gate shorting line during the manufacturing process of the above-described array substrate, and a process of disconnecting the gate shorting line and the Mo-bridge of the neck formed by such a process, and a gate made of such a process. The shorting line applies equally to the data shorting line.

As described above, in forming the gate and the data shorting line to include a neck-shaped Mo-bridge formed thinner than other portions, the present invention has the following advantages.

First, in the neck-shaped Mo-bridge included in each shorting line, the inclination angle of the inclined surface connected to the adjacent portions of different widths is set between 70 degrees and 80 degrees, and the inclined angle of the inclined surfaces opposite thereto is 100 degrees to 110 degrees. The length of the neck-shaped Mo-bridge is set to several micrometers or less, and the distance between Al metals of the lower layer of the neck-shaped Mo-bridge of each shorting line is set to several micrometers or less. As the shear strength can be increased, it can withstand the physical impact applied in the subsequent process, thereby reducing the defect that the shorting line is disconnected at an undesired stage.

second. By setting the width of the neck-shaped Mo-bridge to 3.5 to 4.5 占 퐉, the second Mo metal and the Mo stacked on the Mo-bridge of the gate shorting line when the second Mo metal is separated into the source and drain electrodes. -The bridge can be easily cut to reduce the defects caused by conventional uncut.

While specific embodiments of the invention have been described and illustrated, it will be apparent that the invention may be embodied in various modifications by those skilled in the art.

Such modified embodiments should not be understood individually from the technical idea or the viewpoint of the present invention, and such modified embodiments should fall within the scope of the appended claims of the present invention.

Claims (4)

Providing a substrate; Stacking an Al metal and a first Mo metal into thin films on the substrate, respectively; Etching the stacked metal layers to form a gate line and a gate shorting line including a gate electrode in a chevron shape, Etching the first Mo metal of the upper portion of the gate shorting line to form a neck-shaped Mo-bridge having a width of 3.5 to 4.5 μm; Etching the Al metal below the neck-shaped Mo-bridge so as to be spaced apart; Depositing a gate insulating film on the substrate and forming a semiconductor layer and an ohmic contact layer; Removing the gate insulating film deposited on the gate shorting line; Stacking a second Mo metal film on the entire surface of the substrate from which the gate insulating film of the gate shorting line is removed; Etching the second Mo metal film to form a source electrode and a drain electrode, and removing the Mo-bridge and the second Mo metal film thereon; A method of manufacturing an array panel for a liquid crystal display device comprising depositing a second insulating film on a substrate provided with the source and drain electrodes. The method according to claim 1, The length of the neck-shaped Mo-bridge is several μm or less, The inclination angle of the inclined surface formed by the neck-shaped Mo-bridge and adjacent portions having different widths is between 70 degrees and 80 degrees, and the inclination angle of the inclined surfaces opposite thereto is 100 degrees to 110 degrees, A method of manufacturing an array panel for a liquid crystal display device, wherein a distance of the Al metal below the neck-shaped Mo-bridge is separated by several μm or less. A substrate; A gate line having an Al metal and a Mo metal film laminated on the substrate; Neck panel-shaped Mo-bridge having a width of 3.5 to 4.5㎛ on the gate shorting line connected to the gate line and an Al metal spaced apart from the lower portion of the Mo-bridge array panel for a liquid crystal display device The method according to claim 3, The length of the neck-shaped Mo-bridge is several μm or less, The inclination angle of the inclined surface formed by the neck-shaped Mo-bridge and the adjacent portion is between 70 degrees and 80 degrees, and the inclined angle of the inclined surface opposite thereto is 100 degrees to 110 degrees, An array panel for a liquid crystal display device including a gate shorting line having a distance of two μm or less spaced from both sides about the neck-shaped Mo-bridge.