KR20030057600A - Method for fabricating capacitor of DRAM - Google Patents

Abstract

PURPOSE: A method for manufacturing a DRAM capacitor is provided to simplify manufacturing processes, to increase capacitance and to prevent bridge between cells by using etch-back and wet-etching of an oxide layer for isolating cells. CONSTITUTION: An etch stop layer(33) and a capacitor oxide layer(35) are sequentially formed on a silicon substrate(31) having a plug. A storage node contact hole is formed to expose the plug. An amorphous silicon layer(36) and MPS(Metastable PolySilicon)(37) as a storage node are sequentially formed on the resultant structure including the storage node contact hole. Then, a cell isolation oxide layer(38) is filled into the storage node contact hole. After etch-back of the oxide layer(38), the MPS and the amorphous silicon layer deposited on the capacitor oxide layer(35) are removed by etch-back so as to isolate between storage nodes. The cell isolation oxide layer(38) filled in the storage node contact hole is then removed by wet-etching. At the time, USG(Undoped Silicate Glass) is used as the cell isolation oxide layer(38).

Description

Method for fabricating capacitor of DRAM

The present invention relates to a method of manufacturing a DRAM capacitor, in particular, by using an etch back and wet etching process of the oxide film to simplify the process, increase the capacity of the capacitor, reduce the generation of impurities particles, and prevent the generation of inter-cell bridges It is about a method.

An example of manufacturing a cup-shaped capacitor using only the inside of a conventional cylinder structure will be described with reference to FIGS. 1A to 1B.

First, as shown in FIG. 1A, an interlayer insulating film 12 is formed on a semiconductor substrate 11 on which a predetermined substructure is formed, and SiN is deposited as an etch stop layer 13. Subsequently, the etch stop layer 13 and the interlayer insulating layer 12 are etched to form a storage node contact hole (not shown) exposing a part of the surface of the semiconductor substrate 11.

Next, after forming the storage node contact 14 which is buried in the storage node contact hole and connected to the semiconductor substrate 11, a capacitor oxide film 15 for forming a capacitor is deposited on the etch stop layer 13. In this case, a polysilicon hard mask layer may be deposited on the capacitor oxide layer 15.

Next, the capacitor oxide layer 15 is first etched to open the region where the storage node is to be formed, and then the etch stop layer 13 is further etched.

Subsequently, the amorphous silicon 16 for forming the storage node is deposited on the entire surface of the resultant, and then the MPS 17 is grown on the surface of the amorphous silicon 16, and a photoresist 18 is coated on the entire surface.

As shown in FIG. 1B, the CMP process is performed until the surface of the capacitor oxide film 15 is exposed to separate the amorphous silicon layer 16 for each cell, and then the remaining photoresist film 18 is removed by wet etching. .

Alternatively, the photoresist film 18 is etched back and remains only in the region where the storage node is to be formed. In this state, the amorphous silicon 16 on which the MPS 17 on the capacitor oxide film 15 is grown is removed. After the tooth whitening, the photosensitive film 18 is stripped.

Next, the dielectric layer 19 and the upper electrode 20 are formed on the amorphous silicon layer 16 on which the MPS 17 is grown, that is, the storage node 16/17.

The above-described conventional technique has a disadvantage in that the separation of cells by etch back or CMP reduces the height of the storage node, thereby reducing the capacitor capacity, and there is a problem in that a peak occurs in the capacitor oxide film remaining after the etch back process.

In addition, it causes CMP non-uniformity caused by the oxide film, reduces the capacitor capacity by reducing the height of the cylinder, as well as the separation of MPS particles during the CMP process can generate an inter-cell bridge.

The present invention is to solve the above problems, using a etch back and wet etching process of the oxide film to simplify the process, increase the capacitor capacity, reduce the generation of impurity particles and prevent the formation of inter-cell bridges The purpose is to provide.

1A to 1B are cross-sectional views illustrating a method of manufacturing a DRAM capacitor according to the prior art;

2A through 2C are cross-sectional views illustrating a method of manufacturing a DRAM capacitor according to an exemplary embodiment of the present invention.

* Explanation of symbols for main parts of the drawings

31 semiconductor substrate 32 interlayer insulating film

33: etch stop layer 34: storage node contact

35 capacitor oxide film 36 amorphous silicon layer

37: MPS 38: USG

39 dielectric layer 40 upper electrode

According to an aspect of the present invention, there is provided a method of forming an interlayer insulating film, an etch stop layer, a capacitor oxide film, and a hard mask layer on a semiconductor substrate on which a predetermined substructure is formed, and to define a capacitor storage node forming region. Etching the hard mask layer and the capacitor oxide layer using a photomask, etching back the remaining hard mask layer and etching the etch stop layer, and excessively etching the interlayer insulating layer exposed by etching the etch stop layer. Forming a cylinder structure, depositing amorphous silicon and MPS in order to form a storage node on the entire surface of the cylinder structure formed as described above, depositing an oxide film for cell separation on the entire surface of the substrate, and depositing the oxide film for cell separation. MPS and amorphous silicon deposited on top of the capacitor oxide film, which is then exposed and thus exposed. And etching back the oxide film to the stage and for cell separation in the left to separate the storage nodes for each cell characterized in that configured to include a step of removing by wet etching.

DETAILED DESCRIPTION Hereinafter, exemplary embodiments of the present invention will be described with reference to the accompanying drawings so that those skilled in the art may easily implement the technical idea of the present invention. do.

2A to 2C illustrate a method of manufacturing a DRAM capacitor according to the present invention according to the process sequence.

First, as shown in FIG. 2A, an interlayer insulating film 32 is formed on a semiconductor substrate 31 on which a predetermined substructure is formed, and SiN is deposited as an etch stop layer 33. As shown in FIG. Subsequently, the etch stop layer 33 and the interlayer insulating layer 32 are etched to form a storage node contact hole (not shown) that exposes a portion of the surface of the semiconductor substrate 31.

Next, after forming the storage node contact 34 buried in the storage node contact hole and connected to the semiconductor substrate 31, a capacitor oxide layer 35 for forming a capacitor is deposited on the etch stop layer 33. In this case, the polysilicon hard mask layer may be deposited on the capacitor oxide film 35. This is because when the hard mask layer is deposited, it is difficult to etch the capacitor oxide film 35 using only the photoresist mask.

Next, the capacitor oxide layer 35 is first etched to open the region where the storage node is to be formed, and then the etch stop layer 33 is further etched. In this case, the interlayer insulating layer 32 under the etch stop layer 33 may be excessively etched to a predetermined thickness.

Subsequently, amorphous silicon 36 is deposited on the entire surface of the resultant to form a storage node, and then MPS 37 is grown on the surface of the amorphous silicon 36, and USG (Undoped Silicate Glass) 38 or spin on glass (SOG) is formed on the front surface. Deposit.

USG 38 is then etched back leaving only the region where the storage node is to be formed.

As shown in FIG. 2B, the amorphous silicon 36 is etched back using the etched USG 38 as a mask, leaving only the region where the storage node is to be formed. As a result, isolation between neighboring storage nodes is achieved. Hereinafter, the amorphous silicon 36 in which the MPS 37 is grown is abbreviated as a storage node 36/37.

On the other hand, during the etch back process, the etch target is set to reduce the height loss of the storage node 36/37 while ensuring separation between cells so that the height of the storage node 36/37 of the cylinder structure does not decrease.

As shown in FIG. 2C, the USG 38 remaining on the inner wall of the storage node 36/37 is wet-etched. At this time, the capacitor oxide layer 35 supporting the storage node 36/37 is partially etched to expose a portion of the upper sidewall of the storage node 36/37.

That is, the USG 38 inside the cylinder is completely removed and the capacitor oxide film 35 is half removed by using the difference in etching speed due to the film quality difference between the USG 38 and the capacitor oxide film 35. A storage node 36/37 having a cylinder structure is formed.

In the capacitor manufacturing process according to the present invention described above, due to the loss of the capacitor oxide film due to the difference in film quality between the USG film and the capacitor oxide film during etching of the USG film, it is possible to realize a half cylinder type capacitor, and to deposit MPS. After the storage node is separated by cells, inter-cell bridges due to movement of MPS particles can be prevented. In addition, the capacitor capacity can be sufficiently secured by using the secured sidewalls of the amorphous silicon layer.

Although the technical idea of the present invention has been described in detail according to the above preferred embodiment, it should be noted that the above-described embodiment is for the purpose of description and not of limitation. In addition, those skilled in the art will understand that various embodiments are possible within the scope of the technical idea of the present invention.

According to the present invention, after depositing the MPS, the oxide film is deposited, etched back to perform cell-to-cell separation, and the oxide film is wet-etched to reduce the generation of impurities due to the separation of the MPS particles, thereby preventing the formation of the inter-cell bridge. In addition, it is possible to implement a half-cylinder structure by using the difference in the etching rate due to the film quality difference, it is possible to obtain the capacitor capacity increase effect. In addition, wet etching after the etch back process of the oxide layer may secure sufficient space between adjacent capacitors, which may also contribute to preventing inter-cell bridges.

Claims (5)

Sequentially forming an interlayer insulating film, an etch stop layer, a capacitor oxide film, and a hard mask layer on a semiconductor substrate on which a predetermined substructure is formed; Etching the hard mask layer and the capacitor oxide layer using a photomask for defining a capacitor storage node formation region, Etching back the remaining hard mask layer and etching the etch stop layer, Forming a cylinder structure by over-etching the interlayer insulating layer exposed by etching the etch stop layer; Depositing amorphous silicon and MPS in order to form a storage node on the front surface of the formed cylinder structure; Depositing an oxide film for cell separation on the entire surface of the substrate; Etching back the cell separation oxide film, and etching back MPS and amorphous silicon deposited on the exposed capacitor oxide film to separate storage nodes for each cell, and And removing the remaining cell separation oxide film by wet etching. The method of claim 1, Capacitor manufacturing method characterized in that using USG or SOG as the oxide film for cell separation. The method of claim 1, In the step of removing the cell separation oxide film by wet etching, the cell separation oxide film remaining inside the cylinder is completely removed by using the difference in the etching rate due to the film quality difference between the cell separation oxide film and the capacitor oxide film. Capacitor manufacturing method characterized in that the wet etching to remove only the degree. The method of claim 1, After the step of forming the cylinder structure by the wet etching process further comprising the step of expanding the inner cylinder area. The method of claim 1, The method of manufacturing a capacitor according to claim 1, wherein the separation between the cells during the etch back process of the oxide film for separation of the cells is performed while the etch back is set to minimize the loss of the storage node height.