KR100250736B1 - Method for fabricating a storage node of capacitor - Google Patents

Method for fabricating a storage node of capacitor Download PDF

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Publication number
KR100250736B1
KR100250736B1 KR1019930029774A KR930029774A KR100250736B1 KR 100250736 B1 KR100250736 B1 KR 100250736B1 KR 1019930029774 A KR1019930029774 A KR 1019930029774A KR 930029774 A KR930029774 A KR 930029774A KR 100250736 B1 KR100250736 B1 KR 100250736B1
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South Korea
Prior art keywords
polysilicon
charge storage
sacrificial oxide
storage electrode
oxide film
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KR1019930029774A
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Korean (ko)
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KR950021621A (en
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김대영
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김영환
현대전자산업주식회사
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L28/00—Passive two-terminal components without a potential-jump or surface barrier for integrated circuits; Details thereof; Multistep manufacturing processes therefor
    • H01L28/40—Capacitors
    • H01L28/60—Electrodes
    • H01L28/82—Electrodes with an enlarged surface, e.g. formed by texturisation
    • H01L28/84—Electrodes with an enlarged surface, e.g. formed by texturisation being a rough surface, e.g. using hemispherical grains
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L28/00—Passive two-terminal components without a potential-jump or surface barrier for integrated circuits; Details thereof; Multistep manufacturing processes therefor
    • H01L28/40—Capacitors
    • H01L28/60—Electrodes
    • H01L28/75—Electrodes comprising two or more layers, e.g. comprising a barrier layer and a metal layer
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L28/00—Passive two-terminal components without a potential-jump or surface barrier for integrated circuits; Details thereof; Multistep manufacturing processes therefor
    • H01L28/40—Capacitors
    • H01L28/60—Electrodes
    • H01L28/82—Electrodes with an enlarged surface, e.g. formed by texturisation
    • H01L28/90—Electrodes with an enlarged surface, e.g. formed by texturisation having vertical extensions
    • H01L28/91—Electrodes with an enlarged surface, e.g. formed by texturisation having vertical extensions made by depositing layers, e.g. by depositing alternating conductive and insulating layers

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  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Semiconductor Integrated Circuits (AREA)
  • Semiconductor Memories (AREA)

Abstract

PURPOSE: A method for forming a charge storage electrode of a capacitor is provided to increase an available surface area of a charge storage electrode by using a hemispherical polysilicon. CONSTITUTION: An insulating layer(2) is formed on a semiconductor substrate(1). A multitude of contact hole is formed by suing a contact mask. The first polysilicon(4) is deposited. The first sacrificial oxide layer is deposited on the first polysilicon(4). A multitude of charge storage electrode portion is formed by etching the first sacrificial oxide layer and the first polysilicon(4). The second polysilicon(6) is deposited on an upper portion of the whole structure. A spacer is formed at sidewalls of the first polysilicon(4) and the first sacrificial oxide layer. The first sacrificial oxide layer is removed from an inside of the second polysilicon(6). A hemispherical polysilicon(7) is deposited on the whole face of the structure. The second sacrificial oxide layer is deposited on the upper portion of the whole structure. The hemispherical polysilicon(7) is exposed by etching the second sacrificial oxide layer. The exposed hemispherical polysilicon(7) is removed by using the second sacrificial oxide layer as an etching barrier. A charge storage electrode is formed by etching the remaining second sacrificial oxide layer.

Description

캐패시터의 전하저장전극 형성방법Method of forming charge storage electrode of capacitor

제1a도 내지 제1f도는 본 발명에 의한 캐패시터의 전하저장전극을 형성하는 단계를 도시한 단면도.1A to 1F are cross-sectional views showing steps of forming a charge storage electrode of a capacitor according to the present invention.

* 도면의 주요부분에 대한 부호의 설명* Explanation of symbols for main parts of the drawings

1 : 반도체 기판 2 : 절연막1 semiconductor substrate 2 insulating film

3 : 콘택홀 4 : 제1폴리실리콘3: contact hole 4: first polysilicon

5 : 제1희생 산화막 6 : 제2폴리실리콘5: first sacrificial oxide film 6: second polysilicon

7 : 반구형 폴리실리콘 8 : 제2희생 산화막7: hemispherical polysilicon 8: second sacrificial oxide film

본 발명은 캐패시터의 전하저장전극을 형성하는 방법에 관한 것으로, 특히 측벽이 스페이서 구조를 갖는 실린더형(Cylinder Type) 전하저장전극을 반구형 폴리실리콘을 이용하여 유효표면적을 증대시키고자 할때, 형성되는 반구형 폴리실리콘을 최대한 이용하여 전하저장전극의 유효표면적을 증대시킬 수 있는 캐패시터의 전하저장전극을 형성하는 방법에 관한 것이다.The present invention relates to a method of forming a charge storage electrode of a capacitor, in particular, when a cylindrical type charge storage electrode having a spacer structure with sidewalls is formed using hemispherical polysilicon to increase the effective surface area. The present invention relates to a method of forming a charge storage electrode of a capacitor capable of increasing the effective surface area of the charge storage electrode by utilizing the hemispherical polysilicon to the maximum.

일반적으로, 반도체 소자가 고집적화 되어감에 따라 셀 면적은 급격하게 축소되고, 셀 면적의 축소에도 불구하고 소자의 동작에 필요한 셀당 일정용량 이상의 캐패시터 용량을 확보해야 한다.In general, as semiconductor devices are highly integrated, the cell area is drastically reduced, and despite the reduction in cell area, it is necessary to secure a capacitor capacity more than a predetermined capacity per cell required for the operation of the device.

이를 해결하기 위하여 여러가지 3차원의 전하저장전극이 제시되고 있으며, 보다 유용한 구조를 제조하기 위해 계속 연구되고 있다.In order to solve this problem, various three-dimensional charge storage electrodes have been proposed, and are being studied to manufacture more useful structures.

따라서 본 발명은 반도체 소자의 고집적화에 적합하도록 제한된 면적하에서 유효표면적을 극대화할 수 있는 캐패시터의 전하저장전극 형성방법을 제공함에 그 목적이 있다.Accordingly, an object of the present invention is to provide a method for forming a charge storage electrode of a capacitor capable of maximizing an effective surface area under a limited area to be suitable for high integration of semiconductor devices.

이러한 목적을 달성하기 위한 본 발명은 스페이서 구조를 갖는 실린더형 전하저장전극이 다수 형성된 웨이퍼 전면에 반구형 폴리실리콘을 증착한 후, 전체구조 상부에 단차 피복성(Step Coverage)이 안좋은 물질을 증착하여 단차피복성이 나쁘기 때문에 폭이 좁은 부분 즉 이웃하는 전하저장전극 사이에는 두께가 얇아 증착된 물질을 1차로 식각하여 전하저장전극간의 반구형 폴리실리콘을 노출시키고, 노출된 반구형 폴리실리콘을 식각하여 이웃하는 전하저장전극간을 분리시키고, 상기 1차로 식각되고 남은 물질을 2차로 식각하여 전하저장전극 표면에 반구형 폴리실리콘이 그대로 남아있게 하여 전하저장전극의 유효표면적을 증대시키는 것을 특징으로 한다.In order to achieve the above object, the present invention deposits hemispherical polysilicon on the entire surface of a wafer on which a plurality of cylindrical charge storage electrodes having a spacer structure are formed, and then deposits a material having poor step coverage on the entire structure. Due to the poor coverage, a thin layer is formed between the narrow portions, that is, adjacent charge storage electrodes, so that the deposited material is first etched to expose the hemispherical polysilicon between the charge storage electrodes, and the exposed hemispherical polysilicon is etched to expose the adjacent charge. Separating between the storage electrodes and secondly etching the remaining material after the primary etching, hemispherical polysilicon remains on the surface of the charge storage electrode, thereby increasing the effective surface area of the charge storage electrode.

이하, 본 발명을 첨부된 도면을 참조하여 상세히 설명하기로 한다.Hereinafter, the present invention will be described in detail with reference to the accompanying drawings.

제1a도 내지 제1f도는 본 발명에 의한 캐패시터의 전하저장전극을 형성하는 단계를 도시한 단면도로서, 제1a도는 트랜지스터 및 비트라인등이 구성된 반도체 기판(1)위에 층간을 절연하는 절연막(2)을 일정두께로 증착한 다음, 전하저장전극용 콘택 마스크로 다수의 콘택홀(3)을 형성하고, 상기 콘택홀(3)을 통해 반도체 기판(1)의 소정부위와 접속되도록 전하저장전극용 제1폴리실리콘(4)을 증착한 후, 상기 제1폴리실리콘(4) 상부에 제1희생 산화막(5)을 두껍게 증착한 상태를 도시한 것이다.1A to 1F are cross-sectional views illustrating a step of forming a charge storage electrode of a capacitor according to the present invention. FIG. 1A is an insulating film 2 for insulating an interlayer on a semiconductor substrate 1 including transistors, bit lines, and the like. Is deposited to a predetermined thickness, and then a plurality of contact holes 3 are formed with a contact mask for charge storage electrode, and the charge storage electrode is made to be connected to a predetermined portion of the semiconductor substrate 1 through the contact hole 3. After depositing one polysilicon 4, the first sacrificial oxide film 5 is thickly deposited on the first polysilicon 4.

제1b도는 전하저장전극용 마스크를 사용한 식각공정으로 상기 제1희생 산화막(5) 및 제1폴리실리콘(4)을 식각하여 다수의 전하저장전극 부분을 설정한 상태를 도시한 것이다.FIG. 1B illustrates a state in which a plurality of charge storage electrode portions are set by etching the first sacrificial oxide film 5 and the first polysilicon 4 by an etching process using a charge storage electrode mask.

제1c도는 상기 전체구조 상부에 전하저장전극용 제2폴리실리콘(6)을 증착한 후, 상기 제2폴리실리콘(6)을 스페이서 식각공정에 의해 상기 설정된 제1폴리실리콘(4) 및 제1희생 산화막(5) 측벽에 스페이서를 형성하고, 이후 건식 또는 습식식각으로 패턴화된 제1폴리실리콘(4)과 스페이서로된 제2폴리실리콘(6) 내부에 남아있는 제1희생 산화막(5)을 완전히 제거한 상태를 도시한 것이다.FIG. 1C shows the first polysilicon 4 and the first polysilicon 6 deposited on the entire structure after depositing the second polysilicon 6 for the charge storage electrode, and then etching the second polysilicon 6 by a spacer etching process. The first sacrificial oxide film 5 is formed on the sidewalls of the sacrificial oxide film 5, and then remains inside the second polysilicon 6 including the first polysilicon 4 and the spacer patterned by dry or wet etching. It shows the state completely removed.

제1d도는 상기 제1 및 2폴리실리콘(4 및 6)으로 스페이서 구조를 갖는 실린더형 전하저장전극이 다수 형성된 웨이퍼 전면에 반구형 폴리실리콘(7)을 증착한 후, 전체구조 상부에 단차 피복성이 나쁜 제2희생 산화막(8)을 증착한 상태를 도시한 것이다.FIG. 1D is a diagram showing the step coverage of the hemispherical polysilicon 7 on the entire surface of the wafer on which a plurality of cylindrical charge storage electrodes having a spacer structure are formed of the first and second polysilicon 4 and 6. The state in which the bad second sacrificial oxide film 8 is deposited is shown.

상기 제2희생 산화막(8)은 예를들어, 플라즈마 질화물, 플라즈마 산화막등으로 이루어진다.The second sacrificial oxide film 8 is made of, for example, a plasma nitride, a plasma oxide film, or the like.

상기에서 웨이퍼 전면에 반구형 폴리실리콘(7)을 증착함에 의해 이웃하는 전하저장전극이 전기적으로 접속되어 이들 이웃하는 전하저장전극간을 분리시켜야 하는데, 종래에는 상기 반구형 폴리실리콘(7)이 증착된 상태에서 직접 반구형 폴리실리콘(7)을 식각하는 방법으로 이웃하는 전하저장전극간을 분리시킴에 의해 유효표면적을 늘리고자 증착된 전하저장전극상의 반구형 폴리실리콘(7)이 심하게 손상당하는 문제가 발생하였다.In the above, by depositing the hemispherical polysilicon 7 on the entire surface of the wafer, neighboring charge storage electrodes are electrically connected to separate the neighboring charge storage electrodes. In the conventional state, the hemispherical polysilicon 7 is deposited. In order to increase the effective surface area by separating the adjacent charge storage electrodes by etching the hemispherical polysilicon (7) directly at, the hemispherical polysilicon (7) on the deposited charge storage electrode is severely damaged.

따라서, 본 발명에서는 전하저장전극상의 반구형 폴리실리콘(7)을 보호하기 위하여 단차 피복성이 나쁜 희생 산화막(8)을 전체적으로 증착하는데, 이 희생산화막(8)은 단차피복성이 나빠 폭이 좁은 부분 즉 이웃하는 전하저장전극 사이에는 증착되는 두께가 매우 얇게된다.Therefore, in the present invention, in order to protect the hemispherical polysilicon 7 on the charge storage electrode, the sacrificial oxide film 8 having poor step coverage is entirely deposited. The sacrificial oxide film 8 has a narrow step portion having poor step coverage. That is, the thickness deposited between adjacent charge storage electrodes becomes very thin.

제1e도는 상기 제2희생 산화막(8)을 1차로 전면 식각하여 두께가 얇게 증착된 부분을 제거하여 반구형 폴리실리콘(7)을 노출시킨 상태를 도시한 것이다.FIG. 1E illustrates a state in which the hemispherical polysilicon 7 is exposed by first etching the second sacrificial oxide film 8 to remove the thinly deposited portion.

제1f도는 상기 1차 식각공정에서 남은 제2희생 산화막(8)을 식각장벽층으로 하여 노출된 반구형 폴리실리콘(7)을 제거하여 이웃하는 전하저장전극을 분리시킨 다음, 상기 남아있는 제2희생산화막(8)을 2차로 식각하여 완전히 제거하므로써 최초 증착된 반구형 폴리실리콘(7)이 그대로 전하저장전극 표면에 남아있게 되어 유효표면적이 증대된 전하저장전극을 형성한 상태를 도시한 것이다.FIG. 1f illustrates the remaining second sacrificial sacrificial polysilicon 7 by removing the exposed hemispherical polysilicon 7 using the second sacrificial oxide film 8 remaining in the first etching process as an etch barrier layer. FIG. 2 shows a state in which the hemispherical polysilicon 7 deposited as a result of completely etching and removing the oxide film 8 remains on the surface of the charge storage electrode to form a charge storage electrode having an increased effective surface area.

이후, 유전체막 및 플레이트 전극을 형성하여 캐패시터를 구성한다.After that, a dielectric film and a plate electrode are formed to form a capacitor.

상술한 바에 의거한 본 발명은 셀과 셀간의 격리를 단순한 공정을 통해 이룰 수 있고 전하저장전극의 유효표면적을 증대시키기 위해 증착한 반구형 폴리실리콘의 손상도 방지할 수 있다.According to the present invention as described above, the isolation between the cells can be achieved through a simple process, and the damage of the hemispherical polysilicon deposited to increase the effective surface area of the charge storage electrode can be prevented.

Claims (2)

유효표면적을 증대시키기 위한 캐패시터의 전하저장전극 형성방법에 있어서, 트랜지스터 및 비트라인등이 구성된 반도체 기판(1)위에 층간을 절연하는 절연막(2)을 일정두께로 증착한 다음, 전하저장전극용 콘택 마스크로 다수의 콘택홀(3)을 형성하고, 상기 콘택홀(3)을 통해 반도체 기판(1)의 소정부위와 접속되도록 전하저장전극용 제1폴리실리콘(4)을 증착한 후, 상기 제1폴리실리콘(4) 상부에 제1희생 산화막(5)을 두껍게 증착하는 단계와, 상기 단계로부터 전하저장전극용 마스크를 사용한 식각공정으로 상기 제1희생 산화막(5) 및 제1폴리실리콘(4)을 식각하여 다수의 전하저장전극 부분을 설정하는 단계와, 상기 단계로부터 전체구조 상부에 전하저장전극용 제2폴리실리콘(6)을 증착한 후, 상기 제2폴리실리콘(6)을 스페이서 식각공정에 의해 상기 설정된 제1폴리실리콘(4) 및 제1희생 산화막(5) 측벽에 스페이서를 형성하고, 이후 건식 또는 습식식각으로 패턴화된 제1폴리실리콘(4)과 스페이서로된 제2폴리실리콘(6) 내부에 남아있는 제1희생 산화막(5)을 완전히 제거하는 단계와, 상기 단계로부터 상기 제1 및 2폴리실리콘(4 및 6)으로 스페이서 구조를 갖는 실린더형 전하저장전극이 다수 형성된 웨이퍼 전면에 반구형 폴리실리콘(7)을 증착한 후, 전체구조 상부에 단차 피복성이 나쁜 제2희생 산화막(8)을 증착하는 단계와, 상기 단계로부터 제2희생 산화막(8)을 1차로 전면식각하여 두께가 얇게 증착된 부분을 제거하여 반구형 폴리실리콘(7)을 노출시키는 단계와, 상기 단계로부터 상기 1차 식각공정에서 남은 제2희생 산화막(8)을 식각장벽층으로 하여 노출된 반구형 폴리실리콘(7)을 제거하여 이웃하는 전하저장전극간을 분리시킨 다음, 상기 남아있는 제2희생 산화막(8)을 2차로 식각하여 완전히 제거하여 반구형 폴리실리콘(7)이 그대로 제1 및 제2폴리실리콘(4 및 6)으로 된 전하저장전극 표면에 남아있게 되어 유효표면적이 증대된 전하저장전극을 완성하는 단계로 이루어 지는 것을 특징으로 하는 캐패시터 전하저장전극 형성방법.In the method for forming a charge storage electrode of a capacitor for increasing the effective surface area, an insulating film (2) for insulating an interlayer is deposited on a semiconductor substrate (1) including transistors, bit lines, and the like to a predetermined thickness, and then contact for a charge storage electrode is formed. After forming a plurality of contact holes (3) with a mask, and depositing the first polysilicon (4) for the charge storage electrode to be connected to a predetermined portion of the semiconductor substrate 1 through the contact holes (3), The first sacrificial oxide film 5 and the first polysilicon 4 are deposited by thickly depositing the first sacrificial oxide film 5 on the polysilicon 4 and by etching using the mask for the charge storage electrode. Etching) to set a plurality of charge storage electrode portions, and depositing the second polysilicon 6 for the charge storage electrode on the entire structure from the step, and then etching the second polysilicon 6 into the spacer. Set above by process Spacers are formed on sidewalls of the first polysilicon 4 and the first sacrificial oxide film 5, and then inside the second polysilicon 6 including spacers and the first polysilicon 4 patterned by dry or wet etching. Completely removing the first sacrificial oxide film 5 remaining in the substrate; and from the step, the hemispherical poly on the front surface of the wafer in which a plurality of cylindrical charge storage electrodes having a spacer structure are formed as the first and second polysilicons 4 and 6 After the deposition of the silicon 7, the second sacrificial oxide film 8 having poor step coverage is deposited on the entire structure, and the second sacrificial oxide film 8 is firstly etched from the above step so that the thickness is thin. Exposing the hemispherical polysilicon 7 by removing the deposited portion, and exposing the hemispherical polysilicon 7 exposed from the step by using the second sacrificial oxide film 8 remaining in the first etching process as an etching barrier layer. Remove neighboring charges After the separation between the electrodes, the remaining second sacrificial oxide film 8 was secondly etched and completely removed so that the hemispherical polysilicon 7 was made of the first and second polysilicon 4 and 6 as it was. A method of forming a capacitor charge storage electrode, characterized in that it is made to remain on the surface to complete the charge storage electrode having an increased effective surface area. 제1항에 있어서, 상기 제2희생 산화막(8)은 플라즈마 질화물, 플라즈마 산화물로 이루어지는 것을 특징으로 하는 캐패시터 전하저장전극 형성방법.The method of claim 1, wherein the second sacrificial oxide film (8) is made of plasma nitride or plasma oxide.
KR1019930029774A 1993-12-27 1993-12-27 Method for fabricating a storage node of capacitor KR100250736B1 (en)

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Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100563735B1 (en) * 1999-03-29 2006-03-28 주식회사 하이닉스반도체 Method of forming a storage node in a semiconductor device
KR100587046B1 (en) * 2000-05-31 2006-06-07 주식회사 하이닉스반도체 Method of manufacturing stroage electrode

Families Citing this family (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100224710B1 (en) * 1995-10-10 1999-10-15 윤종용 Method for manufacturing of capacitor in semiconductor device
KR100333129B1 (en) * 1998-12-24 2002-09-26 주식회사 하이닉스반도체 Capacitor Formation Method of Semiconductor Device

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100563735B1 (en) * 1999-03-29 2006-03-28 주식회사 하이닉스반도체 Method of forming a storage node in a semiconductor device
KR100587046B1 (en) * 2000-05-31 2006-06-07 주식회사 하이닉스반도체 Method of manufacturing stroage electrode

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