KR20030055401A - Forming method of semiconductor device - Google Patents
Forming method of semiconductor device Download PDFInfo
- Publication number
- KR20030055401A KR20030055401A KR1020010084914A KR20010084914A KR20030055401A KR 20030055401 A KR20030055401 A KR 20030055401A KR 1020010084914 A KR1020010084914 A KR 1020010084914A KR 20010084914 A KR20010084914 A KR 20010084914A KR 20030055401 A KR20030055401 A KR 20030055401A
- Authority
- KR
- South Korea
- Prior art keywords
- forming
- semiconductor device
- metal wiring
- contact
- contact plug
- Prior art date
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76897—Formation of self-aligned vias or contact plugs, i.e. involving a lithographically uncritical step
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02107—Forming insulating materials on a substrate
- H01L21/02109—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates
- H01L21/02112—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer
- H01L21/02123—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon
- H01L21/02126—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon the material containing Si, O, and at least one of H, N, C, F, or other non-metal elements, e.g. SiOC, SiOC:H or SiONC
- H01L21/02129—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon the material containing Si, O, and at least one of H, N, C, F, or other non-metal elements, e.g. SiOC, SiOC:H or SiONC the material being boron or phosphorus doped silicon oxides, e.g. BPSG, BSG or PSG
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
- H01L21/76802—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics
- H01L21/76814—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics post-treatment or after-treatment, e.g. cleaning or removal of oxides on underlying conductors
Abstract
Description
본 발명은 반도체 소자의 형성방법에 관한 것으로, 보다 상세하게는 반도체소자의 금속 배선 형성과정 중 콘택홀이 형성된 산화막을 리플로우시켜 콘택홀의 상부를 라운드화 한 다음 콘택 플러그를 형성하는 공정을 포함함으로써 콘택 플러그와 금속 배선 사이의 중첩 여유도 (overlap margin)를 확보할 수 있는 반도체 소자의 형성방법에 관한 것이다.The present invention relates to a method of forming a semiconductor device, and more particularly, by including reflowing an oxide film in which a contact hole is formed during a metal wiring formation process of a semiconductor device to round the top of the contact hole, and then forming a contact plug. The present invention relates to a method of forming a semiconductor device capable of securing an overlap margin between a contact plug and a metal wiring.
최근의 반도체 장치의 고집적화 추세는 미세 패턴 형성 기술의 발전에 큰 영향을 받고 있는데, 미세 패턴 형성시 선폭 (Critical Dimension; CD)이 감소함에 따라 중첩 여유도 (overlap margin)를 확보하는 문제가 대두되고 있는 실정이다.The recent trend toward higher integration of semiconductor devices has been greatly influenced by the development of fine pattern forming technology. As the critical dimension (CD) decreases in forming fine patterns, there is a problem of securing an overlap margin. There is a situation.
이하, 첨부된 도면을 참고로 하여 종래기술을 상세히 설명한다.Hereinafter, with reference to the accompanying drawings will be described in detail the prior art.
도 1a 내지 도 1f 는 종래기술에 따른 반도체 소자의 형성방법을 도시한 단면도이다.1A to 1F are cross-sectional views illustrating a method of forming a semiconductor device according to the prior art.
먼저, 반도체 기판 상부에 형성된 하부 도전층(10) 상부에 금속 배선 콘택홀(11)이 구비된 층간 절연막(12)을 형성한 다음 (도 1a 참조), 상기 콘택홀(11) 매립하는 텅스텐층(14)을 도포한 다음 (도 1b 참조) 화학적 기계적 연마공정으로 평탄화시켜 금속 배선 콘택 플러그(15)를 형성한다 (도 1c 참조).First, an interlayer insulating layer 12 having a metal wiring contact hole 11 is formed on the lower conductive layer 10 formed on the semiconductor substrate (see FIG. 1A), and then a tungsten layer embedded in the contact hole 11 is formed. (14) is applied (see FIG. 1B) and then planarized by a chemical mechanical polishing process to form a metal wiring contact plug 15 (see FIG. 1C).
다음, 금속 배선 형성용 금속층(16)을 스퍼터링 방법으로 형성하고, 그 상부에 감광막을 도포한 다음 금속 배선 형성용 감광막 패턴(17)을 형성한다 (도 1d 및 도 1e 참조).Next, the metal layer 16 for metal wiring formation is formed by the sputtering method, the photosensitive film is apply | coated on the upper part, and the metal film formation photosensitive film pattern 17 is formed (refer FIG. 1D and FIG. 1E).
그리고, 상기 감광막 패턴(17)을 식각 마스크로 금속층(16)을 식각하여 금속 배선(18)을 형성한다 (도 1f 참조).The metal layer 16 is etched using the photoresist pattern 17 as an etch mask to form a metal wiring 18 (see FIG. 1F).
상기와 같은 종래의 방법에서는 콘택 플러그와 금속 배선 사이의 패턴 중첩도가 작게 되고, 이에 따라 콘택 저항이 커지는 등의 문제가 발생한다. 또한 패턴 크기가 감소할수록 공정 여유도가 작아져 생산 수율 및 반도체 특성에 악영향을 미치게 된다.In the conventional method as described above, there is a problem that the pattern overlap between the contact plug and the metal wiring becomes small, thereby increasing the contact resistance. In addition, as the pattern size decreases, process margin becomes smaller, which adversely affects production yield and semiconductor characteristics.
상기와 같은 문제점을 해결하기 위하여 본 발명에서는 콘택 플러그와 금속 배선 사이의 중첩 여유도를 확보할 수 있는 방법을 제공하는 것을 목적으로 한다.In order to solve the above problems, an object of the present invention is to provide a method that can ensure the overlap margin between the contact plug and the metal wiring.
도 1a 내지 도 1f 는 종래 기술에 따른 반도체 소자의 형성방법을 도시한 단면도.1A to 1F are cross-sectional views showing a method of forming a semiconductor device according to the prior art.
도 2a 내지 도 2g 는 본 발명의 실시예에 따른 반도체 소자의 형성방법을 도시한 단면도.2A to 2G are cross-sectional views illustrating a method of forming a semiconductor device in accordance with an embodiment of the present invention.
도 3은 산화막을 플루우시켜 얻어진 패턴 프로파일 사진.3 is a pattern profile picture obtained by flushing an oxide film.
< 도면의 주요부분에 대한 부호의 설명 ><Description of Symbols for Major Parts of Drawings>
100 : 하부 도전층112 : 층간 절연막100: lower conductive layer 112: interlayer insulating film
111 : 콘택홀113 : 리플로우된 층간 절연막111 contact hole 113 reflowed interlayer insulating film
114 : 텅스텐 층116 : 금속층114: tungsten layer 116: metal layer
117 : 감광막 패턴118 : 금속 배선117 photosensitive film pattern 118 metal wiring
상기 목적을 달성하기 위하여 본 발명에서는 반도체 소자의 금속 배선 형성과정 중 콘택홀이 형성된 산화막을 리플로우시켜 콘택홀의 상부를 라운드화 한 다음 콘택 플러그를 형성하는 공정을 포함하는 반도체 소자의 형성방법을 제공한다.In order to achieve the above object, the present invention provides a method of forming a semiconductor device, which includes forming a contact plug by rounding an upper portion of a contact hole by reflowing an oxide film in which a contact hole is formed during a metal wiring formation process of the semiconductor device. do.
본 발명의 반도체 소자 형성방법은The semiconductor device forming method of the present invention
(a) 반도체 기판 상부에 하부 도전층을 형성하는 단계(a) forming a lower conductive layer on the semiconductor substrate
(b) 상기 하부 도전층의 일측을 노출시키는 콘택홀이 구비된 층간 절연막을 형성하는 단계;(b) forming an interlayer insulating film having a contact hole exposing one side of the lower conductive layer;
(c) 상기 층간 절연막을 열처리하여 플로우 (thermal flow)시켜 콘택홀 상부를 라운드화 하는 단계;(c) rounding an upper portion of the contact hole by thermally treating the interlayer insulating film;
(d) 상기 구조의 콘택홀을 매립하는 금속 배선 콘택 플러그를 형성하는 단계;(d) forming a metallization contact plug to fill the contact hole of the structure;
(e) 상기 콘택 플러그에 접속되는 금속 배선을 형성하는 단계를 포함한다.(e) forming a metal wire connected to the contact plug.
이하, 첨부된 도면을 참고로 하여 본 발명을 상세히 설명한다.Hereinafter, the present invention will be described in detail with reference to the accompanying drawings.
도 2a 내지 도 2g 는 본 발명에 의한 반도체 소자의 형성방법을 도시한 단면도이다.2A to 2G are cross-sectional views showing a method of forming a semiconductor device according to the present invention.
먼저, 반도체 기판 상부에 하부 도전층(110)을 형성하고, 그 상부에 금속 배선 콘택홀(111)이 구비된 층간 절연막(112)을 형성한 다음 (도 2a 참조), 여기에 열처리를 수행하여 상기 층간 절연막(112)인 산화막을 리플로우시켜 상부가 둥글게 된 산화막 패턴(113)을 형성한다 (도 2b 참조). 이러한 플로우에 의하여 콘택 플러그와 금속 배선의 접촉 면적을 넓힘으로써 콘택 플러그층과 금속 배선층간의 중첩 여유도를 확보할 수 있게 되는데, 열처리의 온도에 따라, 또는 층간 절연막(112)으로 사용되는 BPSG (boron-doped phosphosilicate glass)의 B 또는 P의 농도에 따라 상기 접촉 면적을 조절함으로써 적절한 콘택 크기 및 프로필을 얻을 수 있다. 바람직한 열처리 온도는 700∼900℃ 이고, BPSG의 B 또는 P의 농도는 3.0∼6.0중량%의 범위 내에서 조절하는 것이 바람직하다.First, a lower conductive layer 110 is formed on a semiconductor substrate, an interlayer insulating layer 112 having a metal wiring contact hole 111 is formed thereon (see FIG. 2A), and then heat treatment is performed thereon. The oxide film that is the interlayer insulating film 112 is reflowed to form an oxide film pattern 113 having a rounded upper portion (see FIG. 2B). By this flow, the contact area between the contact plug and the metal wiring can be increased to secure an overlapping margin between the contact plug layer and the metal wiring layer. Appropriate contact size and profile can be obtained by adjusting the contact area according to the concentration of B or P of -doped phosphosilicate glass. Preferable heat processing temperature is 700-900 degreeC, and it is preferable to adjust the density | concentration of B or P of BPSG within 3.0 to 6.0 weight%.
그런 다음, 상기 산화막 패턴(113)을 매립하는 텅스텐층(114)을 도포한 다음 (도 2c 참조) 화학적 기계적 연마공정으로 평탄화시켜 금속 배선 콘택 플러그(115)를 형성한다 (도 2d 참조).Then, the tungsten layer 114 filling the oxide layer pattern 113 is coated (see FIG. 2C), and then planarized by a chemical mechanical polishing process to form a metal interconnection contact plug 115 (see FIG. 2D).
다음, Al 또는 Al/Cu 합금과 같은 금속 배선 형성용 금속층(116)을 스퍼터링 방법으로 형성하고, 그 상부에 감광막을 도포한 다음 금속 배선 형성용 감광막 패턴(117)을 형성한다 (도 2e 및 도 2f 참조).Next, a metal layer for forming metal wiring 116 such as Al or Al / Cu alloy is formed by a sputtering method, a photosensitive film is coated on the upper portion thereof, and then a photosensitive film pattern 117 for metal wiring forming is formed (FIGS. 2f).
그리고, 상기 감광막 패턴(117)을 식각 마스크로 금속층(116)을 식각하여 금속 배선(118)을 형성한다 (도 2g 참조). 여기서, 금속 배선 식각후 최종 패턴을 종래 기술과 비교하여 살펴보면, 종래 기술의 경우에는 상기 두 층간의 중첩된 정도가 약간만 어긋나 있어도 텅스텐 (콘택 플러그)과 알루미늄 (금속 배선) 사이의접촉이 제대로 이루어지지 않지만 본 발명의 경우 금속 배선 층과 콘택 플러그 층의 중첩된 정도가 어느 정도 어긋나 있어도 충분한 중첩 여유도를 확보할 수 있음을 알 수 있다 (도 2g의 b 〉도 1f의 a).The metal layer 116 is etched using the photoresist pattern 117 as an etch mask to form a metal wiring 118 (see FIG. 2G). Here, the final pattern after etching the metal wiring is compared with the prior art. In the prior art, even if the overlapping degree between the two layers is slightly shifted, the contact between the tungsten (contact plug) and the aluminum (metal wiring) is not properly made. However, in the case of the present invention, even if the overlapping degree of the metal wiring layer and the contact plug layer is deviated to some extent, it can be seen that sufficient overlap margin can be secured (b in FIG. 2G> a in FIG. 1F).
이상에서 살펴본 바와 같이, 본 발명에서는 산화막 패턴을 리플로우시켜서, 이후에 형성될 텅스텐 플러그와 금속 배선간의 접촉 면적을 넓힘으로써 저항을 감소시킬 수 있을 뿐만 아니라 충분한 중첩 여유도를 확보할 수 있다.As described above, in the present invention, by reflowing the oxide film pattern, the contact area between the tungsten plug and the metal wiring to be formed later is increased, thereby reducing the resistance and ensuring sufficient overlap margin.
Claims (7)
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| KR1020010084914A KR20030055401A (en) | 2001-12-26 | 2001-12-26 | Forming method of semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| KR1020010084914A KR20030055401A (en) | 2001-12-26 | 2001-12-26 | Forming method of semiconductor device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| KR20030055401A true KR20030055401A (en) | 2003-07-04 |
Family
ID=32213323
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| KR1020010084914A KR20030055401A (en) | 2001-12-26 | 2001-12-26 | Forming method of semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| KR (1) | KR20030055401A (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR100833423B1 (en) | 2006-04-06 | 2008-05-29 | 주식회사 하이닉스반도체 | Method of manufacturing a semiconductor device |
-
2001
- 2001-12-26 KR KR1020010084914A patent/KR20030055401A/en not_active Application Discontinuation
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR100833423B1 (en) | 2006-04-06 | 2008-05-29 | 주식회사 하이닉스반도체 | Method of manufacturing a semiconductor device |
| US7572729B2 (en) | 2006-04-06 | 2009-08-11 | Hynix Semiconductor Inc. | Method of manufacturing semiconductor device |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| US10755974B2 (en) | Interconnect structure and method of forming same | |
| KR0185298B1 (en) | Forming method of plug for contact hole | |
| KR20050044376A (en) | Method of eliminating voids in w plugs | |
| US5966632A (en) | Method of forming borderless metal to contact structure | |
| KR20030000137A (en) | Manufacturing method for semiconductor device | |
| KR20030055401A (en) | Forming method of semiconductor device | |
| JP3691982B2 (en) | Manufacturing method of semiconductor device | |
| KR100548548B1 (en) | Method of forming multi-layer metal line with deposition process of interlayer insulator after plug | |
| JPH11186274A (en) | Dual damascene technique | |
| JP2003152074A (en) | Method for manufacturing semiconductor device | |
| JP2000049228A (en) | Dual damascene structure | |
| KR100408683B1 (en) | Method for forming contact of semiconductor device | |
| KR100606537B1 (en) | Method for forming the metal interconnect of semiconductor device using full back process | |
| KR19990084958A (en) | Double inlay structure and manufacturing method thereof | |
| KR20030052664A (en) | Method for forming nano metal line pattern | |
| JP2000243829A (en) | Dual damask structure and its manufacture | |
| KR100439477B1 (en) | Fabricating method of Tungsten plug in semiconductor device | |
| KR100295140B1 (en) | Metal wiring layer formation method of semiconductor device | |
| KR100203298B1 (en) | Interconnecting method of semiconductor device | |
| JPH09115888A (en) | Manufacture of semiconductor device | |
| KR20040055159A (en) | Method for forming contact plug of semiconductor device | |
| JPH1117004A (en) | Semiconductor device and manufacture thereof | |
| KR100364811B1 (en) | method for forming dual damascene of semiconductor device | |
| JPH04280455A (en) | Manufacture of semiconductor device | |
| KR20000054967A (en) | Method of forming contact hole in semiconductor device |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| WITN | Withdrawal due to no request for examination |