KR20030052628A - Method of fabricating capacitor in ferroelectric semiconductor memory device - Google Patents
Method of fabricating capacitor in ferroelectric semiconductor memory device Download PDFInfo
- Publication number
- KR20030052628A KR20030052628A KR1020010082646A KR20010082646A KR20030052628A KR 20030052628 A KR20030052628 A KR 20030052628A KR 1020010082646 A KR1020010082646 A KR 1020010082646A KR 20010082646 A KR20010082646 A KR 20010082646A KR 20030052628 A KR20030052628 A KR 20030052628A
- Authority
- KR
- South Korea
- Prior art keywords
- upper electrode
- memory device
- capacitor
- ferroelectric
- forming
- Prior art date
Links
- 239000003990 capacitor Substances 0.000 title claims abstract description 29
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 16
- 239000004065 semiconductor Substances 0.000 title abstract description 5
- 238000000034 method Methods 0.000 claims abstract description 29
- 239000000758 substrate Substances 0.000 claims abstract description 8
- 238000000151 deposition Methods 0.000 claims description 12
- 238000005530 etching Methods 0.000 claims description 12
- 238000005229 chemical vapour deposition Methods 0.000 claims description 9
- 229910052741 iridium Inorganic materials 0.000 claims description 6
- 229910052697 platinum Inorganic materials 0.000 claims description 6
- 229910052707 ruthenium Inorganic materials 0.000 claims description 6
- 239000000203 mixture Substances 0.000 claims description 3
- 229910019897 RuOx Inorganic materials 0.000 claims 2
- VRIVJOXICYMTAG-IYEMJOQQSA-L iron(ii) gluconate Chemical compound [Fe+2].OC[C@@H](O)[C@@H](O)[C@H](O)[C@@H](O)C([O-])=O.OC[C@@H](O)[C@@H](O)[C@H](O)[C@@H](O)C([O-])=O VRIVJOXICYMTAG-IYEMJOQQSA-L 0.000 claims 2
- 238000004070 electrodeposition Methods 0.000 abstract description 2
- BASFCYQUMIYNBI-UHFFFAOYSA-N platinum Chemical compound [Pt] BASFCYQUMIYNBI-UHFFFAOYSA-N 0.000 description 10
- 239000010408 film Substances 0.000 description 7
- 239000011229 interlayer Substances 0.000 description 7
- 238000000231 atomic layer deposition Methods 0.000 description 6
- 230000004888 barrier function Effects 0.000 description 6
- 239000004020 conductor Substances 0.000 description 5
- 229910052751 metal Inorganic materials 0.000 description 5
- 239000002184 metal Substances 0.000 description 5
- 230000008021 deposition Effects 0.000 description 4
- KJTLSVCANCCWHF-UHFFFAOYSA-N Ruthenium Chemical compound [Ru] KJTLSVCANCCWHF-UHFFFAOYSA-N 0.000 description 3
- 230000010354 integration Effects 0.000 description 3
- GKOZUEZYRPOHIO-UHFFFAOYSA-N iridium atom Chemical compound [Ir] GKOZUEZYRPOHIO-UHFFFAOYSA-N 0.000 description 3
- 238000002955 isolation Methods 0.000 description 3
- 239000010410 layer Substances 0.000 description 3
- 230000010287 polarization Effects 0.000 description 3
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 3
- 229920005591 polysilicon Polymers 0.000 description 3
- 150000001875 compounds Chemical class 0.000 description 2
- 238000005137 deposition process Methods 0.000 description 2
- 238000011161 development Methods 0.000 description 2
- 230000018109 developmental process Effects 0.000 description 2
- 239000003989 dielectric material Substances 0.000 description 2
- 238000009792 diffusion process Methods 0.000 description 2
- 239000012535 impurity Substances 0.000 description 2
- 230000015572 biosynthetic process Effects 0.000 description 1
- 229910052797 bismuth Inorganic materials 0.000 description 1
- 230000005684 electric field Effects 0.000 description 1
- 230000005518 electrochemistry Effects 0.000 description 1
- 229910052746 lanthanum Inorganic materials 0.000 description 1
- 230000007257 malfunction Effects 0.000 description 1
- 239000000463 material Substances 0.000 description 1
- 238000000059 patterning Methods 0.000 description 1
- 239000010409 thin film Substances 0.000 description 1
- 229910052726 zirconium Inorganic materials 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L28/00—Passive two-terminal components without a potential-jump or surface barrier for integrated circuits; Details thereof; Multistep manufacturing processes therefor
- H01L28/40—Capacitors
- H01L28/60—Electrodes
- H01L28/75—Electrodes comprising two or more layers, e.g. comprising a barrier layer and a metal layer
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
- H01L21/283—Deposition of conductive or insulating materials for electrodes conducting electric current
- H01L21/288—Deposition of conductive or insulating materials for electrodes conducting electric current from a liquid, e.g. electrolytic deposition
- H01L21/2885—Deposition of conductive or insulating materials for electrodes conducting electric current from a liquid, e.g. electrolytic deposition using an external electrical current, i.e. electro-deposition
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L28/00—Passive two-terminal components without a potential-jump or surface barrier for integrated circuits; Details thereof; Multistep manufacturing processes therefor
- H01L28/40—Capacitors
- H01L28/60—Electrodes
- H01L28/65—Electrodes comprising a noble metal or a noble metal oxide, e.g. platinum (Pt), ruthenium (Ru), ruthenium dioxide (RuO2), iridium (Ir), iridium dioxide (IrO2)
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B53/00—Ferroelectric RAM [FeRAM] devices comprising ferroelectric memory capacitors
Landscapes
- Engineering & Computer Science (AREA)
- Power Engineering (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Semiconductor Memories (AREA)
Abstract
Description
본 발명은 강유전체 메모리 소자의 캐패시터 제조방법에 관한 것으로 특히, 고집적 FeRAM에서 사용되는 캐패시터의 상부전극을 형성하는 방법에 관한 것이다.The present invention relates to a method for manufacturing a capacitor of a ferroelectric memory device, and more particularly, to a method of forming an upper electrode of a capacitor used in a high density FeRAM.
일반적으로, 반도체 메모리 소자에서 강유전체를 캐패시터에 사용함으로써 DRAM(Dynamic Random Access Memory) 소자에서 필요한 리프레쉬(Refresh)의 한계를 극복하고 대용량의 메모리를 이용할 수 있는 소자의 개발이 진행되어왔다.In general, by using a ferroelectric in a capacitor in a semiconductor memory device, development of a device capable of using a large-capacity memory while overcoming the limitation of refresh required in a DRAM (Dynamic Random Access Memory) device has been in progress.
이러한 강유전체를 이용하는 강유전체 메모리 소자(Ferroelectric Random Access Memory; 이하 'FeRAM'이라 약칭함)는 비휘발성 메모리 소자(Nonvolatile Memory device)의 일종으로 전원이 끊어진 상태에서도 저장 정보를 기억하는 장점이 있을 뿐만 아니라 동작 속도도 DRAM에 필적하여 차세대 기억소자로 각광받고 있다.Ferroelectric Random Access Memory (hereinafter referred to as 'FeRAM') using the ferroelectric is a nonvolatile memory device, which is a kind of nonvolatile memory device. Speeds are also comparable to DRAMs and are gaining popularity as next-generation memory devices.
이러한 FeRAM 소자의 유전체로는 페로브스카이트(Perovskite) 구조를 갖는 (Bi,La)4Ti3O12(이하 BLT), SrBi2Ta2O9(이하 SBT), SrxBiy(TaiNbj)2O9(이하 SBTN), BaxSr(1-x)TiO3(이하, BST), Pb(Zr,Ti)O3(이하 PZT) 와 같은 강유전체가 주로 사용되며, 이러한 강유전체는 상온에서 유전상수가 수백에서 수천에 이르고 두 개의 안정한 잔류분극(Remnant polarization; Pr) 상태를 갖고 있어 이를 박막화하여 비휘발성(Nonvolatile) 메모리 소자로의 응용이 실현되고 있다.Dielectrics of such FeRAM devices include (Bi, La) 4 Ti 3 O 12 (hereinafter referred to as BLT), SrBi 2 Ta 2 O 9 (hereinafter referred to as SBT), and Sr x Bi y (Ta i ) having a perovskite structure. Ferroelectrics such as Nb j ) 2 O 9 (hereinafter referred to as SBTN), Ba x Sr (1-x) TiO 3 (hereinafter referred to as BST) and Pb (Zr, Ti) O 3 (hereinafter referred to as PZT) are mainly used. At room temperature, the dielectric constant reaches hundreds to thousands and has two stable Remnant polarization (Pr) states, which are thinned to realize applications as nonvolatile memory devices.
강유전체를 이용하는 비휘발성 메모리 소자는, 가해주는 전기장의 방향으로 분극의 방향을 조절하여 신호를 입력하고 전기장을 제거하였을 때 남아있는 잔류분극의 방향에 의해 디지털 신호 '1'과 '0'을 저장하는 히스테리시스 (Hysteresis) 특성을 이용한다.Non-volatile memory devices using ferroelectrics adjust the direction of polarization in the direction of the electric field to store the digital signals '1' and '0' by the direction of residual polarization remaining when the signal is removed. Hysteresis characteristics are used.
BLT, SBT, SBTN 과 같은 강유전체는 그 유전율이 매우 높아서 메모리 소자의 셀 캐패시터로 사용되는 경우에 작은 캐패시터 면적에서도 충분한 정전용량을 확보할 수 있는 장점이 있다. 이 때문에 수 기가(giga) 비트급 메모리소자에서 셀 캐패시터로서 BLT, SBT, SBTN 박막을 이용한 강유전체 캐패시터에 관한 개발이 많이 이루어지고 있다.Ferroelectrics such as BLT, SBT, and SBTN have a very high dielectric constant, and thus, when used as a cell capacitor of a memory device, there is an advantage that sufficient capacitance can be secured even in a small capacitor area. For this reason, many developments have been made on ferroelectric capacitors using BLT, SBT, and SBTN thin films as cell capacitors in giga-bit memory devices.
2차원 구조인 평판형으로 제조되는 FeRAM은 캐패시터의 면적의 증가에 한계가 있기 때문에 고집적화가 어렵기 때문에 캐패시터를 3차원 구조로 형성하여 캐패시터의 용량을 확보함과 동시에 소자의 고집적화를 용이하게 하는 방법이 제시되었다.Since the FeRAM manufactured in the planar form, which is a two-dimensional structure, has a limitation in increasing the area of the capacitor, it is difficult to achieve high integration, so that the capacitor is formed in a three-dimensional structure to secure the capacity of the capacitor and at the same time facilitate the high integration of the device. This has been presented.
도1 내지 도3은 3차원구조인 스택(stack)형태를 갖는 FeRAM 캐패시터의 제조공정을 도시한 도면으로 이를 참조하여 종래기술을 설명한다.1 to 3 illustrate a manufacturing process of a FeRAM capacitor having a stack form having a three-dimensional structure, with reference to the related art.
먼저, 도1에 도시된 것처럼 트랜지스터(미도시) 형성을 위한 공정이 실시된 반도체 기판(11) 상에 층간절연막(12)을 증착하고, 층간절연막(12)을 선택적으로 식각하여 트랜지스터의 불순물확산층, 예를 들면, 소오스/드레인 영역(미도시)이 노출되는 콘택홀을 형성한다. 이어 콘택홀에 폴리실리콘(13)을 매립 및 평탄화한 다음, 배리어 메탈(14)을 형성한다.First, as shown in FIG. 1, an interlayer insulating film 12 is deposited on a semiconductor substrate 11 on which a process for forming a transistor (not shown) is performed, and the interlayer insulating film 12 is selectively etched to form an impurity diffusion layer of the transistor. For example, contact holes may be formed to expose source / drain regions (not shown). Then, the polysilicon 13 is buried and planarized in the contact hole, and then the barrier metal 14 is formed.
이어서, 배리어 메탈(14)을 포함하는 층간절연막(12) 상에 하부전극 (15)용 전도물질을 증착하고 선택적으로 식각한다. 하부전극용 전도물질로는 백금(Pt), 루테늄(Ru), 이리듐(Ir) 또는 이들을 이용한 화합물이 주로 사용된다.Subsequently, a conductive material for the lower electrode 15 is deposited and selectively etched on the interlayer insulating film 12 including the barrier metal 14. As the conductive material for the lower electrode, platinum (Pt), ruthenium (Ru), iridium (Ir) or compounds using them are mainly used.
이어서 도1에 도시된 것처럼 하부전극(15)을 포함한 전면에 유전체(16)를 전면증착하는데 FeRAM에서 사용되는 유전체로는 전술한 바와 같이 BLT, SBT, SBTN, PZT 등과 같은 고유전체가 사용되며 유전체 증착공정은 화학기상증착 (Chemical Vapor Deposition:CVD)법 또는 단원자증착법 (Atomic Layer Deposition)법 등을 이용한다.Subsequently, as shown in FIG. 1, a high dielectric material such as BLT, SBT, SBTN, PZT, etc. is used as the dielectric used in FeRAM to deposit the entire surface of the dielectric 16 on the front surface including the lower electrode 15. The deposition process may be performed by chemical vapor deposition (CVD) or atomic layer deposition (Atomic Layer Deposition).
다음으로 유전체(16)상에 상부전극(17)을 균일한 두께로 증착하는데, 도2는 유전체(16)상에 균일한 상부전극(17)이 증착되어 있는 모습을 보인 도면으로, 상부전극(17)은 인접 셀과 전기적으로 연결되어 있음을 알수 있다.Next, a uniform thickness of the upper electrode 17 is deposited on the dielectric 16. FIG. 2 is a view showing a uniform upper electrode 17 deposited on the dielectric 16. It can be seen that 17) is electrically connected to an adjacent cell.
한편, FeRAM은 동작 특성상 DRAM과는 다르게 상부전극을 캐패시터 단위로 분리(isolation)시켜야 하는 특징이 있다. 스택 구조의 캐패시터는 이 경우 상부전극을 캐패시터 단위로 패터닝 하여야 하는데 스택 구조의 깊은 골에서 식각하여야 한다.FeRAM, on the other hand, is characterized in that the upper electrode is separated by a capacitor unit, unlike the DRAM, due to its operation characteristics. In this case, the capacitor of the stack structure should pattern the upper electrode by the capacitor unit, which should be etched in the deep valley of the stack structure.
도3에 도시된 바와 같이 상부전극(17)으로 사용되는 Pt, Ir, Ru 등을 고립시키 위해서는 도2에 도시된 바와 같이 하부전극(15)의 스택의 골짜기를 따라서 노광공정과 식각공정을 진행해야 하는데, 3차원 스택구조는 전술한 바와 같이 노광공정과 식각공정 자체를 매우 어렵게 하는 요인이 된다.As shown in FIG. 3, to isolate Pt, Ir, and Ru used as the upper electrode 17, an exposure process and an etching process are performed along the valley of the stack of the lower electrode 15 as shown in FIG. 2. As described above, the three-dimensional stack structure becomes a very difficult factor for the exposure process and the etching process itself.
또한, 상부전극(17) 식각을 위한 패턴닝시에 하부전극 스택의 크기와 간격이넓을수록 확실한 상부전극 고립을 얻을 수 있어 소자의 오동작을 막을 수 있지만, 스택의 크기와 간격이 넓어지면 소자의 고집적화에 장애가 되며 스택의 크기와 간격을 넓히는 대신에 스택의 높이를 높여서 캐패시터의 면적을 넓히는 방법을 채택할 경우에는, 높아진 스택의 높이만큼 상부전극 고립을 위한 식각공정은 더 어려워지는 문제가 있다.In addition, when the size and spacing of the lower electrode stack is wider at the time of patterning for etching the upper electrode 17, it is possible to obtain reliable upper electrode isolation to prevent malfunction of the device. In case of adopting a method of increasing the area of the capacitor by increasing the height of the stack instead of increasing the size and spacing of the stack, the etching process for the isolation of the upper electrode by the height of the stack becomes more difficult.
본 발명은 상기한 종래의 문제점을 해결하기 위한 것으로, 상부전극 식각을 용이하게 한 강유전체 메모리 소자의 캐패시터 제조방법을 제공함을 그 목적으로 한다.SUMMARY OF THE INVENTION The present invention has been made in view of the above-described problems, and an object thereof is to provide a method for manufacturing a capacitor of a ferroelectric memory device that facilitates etching of an upper electrode.
도1 내지 도3은 종래기술에 따른 3차원 스택구조를 갖는 캐패시터 제조공정을 도시한 도면,1 to 3 is a view showing a capacitor manufacturing process having a three-dimensional stack structure according to the prior art,
도4 내지 도6은 본 발명의 일실시예에 따른 3차원 스택구조를 갖는 캐패시터 제조공정을 도시한 도면.4 to 6 is a view showing a capacitor manufacturing process having a three-dimensional stack structure according to an embodiment of the present invention.
*도면의 주요부분에 대한 부호의 설명** Description of the symbols for the main parts of the drawings *
11 : 기판11: substrate
12 : 층간절연막12: interlayer insulating film
13 : 폴리실리콘 플러그13: polysilicon plug
14 : 배리어 메탈14: barrier metal
15 : 하부전극15: lower electrode
16 : 강유전체16: ferroelectric
17 : 상부전극17: upper electrode
18 : 추가 상부전극18: additional upper electrode
상기한 목적을 달성하기 위한 본 발명은, 기판에 스택형의 하부전극을 형성하는 단계; 상기 하부전극을 포함하는 상기 기판전면에 강유전체를 형성하는 단계; 상기 강유전체 상에 균일한 두께의 상부전극을 형성하는 단계; 상기 상부전극상에 추가 상부전극을 형성하는 단계; 상기 추가상부전극을 전면식각하여 상기 상부전극을 고립시키는 단계를 포함하여 이루어진다.The present invention for achieving the above object, forming a stacked bottom electrode on the substrate; Forming a ferroelectric on the entire surface of the substrate including the lower electrode; Forming an upper electrode having a uniform thickness on the ferroelectric; Forming an additional upper electrode on the upper electrode; And etching the additional upper electrode in front to isolate the upper electrode.
이하, 본 발명이 속하는 기술분야에서 통상의 지식을 가진 자가 본 발명의 기술적 사상을 용이하게 실시할 수 있을 정도로 상세히 설명하기 위하여, 본 발명의 가장 바람직한 실시예를 첨부된 도면을 참조하여 설명한다.Hereinafter, the most preferred embodiments of the present invention will be described with reference to the accompanying drawings so that those skilled in the art can easily implement the technical idea of the present invention.
도4 내지 도6은 본 발명의 일실시예에 따른 강유전체 메모리 소자의 캐패시터 제조방법을 도시한 도면으로 이를 참조하여 설명하면, 하부전극 형성후, 유전체를 증착하기까지의 공정은 종래기술과 동일하다.4 to 6 illustrate a method of manufacturing a capacitor of a ferroelectric memory device according to an embodiment of the present invention. Referring to the drawings, the process of forming a lower electrode and then depositing a dielectric is the same as in the related art. .
즉, 도4에 도시된 것처럼 트랜지스터(미도시) 형성을 위한 공정이 실시된 반도체 기판(11) 상에 층간절연막(12)을 증착하고, 층간절연막(12)을 선택적으로 식각하여 트랜지스터의 불순물확산층, 예를 들면, 소오스/드레인 영역(미도시)이 노출되는 콘택홀을 형성한다. 이어 콘택홀에 폴리실리콘(13)을 매립하고 평탄화한 다음, 배리어 메탈(14)을 형성한다.That is, as shown in FIG. 4, an interlayer insulating film 12 is deposited on the semiconductor substrate 11 on which a process for forming a transistor (not shown) is performed, and the interlayer insulating film 12 is selectively etched to form an impurity diffusion layer of the transistor. For example, contact holes may be formed to expose source / drain regions (not shown). Then, the polysilicon 13 is buried and planarized in the contact hole, and then the barrier metal 14 is formed.
이어서, 배리어 메탈(14)을 포함하는 층간절연막(12) 상에 하부전극(15)으로 사용될 전도물질을 증착하고 이를 선택적으로 식각한다. 하부전극용 전도물질로는 백금(Pt), 루테늄(Ru), 이리듐(Ir) 또는 이들을 이용한 화합물이 주로 사용된다.Subsequently, a conductive material to be used as the lower electrode 15 is deposited on the interlayer insulating layer 12 including the barrier metal 14 and selectively etched. As the conductive material for the lower electrode, platinum (Pt), ruthenium (Ru), iridium (Ir) or compounds using them are mainly used.
하부전극은 CVD법, ALD법 또는 PEALD 법 등의 여러가지 증착법을 이용하여 증착한 뒤, 식각공정을 수행하여 형성할 수 있고 또는 전기화학증착법(Electro Chemiacl Deposition : ECD)을 이용하여 형성할 수도 있다.The lower electrode may be formed by deposition using various deposition methods such as CVD, ALD, or PEALD, followed by an etching process, or may be formed by using electrochemistry deposition (ECD).
이어서 하부전극(15)을 포함한 전면에 유전체(16)를 전면증착하는데 FeRAM에서 사용되는 유전체로는 BLT, SBT, SBTN, PZT 등과 같은 강유전체가 사용되며, 유전체 증착공정은 화학기상증착 (Chemical Vapor Deposition:CVD)법 또는 단원자증착법 (Atomic Layer Deposition)법 등을 이용한다.Subsequently, ferroelectrics such as BLT, SBT, SBTN, PZT, etc. are used as the dielectric used in FeRAM to deposit the entire surface of the dielectric 16 on the entire surface including the lower electrode 15. The dielectric deposition process is a chemical vapor deposition (Chemical Vapor Deposition). : CVD or Atomic Layer Deposition is used.
유전체(16)를 증착한 후에 상부전극(17)을 증착하는 공정이 수행되는데 본발명의 일실시예에서는 백금(Pt), 이리듐(Ir), 루테늄(Ru) 또는 이들의 혼합물인 IrO, RuO 등을 사용하거나 또는 이들을 적층하여 사용할 수도 있다.After depositing the dielectric 16, a process of depositing the upper electrode 17 is performed. In one embodiment of the present invention, platinum (Pt), iridium (Ir), ruthenium (Ru), or a mixture thereof IrO, RuO, etc. May be used or may be laminated.
상부전극이 균일한 두께로 증착되도록 본 발명에서는 화학기상증착법(CVD), 단원자 증착법(ALD), 플라즈마인핸스드 단원자증착법(Plasma Enhanced ALD)을 이용하여 상부전극(17)을 증착하며 증착되는 상부전극(17)의 두께는 50 ∼ 5000Å 으로 한다.In the present invention, the upper electrode is deposited by depositing the upper electrode 17 by using chemical vapor deposition (CVD), monoatomic deposition (ALD), and plasma enhanced ALD. The thickness of the upper electrode 17 is 50 to 5000 kPa.
본 발명에서는 상부전극을 증착한 후에, 산화막 형성 및 식각공정을 통하여 메모리셀 부분만 오픈하고 전기화학증착법 (Electro Chemical Deposition : ECD)을 이용하여 상부전극(17) 상에 추가상부전극(18)을 증착하는데 ECD 법을 이용하면 도5에 도시된 바와 같은 형태의 추가상부전극(18)을 얻을 수 있다.In the present invention, after depositing the upper electrode, only the memory cell portion is opened through an oxide film formation and etching process, and the additional upper electrode 18 is formed on the upper electrode 17 by using an electrochemical deposition (ECD). Using the ECD method to deposit, an additional upper electrode 18 of the type shown in FIG. 5 can be obtained.
추가상부전극(18)은 ECD 법을 이용하여 증착되기 때문에 상부전극의 모서리 부분과 평탄면에서는 그 증착두께가 두텁게 증착되며 스택의 골짜기를 따라서 증착되는 부분은 도5에 도시된 바와 같이 얇게 증착된다.Since the additional upper electrode 18 is deposited using the ECD method, the deposition thickness is thickly deposited at the corners and the flat surface of the upper electrode, and the portion deposited along the valley of the stack is thinly deposited as shown in FIG. 5. .
이와 같은 형태의 추가상부전극은 스택의 골짜기 아래에 존재하는 추가상부전극과 상부전극을 식각하여 상부전극을 고립시키기 위한 전면식각 공정(Blanket etch)에서 충분한 식각배리어의 역할을 수행하게 된다.The additional upper electrode of this type serves as a sufficient etching barrier in a blanket etch for etching the additional upper electrode and the upper electrode under the valley of the stack to isolate the upper electrode.
본 발명의 일실시예에 따른 추가상부전극은 상부전극과 동일한 물질을 이용하여 증착할 수도 있으며 상부전극과는 다른 전도물질을 이용하여 형성될 수 있다. 또한, 추가상부전극의 두께는 50 ∼ 5000Å의 두께를 가질 수 있으며 이보다 더 두껍게 형성될 수도 있다.The additional upper electrode according to the exemplary embodiment of the present invention may be deposited using the same material as the upper electrode and may be formed using a conductive material different from the upper electrode. In addition, the thickness of the additional upper electrode may have a thickness of 50 to 5000Å and may be formed thicker than this.
이상에서 설명한 바와 같이 본 발명은 전술한 실시예 및 첨부된 도면에 의해 한정되는 것이 아니고, 본 발명이 기술적 사상을 벗어나지 않는 범위 내에서 여러 가지 치환, 변형 및 변경이 가능함이 본 발명이 속하는 기술분야에서 통상의 지식을 가진자에게 있어 명백할 것이다.As described above, the present invention is not limited to the above-described embodiments and the accompanying drawings, and the present invention may be variously substituted, modified, and changed without departing from the spirit of the present invention. It will be apparent to those of ordinary skill in the art.
본 발명을 강유전체 메모리 소자의 캐패시터 제조공정에 적용하게 되면 상부전극 고립을 위한 식각공정이 용이하게 되어 소자의 고집적화를 이룰 수 있는 효과가 있다.When the present invention is applied to the capacitor manufacturing process of the ferroelectric memory device, the etching process for the isolation of the upper electrode is facilitated, thereby achieving high integration of the device.
Claims (7)
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
KR1020010082646A KR100717767B1 (en) | 2001-12-21 | 2001-12-21 | Method of fabricating capacitor in ferroelectric semiconductor memory device |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
KR1020010082646A KR100717767B1 (en) | 2001-12-21 | 2001-12-21 | Method of fabricating capacitor in ferroelectric semiconductor memory device |
Publications (2)
Publication Number | Publication Date |
---|---|
KR20030052628A true KR20030052628A (en) | 2003-06-27 |
KR100717767B1 KR100717767B1 (en) | 2007-05-11 |
Family
ID=29577386
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
KR1020010082646A KR100717767B1 (en) | 2001-12-21 | 2001-12-21 | Method of fabricating capacitor in ferroelectric semiconductor memory device |
Country Status (1)
Country | Link |
---|---|
KR (1) | KR100717767B1 (en) |
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US8039829B2 (en) | 2008-03-28 | 2011-10-18 | Samsung Electronics Co., Ltd. | Contact structure, a semiconductor device employing the same, and methods of manufacturing the same |
Family Cites Families (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
KR100300059B1 (en) * | 1998-12-08 | 2001-09-22 | 김영환 | Fabrication method of capacitor |
KR20010016930A (en) * | 1999-08-05 | 2001-03-05 | 김지영 | Ferroelectric Capacitor Having Hybrid Top Electrode Structure and Manufacturing Method thereof |
KR100361516B1 (en) * | 2000-02-17 | 2002-11-21 | 주식회사 하이닉스반도체 | Methof for fabricating semiconductor device |
-
2001
- 2001-12-21 KR KR1020010082646A patent/KR100717767B1/en not_active IP Right Cessation
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US8039829B2 (en) | 2008-03-28 | 2011-10-18 | Samsung Electronics Co., Ltd. | Contact structure, a semiconductor device employing the same, and methods of manufacturing the same |
Also Published As
Publication number | Publication date |
---|---|
KR100717767B1 (en) | 2007-05-11 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
KR0147640B1 (en) | Capacitor of semiconductor device & its fabrication method | |
KR100891239B1 (en) | Semiconductor memory device and method for manufacturing the same | |
US6699725B2 (en) | Methods of fabricating ferroelectric memory devices having a ferroelectric planarization layer | |
US7173301B2 (en) | Ferroelectric memory device with merged-top-plate structure and method for fabricating the same | |
US11729993B2 (en) | Ferroelectric random access memory (FRAM) capacitors and methods of construction | |
US6794705B2 (en) | Multi-layer Pt electrode for DRAM and FRAM with high K dielectric materials | |
KR100442103B1 (en) | Fram and method of forming the same | |
US20090321803A1 (en) | Semiconductor device and method of manufacturing the same | |
JP3643314B2 (en) | Method for manufacturing lower electrode of capacitor stack structure | |
KR100717767B1 (en) | Method of fabricating capacitor in ferroelectric semiconductor memory device | |
US6670662B1 (en) | Semiconductor storage component with storage cells, logic areas and filling structures | |
US6534810B2 (en) | Semiconductor memory device having capacitor structure formed in proximity to corresponding transistor | |
KR100448235B1 (en) | Method for fabricating top electrode in Ferroelectric capacitor | |
KR100349687B1 (en) | Ferroelectric capacitor and method for manufacturing the same | |
KR100583961B1 (en) | Method of fabricating a plurality of box-type feroelectric capacitors | |
KR100448237B1 (en) | Ferroelectric RAM and method for fabricating the same | |
KR100362183B1 (en) | Ferroelectric capacitor and method for fabricating the same | |
KR100517907B1 (en) | Fabricating method of ferroelectric capacitor in semiconductor device | |
KR20030057644A (en) | Method for fabricating top electrode in Ferroelectric capacitor | |
KR100968428B1 (en) | Fabricating method for protecting loss of area of ferroelectric capacitor | |
KR100420405B1 (en) | Capacitor making methods of ferroelectric random access memory | |
KR100427031B1 (en) | Method for fabricating capacitor in ferroelectric semiconductor memory device | |
KR20030057643A (en) | Method for fabricating Ferroelectric capacitor | |
KR20050067506A (en) | Fabricating method of ferroelectric capacitor in semiconductor device | |
KR20050041185A (en) | Method for fabricating ferroelectric random access memory having bottom electrode isolated by dielectric |
Legal Events
Date | Code | Title | Description |
---|---|---|---|
A201 | Request for examination | ||
E701 | Decision to grant or registration of patent right | ||
GRNT | Written decision to grant | ||
FPAY | Annual fee payment |
Payment date: 20110429 Year of fee payment: 5 |
|
LAPS | Lapse due to unpaid annual fee |