KR20030057644A - Method for fabricating top electrode in Ferroelectric capacitor - Google Patents

Abstract

PURPOSE: A method for manufacturing an upper electrode of a ferroelectric capacitor is provided to be capable of reducing degradation of a ferroelectric film. CONSTITUTION: A lower electrode(25) is formed on a semiconductor substrate(21). A planarized ferroelectric film(27) is formed on the lower electrode(25). An oxide layer(28) having an opening part to expose selectively the ferroelectric film(27), is formed on the ferroelectric film. An upper electrode(29) is then formed by filling a conductive layer into the opening part and planarizing the conductive layer to expose the oxide layer(28). Then, the oxide layer(28) is removed.

Description

Method for fabricating top electrode in Ferroelectric capacitor

The present invention relates to a ferroelectric capacitor, and more particularly, to a method of forming an upper electrode.

In general, by using a ferroelectric in a capacitor in a semiconductor memory device, development of a device capable of using a large-capacity memory while overcoming the limitation of refresh required in a DRAM (Dynamic Random Access Memory) device has been in progress.

Ferroelectric Random Access Memory (hereinafter referred to as 'FeRAM') using the ferroelectric is a nonvolatile memory device, which is a kind of nonvolatile memory device. Speeds are also comparable to DRAMs and are gaining popularity as next-generation memory devices.

Dielectrics of such FeRAM devices include (Bi, La) ₄ Ti ₃ O ₁₂ (hereinafter referred to as BLT), SrBi ₂ Ta ₂ O ₉ (hereinafter referred to as SBT), and Sr _x Bi _y (Ta _i ) having a perovskite structure. Ferroelectrics such as Nb _j ) ₂ O ₉ (hereinafter SBTN) and Pb (Zr, Ti) O ₃ (hereinafter PZT) are mainly used, and these ferroelectrics have dielectric constants of hundreds to thousands at room temperature and two stable residual polarizations ( Remnant polarization (Pr) state, which has been thinned and applied to nonvolatile memory devices has been realized.

Non-volatile memory devices using ferroelectrics adjust the direction of polarization in the direction of the electric field to store the digital signals '1' and '0' by the direction of residual polarization remaining when the signal is removed. Hysteresis characteristics are used.

Ferroelectrics such as BLT, SBT, and SBTN have a very high dielectric constant, and thus, when used as a cell capacitor of a memory device, there is an advantage that sufficient capacitance can be secured even in a small capacitor area. For this reason, many developments have been made on ferroelectric capacitors using BLT, SBT, and SBTN thin films as cell capacitors in giga bit memory devices.

FIG. 1 is a cross-sectional view showing the structure of a capacitor in a conventional FeRAM, and a capacitor manufacturing process of a conventional FeRAM will be described with reference to FIG.

First, as illustrated in FIG. 1, a first interlayer insulating film 12 is deposited on a semiconductor substrate 11 on which a process for forming a transistor (not shown) is completed, and the first interlayer insulating film 12 is selectively etched to produce a transistor. A contact hole is formed to expose an impurity diffusion layer of, for example, a source / drain region (not shown). Then, the polysilicon 13 is buried and planarized in the contact hole, and then the barrier metal 14 is formed.

Subsequently, a conductive material for the lower electrode 15 is deposited on the first interlayer insulating film 12 including the barrier metal 14, and selectively etched and isolated. As the conductive material for the lower electrode, a noble metal material such as platinum (Pt), ruthenium (Ru), iridium (Ir), or a compound using the same is mainly used, or may be laminated and used. Subsequently, a second interlayer insulating film 16 is deposited on the substrate including the isolated lower electrode 15 and the planarization process is performed.

Subsequently, as a dielectric material used in FeRAM for depositing the entire surface of the ferroelectric 17 on the second interlayer insulating film 16 including the lower electrode 15, as described above, SrTiO ₃ , BST (Ba, Sr) TiO _3, or the like, may be used. A high dielectric material is used, and the dielectric deposition process uses Chemical Vapor Deposition (CVD), Atomic Layer Deposition, Spin Coating, or Sputtering.

Next, after depositing the upper electrode 18 on the dielectric 17, the exposure and etching process is performed to complete the upper electrode. In this case, the upper electrode is used to operate a cell by isolating each cell unit or linearly connecting a predetermined number.

Therefore, it is necessary to etch the upper electrode made of a noble metal material in a desired shape. Since the noble metal material is known to have a high degree of difficulty in etching, there is a limit to achieving high integration by reducing the gap between the upper electrodes, and also the thickness of the upper electrode. In order to etch the etching, the etching time is long, the ferroelectric deterioration was severe.

Disclosure of Invention The present invention has been made to solve the above-described problems, and an object of the present invention is to provide a method for manufacturing a ferroelectric capacitor, which is advantageous for high integration and reduces degradation of the ferroelectric.

1 is a cross-sectional view showing a ferroelectric capacitor formed according to the prior art;

2a to 2d are views illustrating a manufacturing process of the ferroelectric capacitor according to the present invention.

* Description of the symbols for the main parts of the drawings *

21: substrate

22: first interlayer insulating film

23: plug

24: Barrier Metal

25: lower electrode

26: second interlayer insulating film

27: ferroelectric

28: oxide film

29: upper electrode

The present invention for achieving the above object, forming a lower electrode on the substrate; Forming a planarized ferroelectric on the lower electrode; Forming an insulator having an opening on the ferroelectric, the opening having an exposed surface of the ferroelectric; And forming an upper electrode embedded in the opening of the insulator.

Hereinafter, the most preferred embodiments of the present invention will be described with reference to the accompanying drawings so that those skilled in the art can easily implement the technical idea of the present invention.

In the method of forming an upper electrode of a ferroelectric memory device according to an embodiment of the present invention, an oxide film having a predetermined thickness is deposited prior to deposition of an upper electrode, and an isolated form or a few cells are connected to a place where the upper electrode is to be formed. Etch linearly to expose the ferroelectric.

At this time, the etching of the oxide film is easier to control the line width than the upper electrode, which is a precious metal material, and the etching selectivity with the ferroelectric under the oxide film is also large, so that the gap between the upper electrodes can be formed as desired. It is easy to increase the area.

Subsequently, by depositing the precious metal material used as the upper electrode and chemical mechanical polishing (CMP) to remove the precious metal material remaining on the oxide film it is possible to easily form the upper electrode in the desired shape.

2A to 2D are views illustrating a capacitor manufacturing process of a ferroelectric memory device according to an embodiment of the present invention. Referring to this, first, FIG. 2A is a cross-sectional view showing a state in which ferroelectrics 27 are deposited. The process up to the deposition of the ferroelectric 27 used a conventional capacitor manufacturing method.

That is, the first interlayer insulating layer 22 is deposited on the semiconductor substrate 21 on which the process for forming a transistor (not shown) is completed, and the first interlayer insulating layer 22 is selectively etched to form an impurity diffusion layer of the transistor, for example. For example, a contact hole through which a source / drain region (not shown) is exposed is formed. Then, the polysilicon 23 is buried and planarized in the contact hole, and then the barrier metal 24 is formed. A titanium nitride film (TiN) or the like is used as the barrier metal.

Subsequently, a conductive material for the lower electrode 25 is deposited on the first interlayer insulating layer 22 including the barrier metal 24, and selectively etched and isolated. As the conductive material for the lower electrode, a noble metal material such as platinum (Pt), ruthenium (Ru), iridium (Ir), or a compound using the same is mainly used, or may be laminated and used. Subsequently, a second interlayer insulating film 26 is deposited on the substrate including the isolated lower electrode 25 and the planarization process is performed.

Subsequently, as the dielectric used in FeRAM for depositing the entire surface of the dielectric 27 on the second interlayer insulating layer 26 including the lower electrode 25, as described above, SrTiO ₃ , BST, (Ba, Sr) TiO _3, and the like. The same ferroelectric is used, and the ferroelectric deposition process uses Chemical Vapor Deposition (CVD), Atomic Layer Deposition, Spin Coating, or Sputtering.

Next, as illustrated in FIG. 2B, an oxide film 28 is formed on the ferroelectric 27 to a thickness of 100 to 10000 μs, and a process of selectively etching the oxide film 28 existing at the position where the upper electrode is to be formed is performed. . In the case where the oxide film 28 is selectively etched, the etching process is performed to the extent that the ferroelectric 27 positioned below the oxide film 28 is exposed.

In general, the oxide film is not only easier to control the line width than the noble metal material in the etching process, but also has a large etching selectivity with the ferroelectric material 27 present in the lower part, so that the gap between the upper electrode can be easily formed as desired. High integration can be achieved.

In the case of selectively etching the oxide film 28 present at the position where the upper electrode is to be formed, the upper electrode to be formed subsequently is isolated to each cell or used to operate a cell by linearly connecting a certain number. The oxide film 28 is also etched in an isolated form in units of cells or in a linear manner in which several cells are connected.

FIG. 2C shows the upper electrode 29 at the position where the oxide film 28 is selectively etched and removed, using chemical vapor deposition (CVD), atomic layer deposition, sputtering, or the like. ) Is formed to a thickness of 100 to 10000 GPa, and then the upper electrode 29 deposited on the oxide film 28 is removed to make it flat.

As a method for removing the upper electrode deposited on the oxide film 28, chemical mechanical polishing or blanket etch is performed until the oxide film 28 is exposed. As the upper electrode material, platinum (Pt), iridium (Ir), iridium oxide (IrOx), ruthenium (Ru), ruthenium oxide (RuOx) may be used, or a mixture thereof may be used, or a stack thereof may be used. Where x depends on the composition ratio of iridium or ruthenium and oxygen, preferably 2.

The oxide film 28 remaining between the upper electrode 29 and the adjacent upper electrode 29 may be used as a part of the interlayer insulating film or removed.

Subsequently, a general subsequent process such as an interlayer insulating film forming process or a metal wiring forming process is performed to complete the capacitor of the ferroelectric memory element, as shown in FIG. 2D.

As described above, the present invention is not limited to the above-described embodiments and the accompanying drawings, and the present invention may be variously substituted, modified, and changed without departing from the spirit of the present invention. It will be apparent to those of ordinary skill in the art.

When the present invention is applied to the manufacturing process of the ferroelectric device, the gap between the upper electrodes can be narrowed, which is advantageous for high integration, and the area of the upper electrode can be maximized to increase the reliability of the device and the time required for etching the upper electrode. Due to the reduction of the ferroelectric thin film can be prevented to deteriorate, thereby improving the characteristics of the ferroelectric.

Claims (8)

Forming a lower electrode on the substrate; Forming a planarized ferroelectric on the lower electrode; Forming an insulator having an opening on the ferroelectric, the opening having an exposed surface of the ferroelectric; And Forming an upper electrode embedded in the opening of the insulator Method of manufacturing a ferroelectric capacitor comprising a. The method of claim 1, Forming an upper electrode embedded in the opening of the insulator, Depositing an upper electrode on an insulator having an opening that exposes a predetermined surface of the ferroelectric; And Performing a planarization process to expose the insulator Method of manufacturing a ferroelectric capacitor, characterized in that it comprises a. The method of claim 2, Performing the planarization process so that the insulator is exposed, A method of producing a ferroelectric capacitor, characterized by using chemical mechanical polishing or full etching. The method of claim 2, Performing the planarization process so that the insulator is exposed, The method of manufacturing a ferroelectric capacitor, characterized in that it further comprises the step of removing the insulator. The method of claim 1, The insulator is a method of manufacturing a ferroelectric capacitor, characterized in that the oxide film. The method of claim 1, A method of manufacturing a ferroelectric capacitor, characterized in that the thickness of the insulator is 100 ~ 10000Å. The method of claim 1, The upper electrode is a method of manufacturing a ferroelectric capacitor, characterized in that formed by using platinum, ruthenium, iridium or a mixture thereof or by laminating them. The method of claim 1, The upper electrode is formed using a chemical vapor deposition method, a monoatomic deposition method or a sputtering method, and the method of manufacturing a ferroelectric capacitor, characterized in that having a thickness of 100 ~ 10000Å.