KR20030047520A - Duplexing Structure between Boards in the ATM Switching System and Operating Method thereof - Google Patents

Abstract

PURPOSE: An inter board duplex structure in an ATM switching system and a method for operating the same are provided to monitor a line state of a redundant port as well as a line state of a working port, thereby securing the reliability of the corresponding redundant port. CONSTITUTION: An inter board dual structure is formed of two boards. The two boards are duplexed with active boards and standby boards respectively. A plurality of FPGA(Field Programmable Gate Array)s(70) execute duplex switching according to the control of an upper processor. Working and redundant SERDES(Serializer/Deserializer)(80,90) receive cells in parallel from the corresponding FPGA(70) to convert the cells into series and transmit the converted cells to a line, and receive the cells in series from the line to convert the cells into parallel and transmit the converted cell to the corresponding FPGA(70). Each working SERDES(80) includes a working port(81) transmitting and receiving the cells through active lines. Each redundant SERDES(90) includes a redundant port(91) transmitting and receiving the cells through standby lines.

Description

Duplexing Structure between Boards in the ATM Switching System and Operating Method

The present invention relates to a duplex structure between boards in an ATM switching system and a method of operating the same. In particular, in a duplex structure between boards in an ATM switching system, a line state can be always monitored for redundant ports as well as working ports. The duplex structure between boards and its operation method.

Generally, in the board-to-board redundancy structure in the ATM switching system, the current state of the working port is continuously monitored, but the redundant port cannot be continuously monitored and the state monitoring is possible only after the redundancy switching is passed.

In the conventional ATM switching system, the board-to-board redundancy structure includes two boards 10 and 20 of redundancy, as shown in FIG. 1, and each of the boards 10 and 20 corresponds to an active board 11 and 21. ) And standby boards (12, 22).

Here, in each of the boards 11, 12, 21, and 22, the FPGA 30 for performing the redundancy switching under the control of the upper processor, and the cells are applied in parallel from the FPGA 30 to convert them in series. And a transmitter / receiver 40 which transmits to a line, receives cells in series from the line, converts the cells in parallel, and transmits them to the FPGA 30.

As shown in FIG. 2, the FPGA 30 includes an overhead table 31 which stores a predetermined special overhead for redundancy, and a memory 32 which stores information necessary for redundancy switching. Consists of including.

In addition, as shown in FIG. 2, the transceiver 40 includes a working port 41 for transmitting and receiving a cell through an active line, a redundant port 42 for transmitting and receiving a cell through a standby line, and a corresponding port. The multiplexer 43 selects one of a cell received through the working port 41 or a cell received through the corresponding redundant port 42 and transmits the selected multiplexer 43 to the FPGA 30.

In the duplex structure between boards in the ATM switching system having the above-described configuration, in the case of cell transmission, the cell is transmitted to the other party through both the working port 41 and the redundant port 42 of the transceiver 40 without any problem. In the case of cell reception, the multiplexer 43 of the transmission / reception unit 40 selects and receives one of the cells received through the corresponding working port 41 and the redundant port 42.

For this reason, if the status of each line is to be monitored, it is possible to continue to monitor the current state of the working port 41, but the continuous monitoring of the redundant port 42 is not possible, but only if the redundancy transfer is taken over. Status monitoring could be performed.

That is, in the related art, after performing a redundant transfer from a working port to a redundant port, the state of the transferred redundant port can be monitored, so that an unstable element that needs to be transferred in a state where reliability of the corresponding redundant port is not secured It had a flaw in not always knowing the status information of each line.

In order to solve the above disadvantages, the present invention is to monitor the line status for the redundant port as well as the working port in the duplex structure between boards in the ATM switching system, so that the corresponding redundant port of the redundant port is suitable for switching In order to secure the reliability, to secure the reliability of redundancy between boards in an ATM switching system.

1 is a block diagram showing a redundancy structure between boards in a conventional Asynchronous Transfer Mode (ATM) switching system.

FIG. 2 is a block diagram briefly illustrating a configuration of a board in FIG. 1. FIG.

3 is a block diagram showing a board-to-board redundancy structure in an ATM switching system according to an embodiment of the present invention.

FIG. 4 is a block diagram briefly illustrating a configuration of a board in FIG. 3. FIG.

5 is a flowchart illustrating a method of operating a redundant structure between boards in an ATM switching system according to an embodiment of the present invention.

Explanation of symbols on the main parts of the drawings

50, 60: board

51, 61: Active Board

52, 62: Stand-by Board

70: FPGA (Field Programmable Gate Array)

71: Overhead Table

72: Memory

80: working SERDES

81: working port

90: redundant transceiver (Redundant SERDES)

91: Redundant Port

In order to achieve the above object, the present invention provides a redundancy structure between boards in an ATM switching system including an FPGA that performs redundancy switching under the control of a higher processor. Two transceivers for converting serial / parallel are included in each board, including a transceiver for transmitting and receiving active boards and cells through a working port, and a redundant transceiver for transmitting and receiving standby boards and cells through redundant ports. It is characterized by.

On the other hand, the redundant structure operation method between the boards in the ATM switching system according to an embodiment of the present invention for achieving the above object is to determine whether or not the active port by checking the presence of a working port in the board in the ATM switching system Process; Transmitting a cell by adding data for informing the state of each line at the same time to two lines of the working port and the redundant port when the active board is the active board; Receiving a cell for two lines of the working port and the redundant port at the same time to determine the state of each line; And reporting the status of the identified line to a higher processor and determining which data to retransmit by informing each line status.

Preferably, when the standby board is a step of transmitting the idle cell by adding data for indicating the line status at the same time for the lines of the two redundant ports; Receiving idle cells for the lines of the two redundant ports at the same time and determining the state of the corresponding lines; The method may further include reporting the state of the identified line to a higher processor and determining which data to retransmit by informing each line state.

Also preferably, the step of transmitting a cell through the transmission line of the working port by adding data for informing the error state when an error occurs in the receiving line of the working port; Receiving the cell and checking a state of a reception line of the redundant port to switch to a reception line of the redundant port; Retransmitting a cell through the redundant port by adding data for indicating a transfer completion status; And receiving the retransmission cell and reporting a switchover from the working port to the redundant port to a higher processor.

Further preferably, the step of re-checking the state of the receiving line of the working port when an error occurs in the receiving line of the redundant port; The method may further include performing board switching from the active board to the standby board when the state of the receiving line of the working port continues to be an error. Hereinafter, embodiments of the present invention will be described in detail with reference to the accompanying drawings.

As shown in FIG. 3, the redundancy structure between the boards in the ATM switching system according to the present invention includes two boards 50 and 60 formed of redundancy, and each of the boards 50 and 60 is an active board. (51, 61) and the standby board (61, 62) are made redundant, and also to ensure the reliability of the redundant transfer by diagnosing and preserving the standby state, that is, the normal status of the path that does not transmit traffic (Traffic) In addition to the traffic cell information between the paths that are in the standby state, data such as flags or bits for the diagnosis and maintenance status are added, and the corresponding 'traffic + flag' is also transmitted to the other side in the standby state. The side that receives the corresponding traffic + flag monitors the information and checks the sender's status, and then retransmits the corresponding traffic + flag. The standby side path in the on-line state is made to be in a normal or abnormal state.

Here, in each of the boards 51, 52, 61, and 62, an FPGA 70 for performing redundant switching under the control of an upper processor and a cell are applied in parallel from the FPGA 70 to be converted in series. It includes two transceivers 80 and 90 which transmit to a line and receive cells in series from the line, convert them in parallel, and transmit the same to the FPGA 70.

In addition, as shown in FIG. 4, the FPGA 70 includes an overhead table 71 that stores a predetermined special overhead for redundancy, and a memory 72 that stores information required for redundancy switching and a receiving cell. )

In addition, as shown in FIG. 4, the working transmission / reception unit 80 includes a working port 81 for transmitting and receiving cells through an active line.

In addition, the redundant transceiver 90 includes a redundant port 91 for transmitting and receiving cells through a standby line, as shown in FIG.

Referring to the flowchart of FIG. 5, a method for operating a redundant structure between boards in an ATM switching system according to an exemplary embodiment of the present invention is as follows.

First, in the FPGA 70 provided in each of the boards 51, 52, 61, and 62, the working port 81 of the working transceiver 80 is located in the boards 51, 52, 61, and 62 where it is located. It is checked whether the boards 51, 52, 61, and 62 are located in the active board or the standby board (step S1).

Accordingly, when the boards 51, 52, 61, and 62 on which the self is located are the active boards 51 and 61 in the first step S1, the FPGA 70 may include two transceiver chips. That is, the working transmission / reception unit 80 and the redundant transmission / reception unit 90 are controlled. In the case where a user traffic cell of every n- (Byte) is to be transmitted, the working transmission / reception unit 80 may work. For both the port 81 and the redundant port 91 of the redundant transmission / reception unit 90, a bit pattern for informing the appropriate line state from the internal overhead table 71 is searched simultaneously (step S2).

In addition, the FPGA 70 attaches the searched bit pattern to the front of each user traffic cell as an obhead (eg, a flag of m (Bit)) to the working transceiver 80 and the redundant transceiver 90. (Step S3).

Accordingly, each of the working transmission / reception unit 80 and the redundant transmission / reception unit 90 receives a user traffic cell having the corresponding overhead in parallel from the FPGA 70 and converts the same to a counterpart in a normal state. The other party is informed of his / her current state such as an error state, a transfer completion state, an active state, a standby state, a walking start request, and the like (step S4).

Thereafter, when receiving the overhead user traffic cell, simultaneous reception is performed on both the working port 81 of the working transceiver 80 and the redundant port 91 of the redundant transceiver 90. S5), each of the working transmission / reception unit 80 and the redundant transmission / reception unit 90 receives a user traffic cell having the overhead in series from the other side, converts them in parallel, and includes a memory provided in the FPGA 70 ( 72), for example, in the RAM (step S6).

Thus, the FPGA 70 reads and interprets the overhead of m (Bit), which is the front part of the user traffic cell stored in the memory 72, to determine the state of the line (step S7), and thus the result. After reporting to the higher processor (step S8), it is determined according to the result which overhead is attached and retransmitted to the other party (step S9).

For example, if the result is an error state, duplication transfer is performed. At this time, the cell carrying the bit pattern indicating the error state in the overhead is transmitted to the counterpart in the above-described operation.

On the other hand, when the boards 51, 52, 61, and 62 on which the self is located are the standby boards 52 and 62 in the first step S1, the FPGA 70 transmits two redundant transceivers 90. Only the redundant port 91 is searched for a bit pattern from the internal overhead table 71 to inform the appropriate line state (step S10).

In addition, the FPGA 70 attaches the searched bit pattern to the two redundant transceiver units 90 by attaching them as an obhead (eg, a flag of m (Bit)) to the front of an idle cell. (Step S11).

Accordingly, the redundant transceiver unit 90 receives the idle cells having the corresponding overhead in parallel from the FPGA 70, converts them in series, and transmits them to the other party, thereby providing a normal state, an error state, a transfer completion state, and an active state. The other party is informed of the current state of itself, such as a state, a standby state, a walking start request, and the like (step S12).

Then, when receiving the idle cell with the overhead is received only for the redundant port 91 of the redundant transceiver 90 (step S13), the redundant transceiver 90 is in series from the other side The overhead idle cell is received and only the overhead is stored in a memory 72 provided in the FPGA 70, for example, RAM (step S14).

Accordingly, the FPGA 70 determines the state of the line by reading and analyzing the overhead of m (Bit) stored in the memory 72 (step S15), and then reports the result to the higher processor. (Step S16) According to the result, it is determined what overhead to attach and resend to the other party (step S17).

An operation as described above will be described with reference to FIGS. 3 and 4 as an example.

Each board (50, 60) transmits the corresponding cell at the same time through the working port 81 and the redundant port (91) when transmitting the cell, and transmit and receive so that the idle cell continues to exchange even in the idle state In the FPGA 70, a special overhead for redundancy is transmitted to a corresponding cell. Here, the overhead represents a normal state, an error state, a transfer completion state, an active state, a standby state, a walking start request, and the like.

In addition, the first board 50 informs the second board 60 of the state of the second line L2, which is an active receiving line, through the first line L1, which is an active transmission line, while the second board 60 is notified. ) Informs the state of the first line L1 through the corresponding second line L2.

At this time, when both of the lines L1 and L2 are normal, after reading the bit pattern indicating the normal state from the overhead table 71, the read bit pattern is transmitted to the cell to be transmitted with overhead. give.

In addition, by performing the same operation as described above with respect to the standby line, that is, the third line L3 and the fourth line L4, the boards 50 and 60 each have reliability of the redundant port 91 in the state. And continue to report to higher processors.

If an error occurs in the second line L2, the first board 50 simultaneously transmits an error state to the second board 60 through the first line L1 and the third line L3. The second board 60 transfers the second line L2 to the fourth line L4 and informs the first board 50 of the transfer completion state through the fourth line L4.

As a result, the working state is switched from the first line L1 and the second line L2 to the third line L3 and the fourth line L4, and the switching is performed to change the state information of the redundant port 91. Because we know it, it can be done without any problem.

In addition, when an error occurs in the fourth line L4, after checking the state of the second line L2 again, if the error is still present, the first board 50 may use the standby board 51 in the standby board 51. A board changeover is performed at 52 to hold the seventh line L7 and the eighth line L8 in the working state.

As such, when the working port 81 is primary, not only the working port 81 but also the redundant port 91 may be monitored at all times, that is, the working port 81 and the redundant port 91 may be monitored. Both lines can be monitored simultaneously.

As described above, according to the present invention, it is possible to always monitor the line status for redundant ports as well as working ports in a redundant structure between boards in an ATM switching system, thereby ensuring reliability of the corresponding redundant port to be suitable for redundancy switching, and thereby enabling ATM exchange. Redundancy between boards can be secured in the system.

Claims (9)

In a redundancy structure between boards in an ATM switching system having an FPGA that performs redundancy switching under the control of an upper processor, Two transceivers for converting cells into parallel / serial or serial / parallel according to the control of the FPGA are included in each board, and a working transceiver for transmitting and receiving cells to and from the active board through a working port, and a standby through a redundant port. Redundancy structure between the boards in the AT switch system, characterized in that the redundant transmission and reception unit for transmitting and receiving the board and the cell. Determining whether the user is an active board by checking the presence of a working port in a board in the ATM switching system; Transmitting a cell by adding data for informing the state of each line at the same time to two lines of the working port and the redundant port when the active board is the active board; Receiving a cell for two lines of the working port and the redundant port at the same time to determine the state of each line; And reporting the status of the identified line to a higher processor and determining which data to retransmit by informing each line status. The method of claim 2, The cell transmission process includes searching for a bit pattern for notifying each appropriate line state from an overhead table for two lines of the working port and the redundant port simultaneously; Attaching the found bit pattern to the front of every user traffic cell as an overhead; And converting the overhead user traffic cells into serial and transmitting them to the other party to inform each other of the line statuses. The method of claim 2, The line status determination process may further include receiving user traffic cells having overheads simultaneously on two lines of the working port and the redundant port; Converting the overhead user traffic cells in parallel and storing them in a memory; And analyzing the overhead of the user traffic cell to determine the state of each line. The method of claim 2, Transmitting an idle cell by adding data for informing a corresponding line state at the same time to a line of two redundant ports when the standby board is a standby board; Receiving idle cells for the lines of the two redundant ports at the same time and determining the state of the corresponding lines; And reporting the status of the identified line to a higher processor and determining which data to retransmit by informing each line status. The method of claim 5, The idle cell transmission process may include searching for a bit pattern for informing each appropriate line state from an overhead table for the lines of the two redundant ports at the same time; Attaching the found bit pattern to the front of every idle cell as an obhead; And converting the idle cells with the overhead into serial and transmitting them to the other party to inform the state of the line. The method of claim 5, The line state determining process may further include receiving an idle cell having overheads simultaneously on the lines of the two redundant ports; Storing the overhead attached to the idle cell in a memory; And determining the state of the line by reading and interpreting the overhead. The method of claim 2, Transmitting a cell through a transmission line of the working port by adding data for indicating an error state when an error occurs in the reception line of the working port; Receiving the cell and checking a state of a reception line of the redundant port to switch to a reception line of the redundant port; Retransmitting a cell through the redundant port by adding data for indicating a transfer completion status; And receiving the retransmission cell and reporting a switchover from the working port to the redundant port to a higher processor. The method of claim 8, Re-checking the state of the receiving line of the working port when an error occurs in the receiving line of the redundant port; And performing a board switchover from the active board to the standby board when the state of the receiving line of the working port continues to be an error.