KR19990017861U - Switch Control Processor Board of ATM Switch System - Google Patents

Abstract

The present invention is an ATM local area network (LAN) switch system in which only the active processor operates in the asynchronous transfer method (ATM), which simultaneously writes to the active and standby DPRAMs and causes the standby processor to continue operating when the active processor is stopped due to a failure. A switch control processor (SCP) board.

To this end, the present invention generates and receives state information necessary for arbitration after initializing its own SCP board under the controller 110 responsible for system initialization, call processing and network operation, and under the control of the controller 110. An FPGA 120 that arbitrates with state information and sets a board state, a dual status interface 130 that transfers state information between the own SCP board and the counterpart SCP board, and the counterpart in the standby state of the own SCP board. DPRAM 140 capable of inputting data under the control of the SCP board, and the DPRAM by the controller 110 and the counterpart SCP board receiving signals from the FPGA 120 while the own SCP board is active. Initializing the own SCP board at the time of replacing the SCP board in the failed standby mode with the data signal transmission unit 150 involved in the data light of 140, It consists of a redundant signal transmission unit 160 that receives routing table information or OAM related information required for redundancy and transmits a signal to the SCP board in an active mode.

Description

Switch Control Processor Board of ATM Switch System

The present invention relates to a switch system for an asynchronous transfer local area network (LAN). In particular, only an active processor operates in an ATM, which simultaneously writes the active and standby DPRAMs to an active processor. A switch control processor (SCP) board of a switch system for an ATM LAN that causes a standby processor that was not operating at the time of the interruption to operate following an active processor.

As shown in the block diagram of FIG. 1, a typical ATM LAN switch system includes a plurality of line interface modules (LIMs) 10, a fabric 11 connected to the line interface modules 10, and the fabric ( 11, the first SCP board 12 and the second SCP 13 board, the first SCP board 12 and the second SCP board 13 and the Ethernet (12a) (13a) It is composed of a hub (HUB) 14 connected via a work station (W / S) 15 (or a personal computer) connected to the hub (14).

Conventionally, the SCP board used in such a switch system for an ATM LAN has a controller 20 which is in charge of initializing, call processing, and network operation of the system, as shown in the block diagram of FIG. 2, and the controller 20. Is composed of an FPGA 21 for generating state information necessary for arbitration after the board is initialized according to the control of the circuit board, a plurality of memories 22, and various interfaces (1 / F) 23-28.

However, since the SCP board of the switch system for the conventional ATM LAN has a redundancy interface (a dual status interface in FIG. 2) with only pin specifications without any logic related to redundancy, it is responsible for initializing, call processing, and network operation of the system. The failure of the controller has the problem of paralyzing the function of the system.

Therefore, the present invention has been proposed to solve the above-mentioned problems of the prior art, in which only the active processor operates in the ATM and writes to the active and standby DPRAMs at the same time. Its purpose is to provide the SCP board of the switch system for ATM LANs with the addition of redundancy, which allows it to run following an active processor.

The technical means of the present invention to achieve this purpose is to provide a dual status interface for transmitting status information between the own SCP board and the counterpart SCP board, and by controlling the counterpart SCP board in the standby state of the own SCP board. DPRAM that can input data, data signal transmission unit that receives control signals from its own SCP board in active state and participates in data write of DPRAM by the controller and counterpart SCP board, and replaces the failed standby SCP board It is characterized in that it comprises a redundancy signal transmission unit which initializes its own SCP board and obtains information necessary for redundancy and transmits a signal to the SCP board in active mode.

1 is a block diagram of a general ATM LAM switch system.

Figure 2 is a block control processor board block diagram of a conventional ATM LAM switch system.

3 is a block control processor board block diagram of an ATM LAM switch system according to the present invention;

Explanation of symbols on the main parts of the drawings

110: controller 120: FPGA

130: dual status interface 140: DPRAM

150: data signal transmission unit 160: redundant signal transmission unit

Hereinafter, the present invention will be described with reference to the accompanying drawings.

3 is a block diagram of the SCP board of the ATM LAN switch system according to the present invention, the controller 110 responsible for the initialization and call processing and network operation of the system, and when the power is supplied to the controller 110 Under control, it initializes its own SCP board and then generates the necessary status information for arbitration.When replacing a failed SCP board in standby mode, it generates status information until it initializes its own SCP board and arbitrates with the input status information. FPGA 120 for setting its own SCP board state according to the determined state, the dual status interface 130 for transferring state information between the own SCP board and the counterpart SCP board, and the own SCP board is in a standby state. DPRAM 140 for inputting data under the control of the opponent SCP board in the Receives a signal from the FPGA 120 in the active state and the data signal transmission unit 150 involved in the data write of the DPRAM 140 by the controller 110 and the counterpart SCP board, and the SCP in a failed standby mode. When the board is replaced, it consists of a redundant signal transfer unit 160 which initializes its own SCP board and receives routing table information or OAM related information necessary for redundancy and transmits a signal to the SCP board in an active mode.

Referring to Figures 1 and 3 attached to the operation and effect of the present invention configured as described above are as follows.

First, when power is supplied to the system, the first SCP board and the second SCP board initialize each board, and then transfer the status information of their SCP board to the counterpart SCP board through the dual status interface 130, and The status information is accepted.

That is, the S-PDP signal of the dual status interface 130 informs the status board that its SCP board is mounted in the system, and the S-RSTI * informs the other SCP board whether its SCP board is in the initialization state, The A-PDP signal informs his SCP board that the opponent SCP board is mounted in the system, and A-RSTI * tells his SCP board whether the opponent SCP board is in the initialization state.

At this time, when both the first SCP board and the second SCP board is in a normal state, each board outputs the S-REQ * and A-REQ * signals as active "low". Therefore, in the arbitration logic of the FPGQ 120, the first SCP board becomes the active mode in the first slot and the second SCP mode becomes the standby mode in the second slot.

Thereafter, only the active processor operates and writes both the active and standby DPRAM 140 DPs simultaneously. If the active processor is stopped due to a failure, it sends an S-ERR * signal to the second SCP board in standby mode. The board receives the signal from the opponent SCP board through the A-ERR * port and switches it to active mode in the arbitration logic of the FPGA 120.

In addition, since the SCP board in the active mode is processing information related to the OAM through the DPRAM 140, the corresponding SCP board in the standby mode is overwritten with each update.

In addition, when the SCP board enters the active mode, when the FPGA 120 sets the SCP interface as a drive type and the controller 110 writes data to the DPRAM 140, the address A [31.0] becomes the first buffer by the OE * signal. AD [31.0] signals are sent to DPRAM 140 and fabric / SCP interface 154 via 151, and DR_ * signals for writing of DPRAM 140 of the opponent SCP board are fabric / SCP interface 154. It is then forwarded to the opponent standby mode SCP board.

The data receives the DIR * signal of the FPGA 120 and transmits the DD [31.0] signal to the DPRAM 140 and the fabric / SCP interface 154 through the second buffer 152. The fabric / SCP interface 154 receives the R_W * signal from the FPGA 120 and sends P_DATA [31.0] to the opponent SCP board.

In addition, the SCP board in standby mode buffers the SCP interface 153 under the control of the FPGA 120 of its SCP board and sends ADD [31.0] and DR_W * signals to the DPRAM 140 from the SCP board in active mode, respectively. In addition, the FPGA 120 prevents input to the data bus through the second buffer 152 and only the fabric / SCP interface 154 receives the R_W * signal and sends the DD [31.0] to the DPRAM 140. The SCP board in active mode sends a TA * signal to the controller 110 to terminate the bus cycle.

On the other hand, when replacing a failed SCP board with a normal SCP board, the newly installed SCP board by HOT SWAP method that can be detached from the system or installed during the operation will initialize the hardware of the own SCP board first, The necessary routing table information or OAM related information is obtained through the redundant signal transmission unit 160, and at the same time, the S_RSTI * signal is transmitted to the SCP board in the active mode.

Next, when initialization is completed, A_REG * signal is received by the SCP board in the active mode to operate in the standby mode, and only the monitoring of the SCP board in the active mode is continued, and subsequent operations are performed according to the above-described operating principle.

As described above, the present invention operates only the active processor in ATM, writes to the active and standby DPRAM 140 at the same time, and causes the standby processor that was not operating when the active processor is stopped due to a failure to operate following the active processor. One redundancy is added.

Claims (2)

Controller responsible for system initialization, call processing and network operations; An FPGA that initializes its own SCP board under the control of the controller, generates state information for arbitration, arbitrates with the received state information, and sets the board state according to the determined state whether it is active mode or standby mode; A dual status interface for transferring status information between the own SCP board and the opponent SCP board; A DPRAM capable of inputting data under the control of the opponent SCP board while the own SCP board is in a standby state, A data signal transfer unit receiving a signal from the FPGA while the self SCP board is active and involved in data writing of the DPRAM by the controller and the counterpart SCP board; Switch for asynchronous transmission type local area network comprising a redundant signal transmission unit for initializing the own SCP board and entering the information necessary for redundancy when transferring the failed SCP board in standby mode and transmitting a signal to the SCP board in active mode Switch control processor board for the system. The method of claim 1, The FPGA is a switch control processor board of the switch system for asynchronous transmission type local area network, characterized in that when the replacement of the SCP board in the standby standby mode until the initialization of the self SCP board.