KR20030033660A - Plasma Display Panel and Driving Method Thereof and Fabricating Method of lower Substrate Thereof - Google Patents

Abstract

PURPOSE: A plasma display panel, a driving method thereof, and a method for fabricating a lower substrate thereof are provided to improve the discharge efficiency by using a plurality of auxiliary electrodes. CONSTITUTION: A scan electrode(46) and a sustain electrode(48) are formed on a back face of an upper plate(40). A plurality of bus electrodes(46',48') are formed on the scan electrode(46) and the sustain electrode(48). An upper dielectric layer(50) is formed on an upper substrate(44) of the upper plate(40). A protective layer(52) is formed on the upper dielectric layer(50). A plurality of auxiliary electrodes(56,58) are formed on a lower substrate(54) of a lower plate(42). An address electrode(62) is formed on the scan electrode(46) and the sustain electrode(48). The first lower dielectric layer(60) is formed between the auxiliary electrodes(56,58) and the address electrode(62). The second lower dielectric layer(64) is formed on the lower substrate(54) and the address electrode(62). A barrier rib(66) is vertically formed between the upper plate(40) and the lower plate(42). A phosphor(68) is coated on each surface of the second lower dielectric layer(64) and the barrier rib(66).

Description

Plasma Display Panel and Driving Method Thereof and Fabricating Method of Lower Substrate Thereof}

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a plasma display panel, and more particularly, to a plasma display panel and a driving method thereof for improving discharge efficiency without increasing a discharge voltage.

Plasma Display Panel (hereinafter referred to as "PDP") displays an image including text or graphics by emitting phosphors by 147 nm ultraviolet rays generated during discharge of He + Xe or Ne + Xe inert mixed gas. . Such a PDP is not only thin and easy to enlarge, but also greatly improved in quality due to recent technology development. In particular, the three-electrode AC surface discharge type PDP has advantages of low voltage driving and long life because wall charges are accumulated on the surface during discharge and protect the electrodes from sputtering caused by the discharge.

1 is a perspective view showing a discharge cell structure of a general AC surface discharge type PDP.

Referring to FIG. 1, the upper plate 10 and the lower plate 12 are provided in parallel with a predetermined distance. An AC driving signal is supplied to the rear surface of the upper substrate 14 constituting the upper plate 10 so that the scan electrode 16 and the sustain electrode 18 which form a sustain surface discharge are formed side by side. The scan electrode 16 and the sustain electrode 18 are transparent electrodes formed transparently of indium tin oxide (hereinafter, referred to as “ITO”). Bus electrodes 16 ′ and 18 ′ are formed side by side on each of the scan electrode 16 and the sustain electrode 18. Since ITO has a high resistance value, a uniform voltage is applied to each discharge cell by supplying an AC signal through the bus electrodes 16 'and 18'. An upper dielectric layer 28 is formed on the front surface of the upper substrate on which the scan electrodes 16 and the sustain electrodes 18 are formed. The upper dielectric layer 20 has a function of accumulating charges during discharge. The protective layer 22 coated on the entire upper dielectric layer 20 protects the upper dielectric layer 20 from sputtering during discharging, thereby extending the life of the pixel cell and increasing discharge efficiency of secondary electrons, thereby improving discharge efficiency. . On the lower substrate 24 constituting the lower plate 12, an address electrode 26 for address discharge is formed to cross at right angles to the scan electrode 16 and the sustain electrode 18. On the lower substrate 24 and the address electrode 26, a lower dielectric layer 28 is formed on the entire surface to form wall charges during discharge. In addition, the partition wall 32 is vertically formed between the upper plate 10 and the lower plate 12. The partition 32 forms the discharge space 34 of the cell together with the upper plate 10 and the lower plate 12, and distinguishes the discharge cells from each other to block mutual interference between neighboring cells. Phosphor 30 is applied to the surfaces of the lower dielectric layer 28 and the partition wall 32. The phosphor 30 is excited by ultraviolet rays generated during plasma discharge to generate visible light of any one of red, green, and blue. The discharge space 34 is filled with a mixed gas of He + Xe or Ne + Xe.

The overall structure of the electrode lines and discharge cells of the AC surface discharge PDP is shown in FIG. 2. Referring to FIG. 2, the discharge cells 34 are positioned at portions where the address electrode line X, the scan electrode line Y, and the sustain electrode line Z cross each other.

Briefly describing the light emission process, an address discharge occurs between the scan electrode 16 and the address electrode 26 to form wall charges in the upper and lower dielectric layers 20 and 28. The formed wall charges lower the discharge voltage required for surface discharge. In the cells selected by the address discharge, sustain discharge occurs between the two electrodes 16 and 18 by an alternating current signal supplied to the scan electrode 16 and the sustain electrode 18 alternately. At this time, in the discharge space 34, ultraviolet rays are generated in the process of transition after the discharge gas is excited. The generated ultraviolet rays excite the phosphor 30 to generate visible light, thereby realizing an image of the PDP.

The AC surface discharge PDP displays an image by a method of driving an address / display separate subfield (hereinafter referred to as "ADS"). 3 is a diagram illustrating an ADS driving method for expressing a gray level of one frame in the PDP. One frame for 16.67 ms is time-divided into eight subfields SF1 to SF8 according to the gradation. Each of the subfields SF1 to SF8 is largely divided into a reset and address period in which screen initialization and address discharge are performed, and a sustain period in which sustain discharge is performed. In each subfield, the widths of the preset reset and address periods are the same while the widths of the sustain periods are different. The sustain period is set in advance so as to increase at a ratio of 2 ⁿ (n = 0,1,2,3,4,5,6,7) in each subfield SFn in accordance with the luminance relative ratio.

In the PDP having the above structure, the distance between the scan electrode 16 and the sustain electrode 18 has a value of about several tens of micrometers. The most shining part between the two electrodes 16 and 18 is called a positive column, and the part where the light changes near the cathode is called a negative glow. In the negative glow, the energy of the electron decreases, and the collision with the molecules / atoms increases and the probability of opposition increases, so that light emission can be seen. In Yanggwangju, the electrons and cations have the same density and form a plasma state. There is an even electric potential gradient of several volts to several tens of volts per cm over the whole photovoltaic column, and light emission of this portion is achieved by excitation and slight recombination. The potential difference between the anodes is lowered evenly in the positive wine column and rapidly lowered in the vicinity of the cathode. This is called cathode fall.

Secondary electrons are released from the cathode by the cations accelerated by the strong electric field of the cathode drop collide with the cathode. The electrons emitted here are accelerated by a strong electric field toward the anode and ionize by colliding with gas molecules and atoms, so that the cations generated at this time cause electron emission from the cathode. As such, the cathode drop is large and the electron emission from the cathode is mainly referred to as the discharge of the cation by the glow discharge.

However, in the case where the two electrode intervals are as narrow as several tens of micrometers, the luminous efficiency is poor because there is no positive liquor having good plasma luminous efficiency and only a sub-low glow whose luminous efficiency is not good.

In order to use a positive liquor having good luminous efficiency, the electrode spacing should be about several hundred μm, but this causes a disadvantage in that the discharge voltage increases.

Accordingly, an object of the present invention is to provide a plasma display panel, a driving method thereof, and a lower substrate thereof in which a discharge efficiency is improved by using a positive light emitting light having a high discharge efficiency without increasing the distance between the scan electrode and the sustain electrode and increasing the discharge voltage. It is to provide a manufacturing method.

1 is a perspective view showing a discharge cell structure of a typical AC surface discharge plasma display panel.

2 is a plan view showing an arrangement of electrode lines and discharge cells as a whole of an AC surface discharge plasma display panel;

3 is a diagram illustrating an ADS driving method for expressing a gray level of one frame in a plasma display panel;

4 is a perspective view illustrating a discharge cell structure of a plasma display panel according to a first embodiment of the present invention.

FIG. 5 is a cross-sectional view for schematically illustrating FIG. 4. FIG.

6A to 6D are schematic views illustrating a bottom plate manufacturing process in FIG. 5.

FIG. 7 is a diagram showing driving waveforms supplied to respective electrode lines of the plasma display panel according to the second embodiment of the present invention; FIG.

8A to 8C are diagrams showing wall charge distribution formed on each electrode line during the sustain period in the driving waveform shown in FIG.

9 is a view showing a driving waveform supplied to each electrode line of the plasma display panel according to the third embodiment of the present invention.

10 is a perspective view illustrating a discharge cell structure of a plasma display panel according to a second embodiment of the present invention.

FIG. 11 is a cross-sectional view for schematically illustrating FIG. 10. FIG.

12A to 12D are schematic views illustrating a bottom plate manufacturing process in FIG. 11.

<Description of Symbols for Main Parts of Drawings>

10,40,70: Top plate 12,42,72: Bottom plate

14,44,74: upper substrate 16,46,76: scanning electrode

18,48,78: sustain electrode 20,50,80: upper dielectric layer

16 ', 18', 46 ', 48', 76 ', 78': Bus electrodes 22, 52, 82: Protective layer

24,54,84: lower substrate 26,62,86: address electrode

28,60,64,88,94: Lower dielectric layer 30,68,98: Phosphor

32,66,96: bulkhead 34: discharge cell

56,58,90,92: auxiliary electrode

In order to achieve the above object, the plasma display panel according to the present invention is the first and second sustain electrodes formed side by side at a predetermined interval so that the AC drive signal is supplied on the first substrate to achieve a sustain surface discharge, and the first And an upper dielectric layer formed to surround the second sustain electrode, a passivation layer formed on the upper dielectric layer, an address electrode formed on the second substrate in a direction crossing the first and second sustain electrodes, First and second auxiliary electrodes formed to be parallel to the first and second sustain electrodes between the second substrate and the address electrode, and partition walls formed on the second substrate in a direction parallel to the address electrodes; It is done.

The method may further include a first lower dielectric layer formed to surround the first and second auxiliary electrodes and a second lower dielectric layer formed to surround the address electrode.

The distance between the first and second sustain electrodes in the present invention is characterized in that more than 200㎛.

Another plasma display panel according to the present invention comprises a first and a second sustain electrode and the first and second sustain electrodes formed side by side at a predetermined interval so that an AC driving signal is supplied on the first substrate to achieve sustain surface discharge. An upper dielectric layer formed to surround the protective layer, a protective film formed on the upper dielectric layer, an address electrode formed on the second substrate in a direction crossing the first and second sustain electrodes, and the first electrode on the address electrode; And first and second auxiliary electrodes formed to be parallel to the second sustain electrode, and partition walls formed on the second substrate in a direction parallel to the address electrode.

The present invention may further include a first lower dielectric layer formed to surround the address electrode, and a second lower dielectric layer formed to surround the first and second auxiliary electrodes.

According to the present invention, a method of manufacturing a lower plate of a plasma display panel includes forming first and second auxiliary electrodes at predetermined intervals through photoresist patterning on the substrate, and covering the first and second auxiliary electrodes on the substrate. Forming a first lower dielectric layer on the substrate; forming an address electrode on the first lower dielectric layer to intersect the first and second auxiliary electrodes; and covering the address electrode on the substrate to cover the address electrode. And forming a lower dielectric layer.

According to another aspect of the present invention, there is provided a method of manufacturing a lower plate of a plasma display panel, including forming an address electrode through photoresist patterning on a substrate, forming a first lower dielectric layer on the substrate to cover the address electrode, and Forming first and second auxiliary electrodes on the first lower dielectric layer so as to cross the address electrode, and forming a second lower dielectric layer on the substrate to cover the first and second auxiliary electrodes; Characterized in that it comprises a.

A method of driving a plasma display panel according to the present invention is to provide a plasma display panel including an auxiliary electrode pair causing a trigger discharge to initiate sustain discharge, a sustain electrode pair causing a sustain discharge after trigger discharge, and an address electrode for address discharge. A driving method comprising: supplying a first trigger pulse having a predetermined voltage to the first auxiliary electrode to cause a trigger discharge, and after supplying the trigger pulse to a first sustain electrode facing diagonally with the first auxiliary electrode. And applying a first sustain pulse to cause a sustain discharge.

The method may further include generating a trigger discharge by supplying a second trigger pulse having a predetermined voltage to the second auxiliary electrode, and applying a second sustain pulse to a second sustain electrode diagonally opposite to the second auxiliary electrode after supplying the trigger pulse. It is characterized in that it further comprises the step of causing a sustain discharge by applying.

In the case of the present invention, the first trigger pulse and the first sustain pulse and the second trigger pulse and the second sustain pulse are alternately supplied to each other. In addition, the width of the trigger pulse and the sustain pulse is characterized by different.

The present invention is characterized in that it comprises the step of supplying a predetermined voltage to the address electrode during the sustain discharge to prevent erroneous discharge.

Other objects and features of the present invention in addition to the above object will be apparent from the description of the embodiments with reference to the accompanying drawings.

Hereinafter, exemplary embodiments of the present invention will be described with reference to FIGS. 4 to //.

4 is a perspective view illustrating a discharge cell structure of a plasma display panel according to the present invention. FIG. 5 is a cross-sectional view schematically illustrating FIG. 4.

Referring to FIG. 4 and FIG. 5, the upper plate 40 and the lower plate 42 are provided in parallel at a predetermined distance. An AC driving signal is supplied to the rear surface of the upper substrate 44 constituting the upper plate 40 so that the scan electrode 46 and the sustain electrode 48 which form a sustain surface discharge are formed side by side. The scan electrode 46 and the sustain electrode 48 are transparent electrodes formed transparently from ITO. Bus electrodes 46 'and 48' are formed side by side on the scan electrode 46 and the sustain electrode 48, respectively. Since ITO has a high resistance value, a uniform voltage is applied to each discharge cell by supplying an AC signal through the bus electrodes 46 'and 48'. At this time, the interval between the scan electrode 46 and the sustain electrode 48 is formed to be 200 μm or more. An upper dielectric layer 50 is formed on the entire surface of the upper substrate 44 on which the scan electrodes 46 and the sustain electrodes 48 are formed. The upper dielectric layer 50 has a function of accumulating charge during discharge. The protective layer 52 coated on the entire upper dielectric layer 50 protects the upper dielectric layer 50 from sputtering during discharging, thereby extending the life of the pixel cell and increasing discharge efficiency of secondary electrons to improve discharge efficiency. . On the lower substrate 54 constituting the lower plate 42, auxiliary electrodes 56 and 58 are formed in a direction parallel to the scan electrode 46 and the sustain electrode 48. On the auxiliary electrodes 56 and 58, an address electrode 26 for address discharge is formed to cross at right angles to the scan electrode 46 and the sustain electrode 48. The first lower dielectric layer 60 is entirely coated between the auxiliary electrodes 56 and 58 and the address electrode 62. On the lower substrate 54 and the address electrode 62, a second lower dielectric layer 64 is formed on the entire surface to form wall charges during discharge. In addition, the partition wall 66 is formed vertically between the upper plate 40 and the lower plate 42. The partition 66 forms a discharge space of the cell together with the upper plate 40 and the lower plate 42, and separates the discharge cells from each other to block mutual interference between neighboring cells. The phosphor 68 is coated on the surfaces of the second lower dielectric layer 64 and the partition 66. The phosphor 68 is excited by ultraviolet rays generated during plasma discharge to generate visible light of any one of red, green, and blue. The discharge space is filled with a mixed gas of He + Xe or Ne + Xe.

6A to 6D are diagrams schematically showing a lower plate manufacturing process in FIG. 5.

Referring to the manufacturing process of the lower plate, first, a pair of auxiliary electrodes 56 and 58 are formed on the lower glass substrate 54. At this time, the auxiliary electrodes 56 and 58 are spaced at intervals of 200 μm or more like the scan and sustain electrodes 46 and 48 formed on the upper plate 40. When the auxiliary electrodes 56 and 58 are formed, the first lower dielectric layer 60 is coated on the entire surface of the lower glass substrate 54 as shown in FIG. 6B.

When the first lower dielectric layer 60 is formed, an address electrode 60 is formed on the lower glass substrate 54 to intersect the auxiliary electrodes 56 and 56, as shown in FIG. 6C.

When the address electrode 60 is formed, the second lower dielectric layer 64 is coated on the entire surface of the lower glass substrate 54 as shown in FIG. 6D.

7 is a waveform diagram illustrating driving waveforms supplied to respective electrode lines of the plasma display panel according to the present invention.

Referring to Fig. 7, one subfield includes a priming and reset period for initializing the full screen, an address period for writing data while scanning the full screen in a linear order manner, and a sustain period for maintaining the light emission state of the cells in which data is written. And an erasing period for erasing discharge. First, in the priming and reset periods, all the discharge cells are initialized by causing the discharge by the priming pulse Vp applied to the respective electrode lines. During priming discharge, the charged particles generated in the discharge space 68 accumulate as wall charges in the upper and lower dielectric layers 58 and 66. The voltage Vp and the pulse width Tp of the priming pulse are always the same for each subfield. Since discharge is delayed for a certain period until discharge starts during the address period and charged particles are generated in each discharge cell, an address discharge is generated by activating a certain amount of charged particles in each discharge cell through priming discharge. High-speed drive and discharge stabilization at the time can be achieved. The wall charges accumulated in the respective discharge cells by the priming discharge lower the address discharge voltage during the address period.

In the case of an interval of 200 µm or more, since the discharge is not easily formed, the opposite discharge is used as the trigger discharge, and the positive discharge, that is, the surface discharge is caused by using the priming effect by the particles formed by the trigger discharge.

In the address period, the scan pulse (-Vs) is sequentially applied to the scan electrode lines (Y) for each scan line of the PDP, and the data voltage (Vd) is synchronized with the scan pulse (-Vs) to each address electrode line (X). ), An address discharge for cell selection occurs. In the sustain period, first, the trigger pulse TP having the same pulse width and voltage is alternately applied to the first auxiliary electrode line Aux1 and the second auxiliary electrode line Aux2 to generate a trigger discharge in the selected discharge cells. In addition, a sustain pulse (SUSP) having the same pulse width and voltage is alternately applied to the scan electrode line (Y) and the sustain electrode line (Z) to cause opposite discharge to the selected discharge cells after the trigger discharge, and at the same time, the scan electrode A positive column discharge is caused between the line Y and the sustain electrode line Z.

8A to 8C are diagrams showing wall charge distributions formed on respective electrode lines during the sustain period in the driving waveform shown in FIG.

Referring to FIGS. 7 and 8, the driving method is described first. Before the sustain pulse SSUS is applied to any one of the scan electrode line Y and the sustain electrode line Z, the sustain pulse SSUS is applied. ), The trigger pulse TP having the auxiliary voltage Vaux is applied to the auxiliary electrode line Aux. In this case, first, the electrode to which the sustain pulse SSUS is applied is the scan electrode line Y, and the electrode to which the trigger pulse TP is applied is the second auxiliary electrode line Aux2.

When the trigger pulse TP2 of the auxiliary voltage Vaux is applied to the second auxiliary electrode line Aux2, the trigger is performed between the sustain electrode line Z to which the sustain pulse SUSPy is not applied and the second auxiliary electrode line Aux2. Discharge occurs. The positive wall charges are formed on the second auxiliary electrode line Aux2 by the trigger discharge before the sustain discharge, and the negative wall charges are accumulated on the sustain electrode line Z. In addition, the upper plate coated with magnesium oxide (MgO) having a high secondary electron coefficient acts as a cathode, thereby lowering the discharge voltage.

After the trigger discharge, as shown in FIG. 8B, when the sustain pulse SSUS having the sustain voltage Vs is applied to the scan electrode line Y, the discharge of the scan electrode line Y is opposite to the address electrode X. In addition, a positive light discharge, that is, a surface discharge occurs between the sustain electrode lines Z. At this time, the width of the pulse applied to the auxiliary electrode Aux in order to reduce the amount of wall charges accumulated on the lower plate 42 than the upper plate 40 is smaller than the sustain pulse (SUSP). As a result, since the amount of wall charges is small, the discharge moves toward the surface discharge (positive column discharge) between the scan electrode line Y and the sustain electrode line Z in the counter discharge.

Subsequently, as shown in FIG. 8C, since the wall charge state is opposite to that of FIG. 8A, which is the initial state, the voltage of the second auxiliary electrode Aux2 is lowered back to 0V. This results in a sustained discharge.

Subsequently, in order to form a sustain discharge, when a voltage is applied to the first auxiliary electrode line Aux1 and the sustain electrode line X as described above even after the addressing discharge, a wall charge state as shown in FIG. 8A is formed again. For this reason, the same reset voltage is applied to the scan electrode line Y and the sustain electrode line Z formed on the upper substrate 44, and a reset discharge occurs with the address electrode X formed on the lower substrate. Discharge is generated between the scan electrode line (Y) and the address electrode (X) in the address period after the reset discharge, and a voltage higher than the voltage applied to the address electrode line (X) is applied to the sustain electrode line (Z) to help form wall charges. .

In addition, the discharge between the address electrode X and the auxiliary electrode line Aux in the lower plate 44 by additionally configuring the auxiliary electrode pairs should be suppressed as much as possible. For this purpose, a predetermined voltage is applied to the address electrode X in the sustain period as shown in FIG. As a result, the potential difference between the address electrode line X and the auxiliary electrode line Aux becomes small, and erroneous discharge can be prevented.

10 is a perspective view illustrating a discharge cell structure of a plasma display panel according to a second embodiment of the present invention. FIG. 11 is a cross-sectional view schematically illustrating FIG. 10.

Referring to FIGS. 10 and 11, the upper plate 70 and the lower plate 72 are provided in parallel with a predetermined distance. An AC driving signal is supplied to the rear surface of the upper substrate 74 constituting the upper plate 70 so that the scan electrode 76 and the sustain electrode 78 which form a sustain surface discharge are formed side by side. The scan electrode 76 and the sustain electrode 78 are transparent electrodes formed transparently from ITO. Bus electrodes 76 ', 78' are formed side by side on the scan electrode 76 and the sustain electrode 78, respectively. Since ITO has a high resistance value, a uniform voltage is applied to each discharge cell by supplying an AC signal through the bus electrodes 76 ', 78'. At this time, the interval between the scan electrode 76 and the sustain electrode 78 is formed to be 200㎛ or more. The upper dielectric layer 80 is formed on the entire surface of the upper substrate 74 on which the scan electrodes 76 and the sustain electrodes 78 are formed. The upper dielectric layer 80 has a function of accumulating charges during discharge. The protective layer 82 coated on the entire upper dielectric layer 80 protects the upper dielectric layer 80 from sputtering during discharging, thereby extending the life of the pixel cell and increasing discharge efficiency of secondary electrons to improve discharge efficiency. . On the lower substrate 84 constituting the lower plate 72, an address electrode 86 for address discharge is formed to intersect the scan electrode 76 and the sustain electrode 78. The auxiliary electrode pairs 90 and 92 are formed on the address electrode 86 in parallel with the scan electrode 76 and the sustain electrode 78. The first lower dielectric layer 60 is entirely coated between the address electrode 84 and the auxiliary electrode pairs 90 and 92. The second lower dielectric layer 94 is entirely coated on the auxiliary electrode pairs 90 and 92. In addition, the partition wall 66 is vertically formed between the upper plate 70 and the lower plate 72. The partition wall 96 forms a discharge space of the cell together with the upper plate 70 and the lower plate 72, and separates the discharge cells from each other to block mutual interference between neighboring cells. The phosphor 98 is coated on the surfaces of the second lower dielectric layer 94 and the partition 96. The phosphor 98 is excited by ultraviolet rays generated during plasma discharge to generate visible light of any one of red, green, and blue. The discharge space is filled with a mixed gas of He + Xe or Ne + Xe.

12A to 12D are diagrams schematically showing a lower plate manufacturing process in FIG. 11.

Referring to the manufacturing process of the lower plate, an address electrode 86 is first formed on the lower glass substrate 84 as shown in FIG. 12A. After the address electrode 86 is formed, the first lower dielectric layer 88 is coated on the entire surface of the lower glass substrate 84 as shown in FIG. 12B.

When the first lower dielectric layer 88 is formed, auxiliary electrode pairs 90 and 92 are formed on the lower glass substrate 54 to intersect the address electrode 86 as shown in FIG. 12C. At this time, the auxiliary electrode pairs 90 and 92 are spaced at intervals of 200 μm or more, similarly to the scan and sustain electrodes 76 and 78 formed on the upper plate 70. When the auxiliary electrode pairs 90 and 92 are formed, the second lower dielectric layer 64 is coated on the entire surface of the lower glass substrate 54 as shown in FIG. 12D. Accordingly, the driving method is the same as described with reference to FIGS. 7, 8, and 9.

As described above, the plasma display panel according to the present invention is configured such that the distance between the scan electrode and the sustain electrode is about 200 μm, and two auxiliary electrodes are formed between the lower substrate and the address so as to be parallel to the scan electrode and the sustain electrode. It is possible to improve the discharge efficiency without increasing the discharge voltage.

Those skilled in the art will appreciate that various changes and modifications can be made without departing from the technical spirit of the present invention. Therefore, the technical scope of the present invention should not be limited to the contents described in the detailed description of the specification but should be defined by the claims.

Claims (21)

First and second sustain electrodes formed side by side at a predetermined interval so that an AC driving signal is supplied on the first substrate to achieve sustain surface discharge; An upper dielectric layer formed to surround the first and second sustain electrodes; A protective film formed on the upper dielectric layer; An address electrode formed on the second substrate in a direction crossing the first and second sustain electrodes; First and second auxiliary electrodes formed parallel to the first and second sustain electrodes between the second substrate and the address electrode; And a barrier rib formed on the second substrate in a direction parallel to the address electrode. The method of claim 1, A first lower dielectric layer formed to surround the first and second auxiliary electrodes; And a second lower dielectric layer formed to surround the address electrode. The method of claim 1, And first and second bus electrodes on the first and second sustain electrodes to apply a uniform voltage to the discharge cells. The method of claim 1, And a distance between the first and second sustain electrodes is 200 μm or more. The method of claim 1, The first and second auxiliary electrodes are made of any one of silver (Ag), copper (Cu), and chromium (Cr). First and second sustain electrodes formed side by side at a predetermined interval so that an AC driving signal is supplied on the first substrate to achieve sustain surface discharge; An upper dielectric layer formed to surround the first and second sustain electrodes; A protective film formed on the upper dielectric layer; An address electrode formed on the second substrate in a direction crossing the first and second sustain electrodes; First and second auxiliary electrodes formed on the address electrode in parallel with the first and second sustain electrodes; And a barrier rib formed on the second substrate in a direction parallel to the address electrode. The method of claim 6, A first lower dielectric layer formed to surround the address electrode; And a second lower dielectric layer formed to surround the first and second auxiliary electrodes. The method of claim 6, And first and second bus electrodes on the first and second sustain electrodes to apply a uniform voltage to the discharge cells. The method of claim 6, And a distance between the first and second sustain electrodes is 200 μm or more. The method of claim 6, The first and second auxiliary electrodes are made of any one of silver (Ag), copper (Cu), and chromium (Cr). Forming first and second auxiliary electrodes at predetermined intervals through photoresist patterning on the substrate; Forming a first lower dielectric layer on the substrate to cover the first and second auxiliary electrodes; Forming an address electrode on the first lower dielectric layer to cross the first and second auxiliary electrodes; And forming the second lower dielectric layer on the substrate so as to cover the address electrode. The method of claim 11, The predetermined interval is a secondary electrode manufacturing method of the plasma display panel, characterized in that more than 200㎛. Forming an address electrode on the substrate through photoresist patterning; Forming a first lower dielectric layer on the substrate to cover the address electrode; Forming first and second auxiliary electrodes on the first lower dielectric layer in parallel with the address electrodes; Forming a second lower dielectric layer on the substrate to cover the first and second auxiliary electrodes. The method of claim 13, The predetermined interval is a lower plate manufacturing method of the plasma display panel, characterized in that. A method of driving a plasma display panel comprising: an auxiliary electrode pair causing a trigger discharge to initiate sustain discharge; a sustain electrode pair causing a sustain discharge after a trigger discharge; and an address electrode for address discharge; Supplying a first trigger pulse having a predetermined voltage to the first auxiliary electrode to cause a trigger discharge; And supplying a first sustain pulse to the first sustain electrode facing the first auxiliary electrode in a diagonal direction after the trigger pulse supply to cause a sustain discharge. The method of claim 15, Supplying a second trigger pulse having a predetermined voltage to the second auxiliary electrode to cause a trigger discharge; And supplying a second sustain pulse to a second sustain electrode facing the second auxiliary electrode in a diagonal direction after the trigger pulse is supplied to cause a sustain discharge. The method of claim 16, And the first trigger pulse, the first sustain pulse and the second trigger pulse and the second sustain pulse are alternately supplied to each other. The method of claim 17, And a width of the trigger pulse and the sustain pulse is different from each other. The method of claim 18, And the sustain pulse has a larger width than the trigger pulse. The method of claim 15, And supplying a predetermined voltage to the address electrode during the sustain discharge to prevent mis-discharge. The method of claim 20, And the predetermined voltage is a voltage corresponding to 1/2 of a trigger pulse applied to the auxiliary electrode.