KR100453161B1 - Plasma Display Panel and Driving Method Thereof and Fabricating Method of lower Plate Thereof - Google Patents

Abstract

The present invention relates to a plasma display panel and a driving method thereof for improving the discharge efficiency without increasing the discharge voltage.

A plasma display panel according to the present invention is formed on a first substrate on which first and second sustain electrodes to which sustain voltages are alternately applied, an upper dielectric layer covering the first and second sustain electrodes, and an upper dielectric layer. A second substrate having a passivation layer formed thereon, first and second auxiliary electrodes parallel to the first and second sustain electrodes, and an address electrode intersecting the sustain electrodes and the auxiliary electrodes; A partition is formed on a substrate. The first and second auxiliary electrodes are alternately supplied with an auxiliary voltage during the sustain period. After the opposite discharge is generated between the second auxiliary electrode to which the auxiliary voltage is applied and the second sustain electrode opposite thereto, the second auxiliary electrode to which the auxiliary voltage is applied is applied to the first sustain electrode facing diagonally The surface discharge occurs between the first and second sustain electrodes by the sustain voltage.

Description

Plasma display panel and driving method thereof and lower plate manufacturing method {Plasma Display Panel and Driving Method Thereof and Fabricating Method of lower Plate Thereof}

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a plasma display panel, and more particularly, to a plasma display panel and a driving method thereof for improving discharge efficiency without increasing a discharge voltage. The present invention also relates to a method of manufacturing a lower plate of the plasma display panel.

Plasma Display Panel (hereinafter referred to as "PDP") displays an image including text or graphics by emitting phosphors by 147 nm ultraviolet rays generated during discharge of He + Xe or Ne + Xe inert mixed gas. . Such a PDP is not only thin and easy to enlarge, but also greatly improved in quality due to recent technology development. In particular, the three-electrode AC surface discharge type PDP has advantages of low voltage driving and long life because wall charges are accumulated on the surface during discharge and protect the electrodes from sputtering caused by the discharge.

1 is a perspective view showing a discharge cell structure of a general AC surface discharge type PDP.

Referring to FIG. 1, the upper plate 10 and the lower plate 12 are provided in parallel with a predetermined distance. An AC driving signal is supplied to the rear surface of the upper substrate 14 constituting the upper plate 10 so that the scan electrode 16 and the sustain electrode 18 which form a sustain surface discharge are formed side by side. The scan electrode 16 and the sustain electrode 18 are transparent electrodes formed transparently of indium tin oxide (hereinafter, referred to as “ITO”). Bus electrodes 16 ′ and 18 ′ are formed side by side on each of the scan electrode 16 and the sustain electrode 18. Since ITO has a high resistance value, a uniform voltage is applied to each discharge cell by supplying an AC signal through the bus electrodes 16 'and 18'. The upper dielectric layer 20 is formed on the front surface of the upper substrate on which the scan electrodes 16 and the sustain electrodes 18 are formed. The upper dielectric layer 20 has a function of accumulating charges during discharge. The protective layer 22 coated on the entire upper dielectric layer 20 protects the upper dielectric layer 20 from sputtering during discharging, thereby extending the life of the pixel cell and increasing discharge efficiency of secondary electrons, thereby improving discharge efficiency. . On the lower substrate 24 constituting the lower plate 12, an address electrode 26 for address discharge is formed to cross at right angles to the scan electrode 16 and the sustain electrode 18. On the lower substrate 24 and the address electrode 26, a lower dielectric layer 28 is formed on the entire surface to form wall charges during discharge. In addition, the partition wall 32 is vertically formed between the upper plate 10 and the lower plate 12. The partition 32 forms the discharge space 34 of the cell together with the upper plate 10 and the lower plate 12, and distinguishes the discharge cells from each other to block mutual interference between neighboring cells. Phosphor 30 is applied to the surfaces of the lower dielectric layer 28 and the partition wall 32. The phosphor 30 is excited by ultraviolet rays generated during plasma discharge to generate visible light of any one of red, green, and blue. The discharge space 34 is filled with a mixed gas of He + Xe or Ne + Xe.

The overall structure of the electrode lines and discharge cells of the AC surface discharge PDP is as shown in FIG. Referring to FIG. 2, a discharge cell 34 is positioned at a portion where the address electrode line X, the scan electrode line Y, and the sustain electrode line Z cross each other.

Briefly describing the light emission process, an address discharge occurs between the scan electrode 16 and the address electrode 26 to form wall charges in the upper and lower dielectric layers 20 and 28. The wall charge thus formed serves to lower the discharge voltage required for surface discharge. In the cells selected by the address discharge, a sustain discharge occurs between the two electrodes 16 and 18 by an alternating current signal supplied to the scan electrode 16 and the sustain electrode 18 alternately. At this time, in the discharge space 34, ultraviolet rays are generated in the process of transition after the discharge gas is excited. The generated ultraviolet rays excite the phosphor 30 to generate visible light, thereby realizing an image of the PDP.

The AC surface discharge PDP displays an image by a method of driving an address / display separate subfield (hereinafter referred to as "ADS"). 3 is a diagram illustrating an ADS driving method for expressing a gray level of one frame in the PDP. One frame for 16.67 ms is time-divided into eight subfields SF1 to SF8 according to the gradation. Each of the subfields SF1 to SF8 is largely divided into a reset and address period in which screen initialization and address discharge are performed, and a sustain period in which sustain discharge is performed. In each subfield, the widths of the preset reset and address periods are the same while the widths of the sustain periods are different. The sustain period is set in advance so as to increase at a ratio of 2 ⁿ (n = 0,1,2,3,4,5,6,7) in each subfield SFn in accordance with the luminance relative ratio.

In the PDP having the above structure, the distance between the scan electrode 16 and the sustain electrode 18 has a value of about several tens of micrometers. The most shining part between the two electrodes 16 and 18 is called a positive column, and the part where the light changes near the cathode is called a negative glow. In the negative glow, the energy of the electron decreases, and the collision with the molecules / atoms increases and the probability of opposition increases, so that light emission can be seen. In Yanggwangju, the electrons and cations have the same density and form a plasma state. There is an even electric potential gradient of several volts to several tens of volts per cm over the positive column, and light emission of this portion is caused by slight recombination with excitation. The potential difference between the anodes is lowered evenly in the positive wine column and rapidly lowered in the vicinity of the cathode. This is called cathode fall.

Secondary electrons are released from the cathode by the cations accelerated by the strong electric field of the cathode drop collide with the cathode. The electrons emitted here are accelerated by a strong electric field toward the anode and ionize by colliding with gas molecules and atoms, so that the cations generated at this time cause electron emission from the cathode. As such, the cathode drop is large and the electron emission from the cathode is mainly referred to as the discharge of the cation by the glow discharge.

However, when the distance between the two electrodes is as small as several tens of micrometers, the luminous efficiency is poor because there is no positive liquor having good plasma luminous efficiency and only negative glow whose luminous efficiency is not good.

In order to use a positive liquor having good luminous efficiency, the electrode interval should be about several hundred μm, but in this case, there is a disadvantage in that the discharge voltage increases.

Accordingly, an object of the present invention is to provide a plasma display panel, a driving method thereof, and a lower plate manufacturing method of improving a discharge efficiency by using a positive light emitting light having a high discharge efficiency without increasing the distance between the scan electrode and the sustain electrode and increasing the discharge voltage. To provide a way.

1 is a perspective view showing a discharge cell structure of a typical AC surface discharge plasma display panel.

2 is a plan view showing an arrangement of electrode lines and discharge cells as a whole of an AC surface discharge plasma display panel;

3 is a diagram illustrating an ADS driving method for expressing a gray level of one frame in a plasma display panel;

4 is a perspective view illustrating a discharge cell structure of a plasma display panel according to a first embodiment of the present invention.

FIG. 5 is a sectional view of the plasma display panel shown in FIG. 4; FIG.

Figures 6a to 6d is a view showing step by step the manufacturing process of the lower plate shown in FIG.

7 is a view showing a driving waveform supplied to each electrode line of the plasma display panel according to the embodiment of the present invention.

8A to 8C are diagrams showing wall charge distribution on each electrode line during a sustain period changed by a driving waveform shown in FIG.

9 is a view showing a driving waveform supplied to each electrode line of a plasma display panel according to another embodiment of the present invention. FIG. 10 is a perspective view showing a discharge cell structure of a plasma display panel according to a second embodiment of the present invention. Fig. 11 is a sectional view of the plasma display panel shown in Fig. 10. Figs. 12A to 12D show step by step manufacturing steps of the lower plate shown in Fig. 11. Explanation of symbols for the main parts of the drawings > 70: Upper plate 12,42,72: Lower plate 14,44,74: Upper substrate 16,46,76: Scanning electrode 18,48,78: Sustaining electrode 20,50,80: Upper dielectric layer 16 ', 18', 46 ', 48', 76 ', 78': bus electrodes 22,52,82: protective layers 24,54,84: lower substrates 26,62,86: address electrodes 28,60,64,88,94: lower dielectric layers 30 68,98 Phosphor 32,66,96 Bulkhead 34 Discharge cell 56,58,90,92 Auxiliary electrode

In order to achieve the above object, a plasma display panel according to the present invention includes a first substrate on which first and second sustain electrodes are alternately applied with sustain voltage, an upper dielectric layer covering the first and second sustain electrodes; And a passivation layer formed on the upper dielectric layer, first and second auxiliary electrodes parallel to the first and second sustain electrodes, and an address electrode intersecting the sustain electrodes and the auxiliary electrodes. And a barrier rib formed on the second substrate. The auxiliary voltage is alternately supplied to the first and second auxiliary electrodes during the sustain period. The second auxiliary electrode to which the auxiliary voltage is applied and The sustain applied to the first sustaining electrode facing diagonally with the second auxiliary electrode to which the auxiliary voltage is applied after the opposite discharge is generated between the opposing second sustaining electrodes. The surface discharge occurs between the first and second sustain electrodes by a voltage. The plasma display panel includes a first lower dielectric layer formed on the second substrate to cover the auxiliary electrodes, and to cover the address electrode. And a second lower dielectric layer formed on the first lower dielectric layer. The plasma display panel further includes a first lower dielectric layer formed on the second substrate to cover the address electrode, and the auxiliary electrodes to cover the auxiliary electrodes. And a second lower dielectric layer formed on the first lower dielectric layer. The distance between the first and second sustain electrodes is 200 μm or more. The first and second auxiliary electrodes may include silver (Ag) and copper (Cu). ) Is a metal of any one of chromium (Cr). The lower plate manufacturing method of the plasma display panel according to the present invention is formed on a substrate by a patterning process using a photoresist. Forming first and second auxiliary electrodes spaced at predetermined intervals, forming a first lower dielectric layer on the substrate to cover the first and second auxiliary electrodes, and forming a first lower dielectric layer on the first lower dielectric layer And forming an address electrode to intersect the first and second auxiliary electrodes, and forming the second lower dielectric layer on the substrate to cover the address electrode. Forming an address electrode on the substrate by a patterning process using a photoresist, forming a first lower dielectric layer on the substrate to cover the address electrode, and intersecting the address electrode on the first lower dielectric layer Forming first and second auxiliary electrodes spaced apart from each other at predetermined intervals so as to be parallel to each other; and forming a second lower electrode on the substrate to cover the first and second auxiliary electrodes. A method of driving a plasma display panel according to the present invention includes supplying a first auxiliary voltage to a second auxiliary electrode during a sustain period, between a second auxiliary electrode and a second sustain electrode disposed thereon. Causing a trigger discharge, and applying a first sustain voltage to a first sustain electrode facing the second auxiliary electrode in a diagonal direction after the first auxiliary voltage, between the first sustain electrode and the second sustain electrode. Causing a surface discharge, supplying a second auxiliary voltage to a first auxiliary electrode to cause a trigger discharge between the first auxiliary electrode and the first sustain electrode located thereon, and following the second auxiliary voltage By applying a second sustain voltage to the second sustain electrode facing the first auxiliary electrode in a diagonal direction, the first sustain electrode and the second sustain electrode And a surface discharge. The trigger pulse for supplying the auxiliary voltage to the auxiliary electrodes and the width of the sustain pulse for supplying the sustain voltage to the sustain electrodes are different from each other. The width is larger than the pulse width of the trigger pulse. The method of driving the plasma display panel further includes supplying a predetermined voltage to the address electrode during the sustain period.

The predetermined voltage supplied to the address electrode corresponds to 1/2 of the auxiliary voltage. Other objects and features of the present invention other than the above objects will be apparent from the description of the embodiments with reference to the accompanying drawings.

Hereinafter, exemplary embodiments of the present invention will be described with reference to FIGS. 4 through 12D.

4 is a perspective view illustrating a discharge cell structure of a plasma display panel according to the present invention. FIG. 5 is a cross-sectional view schematically illustrating FIG. 4.

Referring to FIG. 4 and FIG. 5, the upper plate 40 and the lower plate 42 are provided in parallel at a predetermined distance. The back surface of the upper substrate 44 constituting the upper plate 40 is supplied with an AC drive signal to form a scan electrode 46 and a sustain electrode 48 side by side to cause a sustain surface discharge. The scan electrode 46 and the sustain electrode 48 are transparent electrodes formed transparently from ITO. Bus electrodes 46 'and 48' are formed side by side on the scan electrode 46 and the sustain electrode 48, respectively. Since ITO has a high resistance value, a uniform voltage is applied to each discharge cell by supplying an AC signal through the bus electrodes 46 'and 48'. At this time, the interval between the scan electrode 46 and the sustain electrode 48 is formed to be 200 μm or more. An upper dielectric layer 50 is formed on the entire surface of the upper substrate 44 on which the scan electrodes 46 and the sustain electrodes 48 are formed. The upper dielectric layer 50 has a function of accumulating charge during discharge. The protective layer 52 coated on the entire upper dielectric layer 50 protects the upper dielectric layer 50 from sputtering during discharging, thereby extending the life of the pixel cell and increasing discharge efficiency of secondary electrons to improve discharge efficiency. . On the lower substrate 54 constituting the lower plate 42, auxiliary electrodes 56 and 58 are formed in a direction parallel to the scan electrode 46 and the sustain electrode 48. On the auxiliary electrodes 56 and 58, an address electrode 26 for address discharge is formed to cross at right angles to the scan electrode 46 and the sustain electrode 4 + 8. The first lower dielectric layer 60 is entirely coated between the auxiliary electrodes 56 and 58 and the address electrode 62. On the lower substrate 54 and the address electrode 62, a second lower dielectric layer 64 is formed on the entire surface to form wall charges during discharge. In addition, the partition wall 66 is formed vertically between the upper plate 40 and the lower plate 42. The partition 66 forms a discharge space of the cell together with the upper plate 40 and the lower plate 42, and separates the discharge cells from each other to block mutual interference between neighboring cells. The phosphor 68 is coated on the surfaces of the second lower dielectric layer 64 and the partition 66. The phosphor 68 is excited by ultraviolet rays generated during plasma discharge to generate visible light of any one of red, green, and blue. The discharge space is filled with a mixed gas of He + Xe or Ne + Xe.

6A to 6D are diagrams schematically showing a lower plate manufacturing process in FIG. 5.

Referring to the manufacturing process of the lower plate, first, a pair of auxiliary electrodes 56 and 58 are formed on the lower glass substrate 54. At this time, the auxiliary electrodes 56 and 58 are spaced at intervals of 200 μm or more like the scan and sustain electrodes 46 and 48 formed on the upper plate 40. When the auxiliary electrodes 56 and 58 are formed, the first lower dielectric layer 60 is coated on the entire surface of the lower glass substrate 54 as shown in FIG. 6B.

When the first lower dielectric layer 60 is formed, an address electrode 60 is formed on the lower glass substrate 54 to intersect the auxiliary electrodes 56 and 56, as shown in FIG. 6C.

When the address electrode 60 is formed, the second lower dielectric layer 64 is coated on the entire surface of the lower glass substrate 54 as shown in FIG. 6D.

7 is a waveform diagram illustrating driving waveforms supplied to respective electrode lines of the plasma display panel according to the present invention.

Referring to Fig. 7, one subfield includes a priming and reset period for initializing the full screen, an address period for writing data while scanning the full screen in a linear order manner, and a sustain period for maintaining the light emission state of the cells in which data is written. And an erasing period for erasing discharge. First, in the priming and reset periods, all the discharge cells are initialized by the priming pulses applied to the respective electrode lines. The charged particles generated in the discharge space during the priming discharge are accumulated as wall charges in the upper and lower dielectric layers 50 and 64. The voltage and pulse width of the priming pulse are always the same for each subfield. Since discharge is delayed for a certain period until discharge starts during the address period and charged particles are generated in each discharge cell, an address discharge is generated by activating a certain amount of charged particles in each discharge cell through priming discharge. High-speed drive and discharge stabilization at the time can be achieved. The wall charges accumulated in the respective discharge cells by the priming discharge lower the address discharge voltage during the address period.

In the case of an interval of 200 µm or more, since the discharge is not easily formed, the opposite discharge is used as the trigger discharge, and the positive discharge, that is, the surface discharge is caused by using the priming effect by the particles formed by the trigger discharge.

In the address period, the scan pulse (-Vs) is sequentially applied to the scan electrode lines (Y) of each scan line of the PDP, and the data voltage of the data pulse (DP) is synchronized with the scan pulse (SP). Supply to (X) causes address discharge for cell selection. In the sustain period, first, trigger pulses TP having the same pulse width and voltage are alternately applied to the first auxiliary electrode line Aux1 and the second auxiliary electrode line Aux2 to generate trigger discharges in the selected discharge cells. In addition, a sustain pulse (SUSP) having the same pulse width and voltage is alternately applied to the scan electrode line (Y) and the sustain electrode line (Z) to cause opposite discharge to the selected discharge cells after the trigger discharge, and at the same time, the scan electrode A positive column discharge is caused between the line Y and the sustain electrode line Z.

8A to 8C are diagrams showing wall charge distributions formed on respective electrode lines during the sustain period in the driving waveform shown in FIG.

A driving method of the plasma display panel according to an exemplary embodiment of the present invention will be described with reference to FIGS. 7 to 8C. Before the sustain pulse SSUS is applied to the scan electrode line Y and the sustain electrode line Z, the method of driving the plasma display panel is described. The trigger pulse TP of the auxiliary voltage Vaux is applied to the auxiliary electrode line Aux on the side where the sustain pulse SSUS is not applied. The first electrode to which the sustain pulse SSUSP is applied is the scan electrode line Y. 7 and the driving waveform of FIG. 7 on the assumption that the electrode to which the first trigger pulse TP2 is applied is the second auxiliary electrode line Aux2.

First, when the trigger pulse TP2 of the auxiliary voltage Vaux is applied to the second auxiliary electrode line Aux2, the sustain electrode line Z that faces the second auxiliary electrode line Aux2 perpendicularly with a discharge space therebetween. ) And a trigger discharge occurs between the second auxiliary electrode line Aux2. As a result of the trigger discharge generated before the sustain discharge, positive wall charges are formed on the second auxiliary electrode line Aux2, and negative wall charges are accumulated on the sustain electrode line Z. In addition, the upper plate coated with magnesium oxide (MgO) having a high secondary electron coefficient acts as a cathode, thereby lowering the discharge voltage.

After this trigger discharge, as shown in FIG. 8B, the first sustain pulse SUSPy of the sustain voltage Vsus is applied to the scan electrode line Y. Then, the scan electrode line Y has a positive discharge, that is, a surface discharge, between the address electrode X and the sustain electrode line Z. On the other hand, the width of the pulse applied to the auxiliary electrode (Aux) in order to reduce the amount of wall charges accumulated on the lower plate 42 than the upper plate 40 is smaller than the sustain pulse (SUSP). As a result, since the amount of wall charge is small, the discharge moves from the opposite discharge to the surface discharge (positive column discharge) between the scan electrode line Y and the sustain electrode line Z.

Subsequently, as shown in FIG. 8C, since the wall charge state is opposite to that of FIG. 8A, which is the initial state, the voltage of the second auxiliary electrode Aux2 is lowered back to 0V. This results in a sustained discharge.

Subsequently, in order to form a sustain discharge, when a voltage is applied to the first auxiliary electrode line Aux1 and the sustain electrode line X as described above even after the addressing discharge, a wall charge state as shown in FIG. 8A is formed again. For this reason, the same reset voltage is applied to the scan electrode line Y and the sustain electrode line Z formed on the upper substrate 44, and a reset discharge occurs with the address electrode X formed on the lower substrate. Discharge is generated between the scan electrode line (Y) and the address electrode (X) in the address period after the reset discharge, and a voltage higher than the voltage applied to the address electrode line (X) is applied to the sustain electrode line (Z) to help form wall charges. .

In addition, when the auxiliary electrode pair is further configured, the discharge between the address electrode X and the auxiliary electrode line Aux in the lower plate 44 should be suppressed as much as possible. For this purpose, a predetermined voltage is applied to the address electrode X in the sustain period as shown in FIG. The voltage supplied to the address electrode X may be set to about 1/2 of the voltage supplied to the auxiliary electrode line Aux. As a result, the potential difference between the address electrode line X and the auxiliary electrode line Aux becomes small, and it is possible to prevent erroneous discharge. FIG. 10 illustrates a discharge cell structure of the plasma display panel according to the second embodiment of the present invention. One perspective view. FIG. 11 is a cross-sectional view of the plasma display panel shown in FIG. 10. Referring to FIGS. 10 and 11, the upper plate 70 and the lower plate 72 are provided in parallel at a predetermined distance. An AC driving signal is supplied to the rear surface of the upper substrate 74 constituting the upper plate 70 so that the scan electrode 76 and the sustain electrode 78 which form a sustain surface discharge are formed side by side. The scan electrode 76 and the sustain electrode 78 are transparent electrodes formed transparently from ITO. Bus electrodes 76 ', 78' are formed side by side on the scan electrode 76 and the sustain electrode 78, respectively. Since ITO has a high resistance value, a uniform voltage is applied to each discharge cell by supplying an AC signal through the bus electrodes 76 ', 78'. At this time, the interval between the scan electrode 76 and the sustain electrode 78 is formed to be 200㎛ or more. The upper dielectric layer 80 is formed on the entire surface of the upper substrate 74 on which the scan electrodes 76 and the sustain electrodes 78 are formed. The upper dielectric layer 80 has a function of accumulating charges during discharge. The protective layer 82 coated on the entire upper dielectric layer 80 protects the upper dielectric layer 80 from sputtering during discharging, thereby extending the life of the pixel cell and increasing discharge efficiency of secondary electrons to improve discharge efficiency. . On the lower substrate 84 constituting the lower plate 72, an address electrode 86 for address discharge is formed to intersect the scan electrode 76 and the sustain electrode 78. The auxiliary electrode pairs 90 and 92 are formed on the address electrode 86 in parallel with the scan electrode 76 and the sustain electrode 78. The first lower dielectric layer 88 is entirely coated between the address electrode 84 and the auxiliary electrode pairs 90 and 92. The second lower dielectric layer 94 is entirely coated on the auxiliary electrode pairs 90 and 92. In addition, a partition 96 is vertically formed between the upper plate 70 and the lower plate 72. The partition wall 96 forms a discharge space of the cell together with the upper plate 70 and the lower plate 72, and separates the discharge cells from each other to block mutual interference between neighboring cells. The phosphor 98 is coated on the surfaces of the second lower dielectric layer 94 and the partition 96. The phosphor 98 is excited by ultraviolet rays generated during plasma discharge to generate visible light of any one of red, green, and blue. A mixed gas of He + Xe or Ne + Xe is filled in the discharge space. FIGS. 12A to 12D are schematic views illustrating a manufacturing process of the lower plate in FIG. An address electrode 86 is formed on the 84 as in FIG. 12A. Then, when the address electrode 86 is formed, the first lower dielectric layer 88 is coated on the entire surface of the lower glass substrate 84 as shown in FIG. 12B. When the first lower dielectric layer 88 is formed, as shown in FIG. 12C. Auxiliary electrode pairs 90 and 92 are formed on the lower glass substrate 54 to intersect the address electrode 86. At this time, the auxiliary electrode pairs 90 and 92 are spaced at intervals of 200 μm or more, similarly to the scan and sustain electrodes 76 and 78 formed on the upper plate 70. When the auxiliary electrode pairs 90 and 92 are formed, the second lower dielectric layer 64 is coated on the entire surface of the lower glass substrate 84 as shown in FIG. 12D. Accordingly, the driving method is the same as described with reference to FIGS. 7, 8, and 9.

As described above, the plasma display panel and the driving method thereof according to the present invention are configured such that the distance between the scan electrode and the sustain electrode is about 200 μm, and the two auxiliary electrodes are arranged parallel to the scan electrode and the sustain electrode between the lower substrate and the address. By forming and driving, the discharge efficiency can be improved without increasing the discharge voltage. In addition, the lower plate manufacturing method of the plasma display panel according to the present invention can easily form two auxiliary electrodes on the lower plate.

Those skilled in the art will appreciate that various changes and modifications can be made without departing from the technical spirit of the present invention. Therefore, the technical scope of the present invention should not be limited to the contents described in the detailed description of the specification but should be defined by the claims.

Claims (21)

A plasma display panel which is driven by being divided into a reset period, an address period, and a sustain period, A first substrate having first and second sustain electrodes to which a sustain voltage is alternately applied; An upper dielectric layer covering the first and second sustain electrodes; A protective film formed on the upper dielectric layer; A second substrate having first and second auxiliary electrodes parallel to the first and second sustain electrodes, and an address electrode intersecting the sustain electrodes and the auxiliary electrodes; A barrier rib formed on the second substrate, During the sustain period, auxiliary voltages are alternately supplied to the first and second auxiliary electrodes, After the opposite discharge is generated between the second auxiliary electrode to which the auxiliary voltage is applied and the second sustain electrode opposite thereto, the second auxiliary electrode to which the auxiliary voltage is applied is applied to the first sustain electrode facing diagonally And a surface discharge is generated between the first and second sustain electrodes by the sustain voltage. The method of claim 1, A first lower dielectric layer formed on the second substrate to cover the auxiliary electrodes; And a second lower dielectric layer formed on the first lower dielectric layer to cover the address electrode. The method of claim 1, A first lower dielectric layer formed on the second substrate to cover the address electrode; And a second lower dielectric layer formed on the first lower dielectric layer to cover the auxiliary electrodes. The method of claim 1, And a distance between the first and second sustain electrodes is 200 μm or more. The method of claim 1, And the first and second auxiliary electrodes are made of any one of silver (Ag), copper (Cu), and chromium (Cr). delete delete delete delete delete In the method of manufacturing a plasma display panel which is driven divided into a reset period, an address period and a sustain period, Forming first and second auxiliary electrodes spaced at predetermined intervals on the substrate by a patterning process using a photoresist; Forming a first lower dielectric layer on the substrate to cover the first and second auxiliary electrodes; Forming an address electrode on the first lower dielectric layer to cross the first and second auxiliary electrodes; Forming the second lower dielectric layer on the substrate to cover the address electrode; And the auxiliary voltages are alternately supplied to the first and second auxiliary electrodes during the sustain period. The method of claim 11, The predetermined interval is a lower plate manufacturing method of the plasma display panel, characterized in that. In the method of manufacturing a plasma display panel which is driven divided into a reset period, an address period and a sustain period, Forming an address electrode on the substrate by a patterning process using a photoresist; Forming a first lower dielectric layer on the substrate to cover the address electrode; Forming first and second auxiliary electrodes spaced apart at predetermined intervals to intersect the address electrode on the first lower dielectric layer; Forming a second lower dielectric layer on the substrate to cover the first and second auxiliary electrodes, And the auxiliary voltages are alternately supplied to the first and second auxiliary electrodes during the sustain period. The method of claim 13, The predetermined interval is a lower plate manufacturing method of the plasma display panel, characterized in that. A first substrate on which first and second sustain electrodes are formed, first and second auxiliary electrodes parallel to the first and second sustain electrodes, and an address electrode intersecting the sustain electrodes and the auxiliary electrodes are formed. A method of driving a plasma display panel having a second substrate formed therein and being divided into a reset period, an address period, and a sustain period, the method comprising: Supplying a first auxiliary voltage to the second auxiliary electrode during the sustain period to cause a trigger discharge between the second auxiliary electrode and the second sustain electrode disposed thereon; Generating a surface discharge between the first sustain electrode and the second sustain electrode by applying a first sustain voltage to the first sustain electrode diagonally opposite to the second auxiliary electrode after the first auxiliary voltage; , Supplying a second auxiliary voltage to the first auxiliary electrode to cause a trigger discharge between the first auxiliary electrode and the first sustain electrode disposed thereon; Applying a second sustain voltage to the second sustain electrode facing the first auxiliary electrode in a diagonal direction after the second auxiliary voltage to cause surface discharge between the first sustain electrode and the second sustain electrode; Method of driving a plasma display panel comprising a. delete delete The method of claim 15, And a width of a trigger pulse for supplying the auxiliary voltage to the auxiliary electrodes and a width of the sustain pulse for supplying the sustain voltage to the sustain electrodes. The method of claim 18, And the pulse width of the sustain pulse is greater than the pulse width of the trigger pulse. The method of claim 15, And supplying a predetermined voltage to the address electrode during the sustain period. The method of claim 20, And a predetermined voltage supplied to the address electrode is a voltage corresponding to 1/2 of the auxiliary voltage.