KR20030032531A - A thin film transistor panels for liquid crystal display and methods for manufacturing the same - Google Patents

Abstract

PURPOSE: A thin film transistor substrate for a liquid crystal display device and a method for manufacturing the same are provided to reinforce an adhesive force between pads and a tap driving integrated circuit. CONSTITUTION: Gate wiring including gate lines(52), gate electrodes(56), and gate pads(53) is formed on an insulating substrate. A gate insulating film is formed on the gate wiring. Semiconductor patterns(70) are formed on the gate insulating film of the gate electrodes. Data wiring including data lines(92), source and drain electrodes(95,96), and data pads(98) is formed on the gate insulating film. A passivation film formed of a low dielectric insulating material such as SiOC or SiOF is formed through a chemical vapor deposit. The passivation film is patterned, so that the passivation film around the gate pads or the data pads is thinner than other parts. Subsequently, pixel electrodes(112) connected to the drain electrode, and auxiliary gate pads(116) and auxiliary data pads(118) connected to the gate pads and the data pads are formed.

Description

A thin film transistor substrate for a liquid crystal display device and a method of manufacturing the same {A THIN FILM TRANSISTOR PANELS FOR LIQUID CRYSTAL DISPLAY AND METHODS FOR MANUFACTURING THE SAME}

The present invention relates to a method for manufacturing a thin film transistor substrate for a liquid crystal display device.

The liquid crystal display is one of the most widely used flat panel display devices. The liquid crystal display includes two substrates on which electrodes are formed and a liquid crystal layer interposed therebetween, and rearranges the liquid crystal molecules of the liquid crystal layer by applying a voltage to the electrode. Device to display an image by adjusting the amount of transmitted light.

Among the liquid crystal display devices, a liquid crystal display device having a thin film transistor for forming an electrode on each of two substrates and switching a voltage applied to the electrode is one of the liquid crystal display devices. One of the two substrates includes a thin film transistor, a pixel electrode, a gate wiring, Data lines, gate pads, and data pads are formed, and the other substrates are generally formed with a color filter, a black matrix, and a common electrode on the front surface.

In manufacturing such a liquid crystal display device, an interlayer insulating film is formed between the wiring and the wiring or the wiring and the electrode to insulate the conductive wiring from each other by forming an interlayer insulating film made of silicon oxide (SiO ₂ ) or silicon nitride (SiN _x ). The coupling capacitance generated is so large that recently, organic insulating films such as benzocyclobutene (BCB), perfloucyclobutene (PFCB), and acrylic resin (acryl) or inorganic insulating films of SiOC are often used as interlayer insulating films. It is used to realize the aperture ratio.

On the other hand, a gate pad and a data pad to which a scan signal and an image signal are applied from the outside are formed on a substrate of the liquid crystal display device, which are connected to a tap driving integrated circuit which outputs the scan signal and the image signal. In this case, in order to connect the pad and the output terminal of the driving integrated circuit, anisotropic conductive film (ACF) is attached to the pad portion of the substrate, and the tape carrier package (TCP) is included. Is pressed to electrically connect the output terminal and the pad through the anisotropic conductive particles, which is called an outer lead bonding (OLB) process.

However, in such an OLB process, the thickness of the interlayer insulating film causes a problem in that the tab driving integrated circuit does not adhere well to the pad or falls even if attached. This is because the difference in thickness between the anisotropic conductive particles and the interlayer insulating film is not large, and thus the compressive force cannot be sufficiently transmitted to the anisotropic conductive particles when the anisotropic conductive particles are pressed onto the pad. Alternatively, when the substrate is wiped with a cotton swab or the like to remove the corrosion occurring in the pad portion, the interlayer insulating film may fall. As a result, a transparent conductive material such as ITO or IZO formed on the interlayer insulating film falls between the pads adjacent to each other apart from the interlayer insulating film, and a short circuit occurs between the pads.

SUMMARY OF THE INVENTION The present invention has been made in an effort to provide a thin film transistor substrate for a liquid crystal display device and a method of manufacturing the same, which may secure adhesive strength between a pad and an output terminal of a tab driving integrated circuit.

1 is a layout view of a thin film transistor substrate for a liquid crystal display according to a first exemplary embodiment of the present invention.

FIG. 2A is a cross-sectional view taken along the line II-II 'of FIG. 1,

2B is a cross-sectional view of a thin film transistor substrate for a liquid crystal display according to a second embodiment of the present invention;

3A is a layout view illustrating a manufacturing process of a thin film transistor substrate for a liquid crystal display according to a first embodiment of the present invention;

3B is a cross-sectional view taken along line IIIb-IIIb 'of FIG. 3A.

FIG. 4A is a layout view of a thin film transistor substrate manufactured according to an embodiment of the present invention, and illustrates the next step of FIG. 3A.

4B is a cross-sectional view taken along line IVb-IVb 'of FIG. 4A.

FIG. 5A is a layout view of a thin film transistor substrate manufactured according to an embodiment of the present invention, and illustrates the next step of FIG. 4A.

5B is a cross-sectional view taken along line Vb-Vb ′ of FIG. 5A.

FIG. 6A is a layout view of a thin film transistor substrate manufactured according to an embodiment of the present invention, and illustrates the next step of FIG. 5A.

FIG. 6B is a cross-sectional view taken along line VIb-VIb ′ of FIG. 5A;

FIG. 7A is a layout view of a thin film transistor substrate manufactured according to an embodiment of the present invention, and illustrates the next step of FIG. 6A.

FIG. 7B is a cross-sectional view taken along the line VIIb-VIIb 'of FIG. 7A;

FIG. 8A is a layout view of a thin film transistor substrate manufactured according to an embodiment of the present invention, and illustrates the next step of FIG. 7A.

FIG. 8B is a cross-sectional view taken along the line VIIIb-VIIIb ′ in FIG. 8A.

9A through 9B are cross-sectional views taken along the line VIIIb-VIIIb 'of FIG. 8A, which illustrates the previous step of FIG. 8B according to a process sequence.

10 is a plan view illustrating a gate pad or a data pad and a passivation layer thereon;

11A and 11B are cross-sectional views taken along the line VIII-VIII of FIG. 10, and are shown in the order of the process;

12 is a layout view schematically illustrating a structure of a thin film transistor substrate for a liquid crystal display according to a third exemplary embodiment of the present invention.

13 and 14 are cross-sectional views taken along lines XIII-XIII 'and XIV-XIV' of FIG. 12.

15A is a layout view illustrating a process of manufacturing a thin film transistor substrate for a liquid crystal display according to a second embodiment of the present invention;

15B and 15C are cross sectional views taken along lines XVb-XVb 'and XVc-XVc of FIG. 15A;

16A is a layout view of a thin film transistor substrate manufactured according to the second embodiment of the present invention.

16B to 16D are cross-sectional views of XVIb-XVIb 'lines and XVIc-XVIc' lines in FIG. 16A, respectively, and FIG. 16B is a cross-sectional view showing all steps of FIG. 16C.

17A and 17B are cross-sectional views taken along the lines XVIb-XVIb 'and XVIc-XVIc' in FIG. 16A, respectively, and are cross-sectional views in the next steps of FIGS. 16B and 16C;

18A is a layout view of a thin film transistor substrate in the next steps of FIGS. 17A and 17B,

18B and 18C are cross-sectional views taken along lines XVIIIb-XVIIIb 'and XVIIIc-XVIIIc' in FIG. 18A, respectively.

19A, 20A, 21A and 19B, 20B, 21B are cross-sectional views of XVIIIb-XVIIIb 'line and XVIIIc-XVIIIc' line in FIG. 18A, respectively, illustrating the following steps in the order of a process,

FIG. 22A is a layout view of a thin film transistor substrate in the next steps of FIGS. 21A and 21B;

22B and 22C are sectional views taken along lines XXIIb-XXIIb 'and XXIIc-XXIIc', respectively, in FIG. 22A.

In order to achieve the above object, in the present invention, the protective film around the pad is formed using a slit or lattice pattern to form a protective film around the pad to have a thickness thinner than other portions, or a plurality of contact holes exposing the pad in the protective film are formed. .

According to an exemplary embodiment of the present invention, a thin film transistor substrate for a liquid crystal display device includes a gate wiring including a gate line, a gate electrode, and a gate pad, a gate insulating film covering the gate wiring, and a semiconductor formed on the gate insulating film of the gate electrode. A pattern, a data wiring formed on the semiconductor pattern or the gate insulating film, including the data line, the source electrode, the drain electrode, and the data pad, covering the data wiring and the gate insulating film with an insulating material of silicon oxycarbide, and exposing the drain electrode. A pixel having a first contact hole and a second contact hole exposing a gate pad or a data pad, wherein the periphery of the second contact hole is formed to a lower thickness than other portions, and the pixel connected to the drain electrode exposed through the first contact hole. An electrode.

In this case, the substrate may further include a black matrix formed on the insulating substrate and having an opening in the pixel defined by the gate line and the data line, and a color filter of red, green, and blue on the substrate.

Alternatively, the thin film transistor substrate for a liquid crystal display device may include a gate wiring including a gate line, a gate electrode, and a gate pad, a gate insulating film covering the gate wiring, a semiconductor pattern formed over the gate insulating film of the gate electrode, and a semiconductor pattern or At least a first contact hole formed over the gate insulating film, the data wiring including a data line and a source electrode, a drain electrode and a data pad, and covering the data wiring and the gate insulating film with an insulating material of silicon oxycarbide and exposing the drain electrode. And a protective layer having two or more second contact holes exposing the gate pad or the data pad, and a pixel electrode connected to the drain electrode exposed through the first contact hole.

At this time, the size of the second contact hole is preferably formed to 5㎛ or less.

Next, a liquid crystal display and a method of manufacturing the same according to the first embodiment of the present invention will be described in detail with reference to the accompanying drawings so that a person skilled in the art can easily carry out the present invention.

First, the structure of a thin film transistor substrate for a liquid crystal display according to an exemplary embodiment of the present invention will be described in detail with reference to FIGS. 1 to 2B.

1 is a layout view of a thin film transistor substrate for a liquid crystal display according to a first embodiment of the present invention, FIG. 2A is a cross-sectional view taken along line II-II 'of FIG. 1, and FIG. 2B is a second embodiment of the present invention. It is sectional drawing of the thin film transistor substrate for liquid crystal display devices which concerns on this.

On the lower insulating substrate 10, a black matrix 22 made of a single film or a multilayer film including copper-based, aluminum-based or chromium or molybdenum-based or chromium nitride or molybdenum nitride is formed. The black matrix 22 has an opening in a matrix pixel, and is formed in a mesh shape to block light leaking between the pixels, and subsequently enter light incident on the semiconductor layer 70 of the thin film transistor. It may have a modified form to block. In this case, although not shown in the embodiment of the present invention, a gate pad and a data pad may be formed on the same layer as the black matrix to transmit scan signals and image signals from the outside to gate lines and data lines formed later.

In the upper pixel of the lower insulating substrate 10, red (R), green (G), and blue (B) color filters (31, 32, 33) whose edge portions cover the black matrix 22 are formed, respectively. Here, the color filters 31, 32, and 33 may be formed to overlap each other on the black matrix 22, and it is preferable to use a material whose color characteristics do not change due to the manufacturing temperature of the thin film transistor of 350 ° C. or higher.

On the black matrix 22 and the color filters 31, 32, and 33, a low dielectric constant of 3.0 or less, such as BCB (bisbenzocyclobutene) or perfluorocyclobutene (PFCB), etc. 40 is formed.

On the organic insulating layer 40, aluminum (Al) or aluminum alloy (Al alloy), molybdenum (Mo) or molybdenum-tungsten (MoW) alloy, chromium (Cr), tantalum (Ta), copper (Cu) or copper alloy ( A gate wiring made of a metal or a conductor such as Cu alloy) is formed. The gate wire is connected to the gate line 52, the gate electrode 56, which is a branch of the gate line 52, and the gate line 52. The gate pad receives the scan signal from the outside and transfers the scan signal to the gate line 52. (53). Here, the gate line 52 overlaps with the pixel electrode 112 to be described later to form a storage capacitor which improves the charge storage capability of the pixel, and the storage line is generated by the overlap of the pixel electrode 112 and the gate line 52 which will be described later. If the capacity is not sufficient, additional wiring for the storage capacitor may be formed.

The gate wirings 52, 53, and 56 may be formed of a single film such as copper series, aluminum series, or silver series having low resistance, but may be formed of a double layer or a triple layer.

The gate insulating film 60 made of silicon nitride (SiN _x ) covers the gate wirings 52, 53, and 56 on the organic insulating film 40, and the hydrogenated amorphous silicon is disposed on the gate insulating film 60 of the gate electrode 56. A semiconductor layer 70 made of a semiconductor such as hydrogenated amorphous silicon is formed. On the semiconductor layer 70, ohmic contact layers 85 and 86 including amorphous silicon or microcrystalline silicon or metal silicide doped at high concentration with n-type impurities such as phosphorus (P) are gated. The electrodes 56 are separated from each other and formed.

On the gate insulating layer 60 and the ohmic contacts 85 and 86, a data line made of an aluminum-based, copper-based, or silver-based conductive material having low resistance is formed. The data line is connected to the data line 92 formed in the vertical direction, the data pad 98 connected to one end of the data line 92 to receive an image signal from the outside, and the data line 92. An upper portion of the ohmic contact layer 86 opposite the source electrode 95 with respect to the gate electrode 56 and separated from the source electrode 95 and the data line portions 92, 95, 98 positioned over the contact layer 85. And a drain electrode 96 of the thin film transistor positioned at the top.

The data lines 92, 95, 96, and 98 may also be formed of a single layer of a conductive material having a low resistance like the gate lines 52 and 56, but may be formed of a double layer or a triple layer. Of course, when forming more than two layers, it is preferable that one layer is made of a material having a low resistance and the other layer is made of a material having good contact characteristics with other materials, and the data pad 98 is the same as the gate pad 53. In the case of forming a layer, it is preferable to form a single film of a conductive material having a low resistance without considering contact characteristics with other materials.

On the data lines 92, 95, 96 and 98, a protective film 100 made of a low dielectric constant insulating material such as SiOC or SiOF having a low dielectric constant is formed. Here, the passivation layer 100 has contact holes 102 and 108 exposing the drain electrode 96 and the data pad 98, and the contact hole 106 exposing the gate pad 53 together with the gate insulating film 60. Has)

As shown in FIG. 2A, the protective film 100 around the gate pad 53 and the data pad 98 has a thickness thinner than that of other portions. The pressure is sufficiently transferred to the conductive particles included in the anisotropic conductive film (ACF) in the outer lead bonding (OLB) process of attaching the driving integrated circuit to the liquid crystal panel, thereby providing the pads 53 and 98 and the driving integrated circuit. This is to enhance the adhesive strength of the pad.

A pixel electrode 112 is formed on the passivation layer 100 to receive an image signal from the thin film transistor and generate an electric field together with the electrode of the upper plate. The pixel electrode 112 is made of a transparent conductive material such as indium tin oxide (ITO) or indium zinc oxide (IZO), and is physically and electrically connected to the drain electrode 96 through the contact hole 102 to receive an image signal. I receive it. The pixel electrode 112 also overlaps the neighboring gate line 52 and the data line 92 to increase the aperture ratio, but may not overlap. On the other hand, an auxiliary gate pad 116 and an auxiliary data pad 118 connected to the gate pad 53 and the data pad 98 through the contact holes 106 and 108, respectively, are formed. , 98) and supplementing the adhesion between the external circuit device and protecting the pad, are not essential, and their application is optional.

Meanwhile, in order to secure the adhesive force of the pads 53 and 98, the protective layer 100 may have a plurality of contact holes 106 and 108 exposing the pads 26 and 98 with respect to one pad 26 and 98. . This will be described with reference to FIG. 2B.

As shown in FIG. 2B, most of the structures are the same as those of FIG. 2A, but the protective layer 100 includes one pad having contact holes 106 and 108 exposing the gate pad 53 and the data pad 98, respectively. It is formed in large number with respect to (53, 98). The plurality of contact holes 106 and 108 exposing the pads 53 and 98 may maximize the contact area of the conductive particles of the anisotropic conductive film in the subsequent OLB process to enhance the adhesion of the pads 53 and 98 to the anisotropic conductive particles. Can be. In addition, the external force generated when scratching the corrosion of the pads (53, 98) with a cotton swab can be distributed through a plurality of holes to minimize the damage to the pad.

In the thin film transistor substrate for a liquid crystal display according to the exemplary embodiment of the present invention, the passivation layer 100 around the pads 53 and 98 may be formed to have a thickness thinner than that of other portions, or one pad 53 or 98 may be formed on the passivation layer 100. A plurality of contact holes exposing the pads with respect to the pads can enhance the adhesion between the pads 53 and 98 and the driving integrated circuit. In addition, the gate insulating layer 60 and the passivation layer 100 having a low dielectric constant are formed between the data line 92 and the pixel electrode 112, so that the coupling capacitance generated between them can be minimized. It is possible to improve the properties and at the same time eliminate the need to space between them, ensuring the maximum aperture ratio.

Next, a method of manufacturing the thin film transistor substrate for a liquid crystal display device according to the first and second embodiments of the present invention will be described in detail with reference to FIGS. 3A to 11B.

First, as shown in FIGS. 3A to 3B, the conductive material is deposited by a method such as sputtering and dry or wet etching by a photolithography process using a mask to form a black matrix 22 on the lower insulating substrate 10. .

Here, the conductive material is formed of a multilayer film including a conductive material having a low resistance, such as aluminum or an aluminum alloy or a copper or a copper alloy, or a silver series, or chromium or molybdenum or titanium having excellent contact characteristics with ITO, or a chromium nitride having low reflectivity. It is desirable to.

In this case, the gate pad 53 or the data lines 92, 96, and 98 may be formed on the same layer as the black matrix 22.

Subsequently, as shown in FIGS. 4A and 4B, photosensitive materials including pigments of red, green, and blue are sequentially applied and patterned by a photo process using a mask to sequentially turn red, green, and blue color filters 31, 32, and 33. Form. In this case, it is preferable to use a heat-resistant material that does not change color characteristics even at a temperature of 350 ° C. or higher, and the red, green, and blue color filters 31, 32, and 33 are formed using three masks, but the manufacturing cost It can also be formed by using one mask while moving to reduce the. In addition, using a laser transfer method or a print method can be formed without using a mask, thereby minimizing the manufacturing cost. At this time, as shown in the figure. The edges of the color filters 31, 32, 33 of red, green, and blue are preferably formed to overlap the black matrix 22.

5A and 5B, the organic insulating layer 40 is formed on the lower insulating substrate 10 by using an organic material such as BCB or PFCB having excellent heat resistance and planarization characteristics of 350 ° C. or higher. Next, a conductive material for gate wiring having low resistance, such as aluminum, aluminum alloy, copper, copper alloy, or silver series, is sequentially stacked on the organic insulating layer 40, and the gate line 52 and the gate are formed by a photolithography process using a mask. A gate wiring including an electrode 56 and a gate pad 53 is formed. At this time, the gate wirings 52 and 56 are preferably formed inside the horizontal portion of the black matrix 22.

Here, the gate wirings 52, 56, 53 are preferably formed of a double film made of a conductive material having a low resistance and a conductive material having good contact properties with ITO or IZO.

6A and 6B, the gate insulating film 60, the semiconductor layer 70, and the ohmic contact layer 80 are deposited by chemical vapor deposition, respectively, and patterned by a photolithography process using a mask. The semiconductor layer 70 and the ohmic contact layer 80 are formed on the gate insulating layer 60 facing the electrode 53.

Next, as illustrated in FIGS. 7A to 7B, after the molybdenum, molybdenum alloy, or chromium is laminated, the data line may be patterned by a photolithography process using a mask to intersect the gate line 52 to define pixels having a matrix form. 92, a source electrode 95 connected to the data line 92 and extending to an upper portion of the gate electrode 56, a data pad 98 and a source electrode 95 connected to one end of the data line 92; A data line that is separated and includes a drain electrode 96 facing the source electrode 95 around the gate electrode 56 is formed.

Subsequently, the doped amorphous silicon layer pattern 80 not covered by the data lines 92, 95, 96, and 98 is etched so as to be separated on both sides of the gate electrode 56, while both doped amorphous silicon layers ( The semiconductor layer pattern 70 between 85 and 86 is exposed.

Next, as shown in FIGS. 8A and 8B, the protective film 100 is formed by laminating by chemical vapor deposition with a low dielectric constant insulating material having a low dielectric constant of 4.0 or less, such as SiOC or SiOF. Next, the passivation layer 100 is patterned by a photolithography process to form contact holes 102 and 108 exposing the drain electrode 96 and the data pad 98, and the gate insulating layer 60 is etched to form the gate pad 53. Contact holes 106 are formed. At this time, in the OLB process, the protective film 100 around the pads 53 and 98 is formed to have a thickness thinner than other portions so that the protective film 100 around the pads 53 and 98 can transmit sufficient pressure to the anisotropic conductive particles. To this end, a slit or lattice pattern is formed to expose and develop a photoresist film using a mask having a transflective area that can control the amount of light transmitted, thereby forming a photoresist pattern having a thin thickness, which is used as an etching mask. The protective film 100 may be etched.

As shown in FIG. 9A, a mask 200 having a transflective area capable of applying a photoresist film and partially adjusting the light transmission amount is disposed on the passivation layer 100, and then the photoresist film is exposed and developed to expose the drain electrode 96. The photoresist pattern 300 having a first portion 312 having a thickness thinner than that of the second portion 314 is formed around the pads 53 and 98. That is, a light shielding film is disposed in a region corresponding to a so as to prevent light from being transmitted, and a slit or lattice pattern is formed in a region corresponding to b to adjust the amount of light transmitted, and a region corresponding to c. The mask is placed in an empty space so that light is transmitted.

At this time, it is preferable that the slits arranged in the area corresponding to b have a line width of the pattern located between the slits or an interval between the patterns, that is, a width of the slits smaller than the resolution of the exposure machine used during exposure.

Subsequently, when the passivation layer 100 and the gate insulating layer 60 are etched using the photoresist pattern 300 as an etching mask, the drain electrode 96, the gate pad 53, and the data pad 98 may be formed as illustrated in FIG. 9B. Form exposed contact holes 102, 106, 108.

Subsequently, a portion of the passivation layer 100 is etched using the second portion 314 of the remaining photoresist pattern after etching the photoresist pattern 312 having a thin thickness, as shown in FIG. 8B. 53 and the protective film 100 around the data pad 98 is formed thinner than other portions.

In this case, in order to enhance adhesion between the pads 53 and 98 and the driving integrated circuit in the OLB process, the protective film 100 around the pads 53 and 98 may have a thickness thinner than that of the pads 53 and 98. Although formed, as in the second embodiment, a plurality of contact holes may be formed in each of the pads 53 and 98 in the protective film 100. This will be described with reference to FIGS. 10 to 11B.

FIG. 10 is a plan view illustrating a structure of a pad unit in which a gate pad or a data pad is formed, and FIG. 11A is a cross-sectional view taken along the line 'Ia-'Ia' of FIG. 10, and shows both the gate pad and the data pad. Is a cross-sectional view of the next step in FIG. 11A.

First, as shown in FIGS. 10 and 11A, a plurality of contact holes 106 and 108 are formed in the protective film 100 around the pads 53 and 98. At this time, the data pad 98 is exposed through the contact hole 108. Next, as shown in FIG. 11B, the gate insulating film 60 is etched to expose the gate pad 53 through the contact hole 106. At this time, the size of the contact holes 106 and 108 is formed equal to or smaller than the size of the anisotropic conductive particles having a size of about 5㎛. This allows the protective film 100 around the pads 53 and 98 to maximize the contact area with the anisotropic conductive particles and to the surface of the protective film 100 around the pads 53 and 98 when removing the corrosion by the swab. Adhesion can be distributed to multiple holes.

Next, as shown in FIGS. 2A and 2B, the ITO film is stacked and patterned using a mask to contact the pixel electrode 112 and the contact holes 106 and 108 connected to the drain electrode 96 through the contact hole 102. The auxiliary gate pads 116 and the auxiliary data pads 118 connected to the gate pads 53 and the data pads 98 are respectively formed through the first and second gate pads 53 and 102.

In the method of manufacturing the liquid crystal display according to the exemplary embodiment of the present invention, as described above, the protective film 100 around the pads 53 and 98 is thinner than the protective film 100 in other portions except the pads 53 and 98. It may be formed to have a thickness to enhance the adhesion of the pads (53, 98) and the driving integrated circuit. In addition, a plurality of contact holes exposing the pads 53 and 98 may be formed in the passivation layer 100 to maximize the contact area between the pads 53 and 98 and the anisotropic conductive particles. In addition, since the color filters 31, 32, 33, and the black matrix 22 are formed together with the thin film transistors on the lower substrate 10, the aperture ratio of the lower substrate and the upper substrate may not be considered, and thus the aperture ratio may be improved. have. Of course, the color filters 31, 32, 33 and the black matrix 22 may be formed on the upper substrate facing the lower substrate 10.

As described above, the first and second embodiments of the present invention can be applied to a manufacturing method of completing a thin film transistor on an organic insulating film using five masks, but using four masks on an organic insulating film. The present invention can also be applied to a method for producing a thin film transistor substrate. This will be described in detail with reference to the drawings.

First, a unit pixel structure of a thin film transistor substrate for a liquid crystal display device having a thin film transistor completed using four masks according to an exemplary embodiment of the present invention will be described in detail with reference to FIGS. 12 to 14.

12 is a layout view of a thin film transistor substrate for a liquid crystal display according to a third exemplary embodiment of the present invention, and FIGS. 13 and 14 are XIII-XIII 'lines and XIV-XIV' lines, respectively, of the thin film transistor substrate shown in FIG. The cross section for

First, the black matrix 22 and the color filters 31, 32, and 33 and the organic insulating layer 40 covering them are formed on the insulating substrate 10 as in the first embodiment.

The gate wiring including the gate line 52, the gate pad 54, and the gate electrode 56 is formed on the organic insulating layer 40. The gate wiring includes a sustain electrode 58 that is parallel to the gate line 52 on the substrate 10 and receives a voltage such as a common electrode voltage input to the common electrode of the upper plate from the outside. The storage electrode 58 overlaps the conductive capacitor conductor 98 for the storage capacitor connected to the pixel electrode 112, which will be described later, to form a storage capacitor that improves the charge retention capability of the pixel. The pixel electrode 112 and the gate line, which will be described later, If the holding capacity generated by the overlap of 52 is sufficient, it may not be formed.

A gate insulating film 60 made of silicon nitride (SiN _x ) is formed on the gate wirings 52, 54, 56, and 58 to cover the gate wirings 52, 54, 56, and 58.

Semiconductor patterns 72 and 78 made of a semiconductor such as hydrogenated amorphous silicon are formed on the gate insulating layer 60, and high concentrations of n-type impurities such as phosphorus (P) are formed on the semiconductor patterns 72 and 78. An ohmic contact layer pattern or an intermediate layer pattern 85, 86, 88 made of amorphous silicon doped with is formed.

On the ohmic contact layer patterns 85, 86, and 88, data lines made of a conductive material such as Mo or MoW alloy, Cr, Al or Al alloy, and Ta are formed. The data line is a thin film transistor which is a branch of the data line 92 formed in the vertical direction, the data pad 94 connected to one end of the data line 92 to receive an image signal from the outside, and the data line 92. And a data line portion of the source electrode 95 of the source electrode 95, and separated from the data line portions 92, 94, and 95, and with respect to the gate electrode 56 or the channel portion C of the thin film transistor. It also includes a conductive capacitor conductor 98 for the storage capacitor located on the drain electrode 96 and the storage electrode 58 of the thin film transistor located on the opposite side. When the sustain electrode 58 is not formed, the conductor pattern 98 for the storage capacitor is also not formed.

The data lines 92, 94, 95, 96, and 98 may also be formed in a single layer like the gate lines 52, 54, 56, and 58, but may be formed in a double layer or a triple layer. In the case of forming, it is preferable that one layer is made of a material having a low resistance and the other layer is made of a material having good contact properties with other materials.

The contact layer patterns 85, 86, and 88 serve to lower the contact resistance between the semiconductor patterns 72 and 78 below and the data wires 92, 94, 95, 96, and 98 above them. It has the exact same form as (92, 94, 95, 96, 98). That is, the data line part intermediate layer pattern 85 is the same as the data line parts 92, 94 and 95, the drain electrode intermediate layer pattern 86 is the same as the drain electrode 96, and the storage capacitor intermediate layer pattern 88 is It is the same as the conductor pattern 98 for holding capacitors.

The semiconductor patterns 72 and 78 have the same shapes as the data lines 92, 94, 95, 96 and 98 and the ohmic contact layer patterns 85, 86 and 87 except for the channel portion C of the thin film transistor. Doing. Specifically, the semiconductor capacitor 48 for the storage capacitor, the conductor pattern 98 for the storage capacitor, and the contact layer pattern 88 for the storage capacitor have the same shape, but the semiconductor pattern 72 for the thin film transistor has data wiring and contact. Slightly different from the rest of the layer pattern. That is, in the channel portion C of the thin film transistor, the data line portions 92, 94, and 95, in particular, the source electrode 95 and the drain electrode 96 are separated, and the contact layer pattern for the data line intermediate layer 85 and the drain electrode. Although 86 is also separated, the semiconductor pattern 72 for thin film transistors is connected here without disconnection to generate a channel of the thin film transistor.

On the data lines 92, 94, 95, 96, and 98, a protective film 100 made of a low dielectric constant insulating material such as SiOC or SiOF formed through chemical vapor deposition and having a low dielectric constant of 4.0 or less is formed. 100 has contact holes 101, 103, 104 exposing the drain electrode 96, the data pad 94, and the conductive pattern 98 for the storage capacitor, and also has a gate pad (along with the gate insulating film 60). 54 has a contact hole 102 exposing it. In this case, the passivation layer 100 around the gate pad 54 and the data pad 94 exposed through the contact holes 102 and 103 may be thinner than the passivation layer 100 in other portions except the pads 54 and 94. Formed. As a result, sufficient pressure may be applied to the conductive particles of the anisotropic conductive film as in the first embodiment, thereby enhancing adhesion between the pads 54 and 94 and the driving integrated circuit. In addition, although not shown, a plurality of contact holes in which the pad is exposed may be formed in the passivation layer 100 as in the second embodiment of the present invention.

A pixel electrode 112 is formed on the passivation layer 100 to receive an image signal from the thin film transistor and generate an electric field together with the electrode of the upper plate. The pixel electrode 112 is made of a transparent conductive material such as indium tin oxide (ITO) or indium zinc oxide (IZO), and is physically and electrically connected to the drain electrode 96 through the contact hole 101 to receive an image signal. I receive it. The pixel electrode 112 also overlaps the neighboring gate line 52 and the data line 92 to increase the aperture ratio, but may not overlap. The pixel electrode 112 is also connected to the conductive capacitor conductor 98 for the storage capacitor through the contact hole 104 to transmit an image signal to the conductor pattern 98. On the other hand, an auxiliary gate pad 114 and an auxiliary data pad 116 connected to the gate pad 54 and the data pad 94 through the contact holes 102 and 103, respectively, are formed. , 94) and to protect the pads and complementary the adhesion of the external circuit device, and their application is optional.

Next, a method of manufacturing a thin film transistor substrate for a liquid crystal display device having the structure of FIGS. 12 to 14 using four masks will be described in detail with reference to FIGS. 12 to 14 and FIGS. 15A to 22C. .

First, as shown in FIGS. 15A to 15C, the black matrix 22, the color filters 31, 32, and 33, and the organic insulating layer 40 are sequentially formed on the substrate 10 as in the first embodiment. .

16A through 16C, gate wirings 52, 54, and 56 are formed on the formed organic insulating layer 40 by a photolithography process using a mask.

17A and 17B, the gate insulating film 60, the semiconductor layer 70, and the intermediate layer 80 are respectively 1,500 mV to 5,000 mV, 500 mV to 2,000 mV, 300 mV using chemical vapor deposition. Successively deposited to a thickness of 600 to 600 kPa, and then depositing a conductor layer 90 such as metal to a thickness of 1,500 kPa to 3,000 kPa by sputtering or the like, and then depositing the photoresist film 130 thereon at a thickness of 1 m to 2 m. Apply with

Thereafter, the photoresist layer 130 is irradiated with light through a second mask and then developed to form photoresist patterns 132 and 134 as shown in FIGS. 18B and 18C. In this case, among the photoresist patterns 132 and 134, the channel portion C of the thin film transistor, that is, the first portion 134 positioned between the source electrode 95 and the drain electrode 96, is the data wiring portion A, that is, the data. The thickness of the wirings 92, 94, 95, 96, and 98 is smaller than that of the second portion 132 located at the portion where the wirings 92, 94, 95, 96, and 98 are to be formed, and all the photoresist of the other portion B is removed. At this time, the ratio of the thickness of the photoresist film 134 remaining in the channel portion C to the thickness of the photoresist film 132 remaining in the data wiring portion A should be different depending on the process conditions in an etching process which will be described later. It is preferable that the thickness of the first portion 134 be 1/2 or less of the thickness of the second portion 132, for example, 4,000 kPa or less.

As such, there may be various methods of varying the thickness of the photoresist layer according to the position. In order to control the light transmittance in the A region, a slit or lattice-shaped pattern is mainly formed or a translucent film is used.

In this case, the line width of the pattern located between the slits, or the interval between the patterns, that is, the width of the slits, is preferably smaller than the resolution of the exposure apparatus used for exposure. A thin film having a thickness or a thin film may be used.

When the light is irradiated to the photosensitive film through such a mask, the polymers are completely decomposed at the part directly exposed to the light, and the polymers are not completely decomposed because the amount of light is small at the part where the slit pattern or the translucent film is formed. In the area covered by, the polymer is hardly decomposed. Subsequently, when the photoresist film is developed, only a portion where the polymer molecules are not decomposed is left, and a thin photoresist film may be left at a portion where the light is not irradiated at a portion less irradiated with light. In this case, if the exposure time is extended, all molecules are decomposed, so it should not be so.

This thin film 134 is exposed to a conventional mask that is divided into a part that can completely transmit light and a part that can not completely transmit light, using a photoresist film made of a reflowable material, and then developed and rippled. It can also be formed by letting a part of the photosensitive film flow to the part which does not remain by making it low.

Subsequently, etching is performed on the photoresist pattern 134 and the underlying layers, that is, the conductor layer 90, the intermediate layer 80, and the semiconductor layer 70. At this time, the data line and the lower layer of the data line remain in the data wiring portion A, only the semiconductor layer should remain in the channel portion C, and the upper three layers 90, 80, 70 must be removed to expose the gate insulating film 30.

First, as shown in FIGS. 19A and 19B, the exposed conductor layer 90 of the other portion B is removed to expose the underlying intermediate layer 80. In this process, either a dry etching method or a wet etching method may be used. In this case, the conductor layer 90 may be etched and the photoresist patterns 132 and 134 may be hardly etched. However, in the case of dry etching, it is difficult to find a condition in which only the conductor layer 90 is etched and the photoresist patterns 132 and 134 are not etched, so that the photoresist patterns 132 and 134 may also be etched together. In this case, the thickness of the first portion 134 is thicker than that of the wet etching so that the first portion 134 is removed in this process so that the lower conductive layer 90 is not exposed.

When the conductor layer 90 is any one of Mo or MoW alloy, Al or Al alloy, and Ta, either dry etching or wet etching can be used. However, since Cr is not easily removed by a dry etching method, only wet etching may be used if the conductor layer 90 is Cr. In the case of wet etching in which the conductor layer 90 is Cr, CeNHO ₃ may be used as an etchant. In the case of dry etching in which the conductor layer 90 is Mo or MoW, the mixed gas or CF of CF ₄ and HCl may be used as the etching gas. A mixed gas of ₄ and O ₂ can be used, and in the latter case, the etching ratio to the photoresist film is almost the same.

In this way, as shown in Figs. 19A and 19B, only the conductor layers of the channel portion C and the data wiring portion B, that is, the conductor pattern 97 for the source / drain and the conductor pattern 98 for the storage capacitor, are shown. All of the conductor layer 90 of the remaining portion B is removed, revealing the underlying intermediate layer 80. The remaining conductor patterns 97 and 98 have the same shape as the data lines 92, 94, 95, 96, and 98 except that the source and drain electrodes 95 and 96 are connected without being separated. In addition, when dry etching is used, the photoresist patterns 132 and 134 are also etched to a certain thickness.

Then, as shown in FIGS. 20A and 20B, the exposed intermediate layer 80 of the other portion B and the semiconductor layer 70 underneath thereof are simultaneously removed together with the first portion 134 of the photosensitive film by a dry etching method. do. At this time, etching is performed under the condition that the photoresist patterns 132 and 134, the intermediate layer 80, and the semiconductor layer 70 (the semiconductor layer and the intermediate layer have almost no etching selectivity) are simultaneously etched and the gate insulating layer 60 is not etched. In particular, it is preferable to etch under conditions in which the etch ratios of the photoresist patterns 132 and 134 and the semiconductor layer 70 are almost the same. For example, using a mixed gas of SF ₆ and HCl or a mixed gas of SF ₆ and O ₂ allows the two films to be etched to about the same thickness. When the etch ratios of the photoresist patterns 132 and 134 and the semiconductor layer 70 are the same, the thickness of the first portion 134 should be equal to or smaller than the sum of the thicknesses of the semiconductor layer 70 and the intermediate layer 70.

In this way, as shown in FIGS. 20A and 20B, the first portion 134 of the channel portion C is removed to reveal the source / drain conductor pattern 97 and the intermediate layer 80 of the other portion B. And the semiconductor layer 70 is removed to expose the lower gate insulating layer 60. On the other hand, since the second portion 132 of the data line portion A is also etched, the thickness becomes thin. In this step, the semiconductor patterns 72 and 78 are completed. Reference numerals 87 and 88 denote intermediate layer patterns under the source / drain conductor patterns 97 and intermediate layer patterns under the storage capacitor conductor patterns 98, respectively.

Subsequently, ashing of the photoresist film remaining on the surface of the source / drain conductor pattern 97 of the channel part C is removed.

Next, as illustrated in FIGS. 21A and 21B, the source / drain conductor pattern 97 of the channel portion C and the source / drain interlayer pattern 87 below are etched and removed. In this case, the etching may be performed only by dry etching with respect to both the source / drain conductor pattern 97 and the intermediate layer pattern 87, and the source / drain conductor pattern 97 may be wet-etched, and the intermediate layer pattern ( 87 may be performed by dry etching. In the former case, it is preferable to perform etching under a condition in which the etching selectivity of the source / drain conductor pattern 97 and the interlayer pattern 87 is large, which is difficult to find the etching end point when the etching selectivity is not large. This is because it is not easy to adjust the thickness of the semiconductor pattern 72 remaining in (). For example, etching of the source / drain conductor pattern 97 is carried out using a mixed gas of SF ₆ and O ₂ . In the latter case of alternating between wet etching and dry etching, the side surface of the wet-etched source / drain conductor pattern 97 is etched, but the dry layer-etched intermediate layer pattern 87 is hardly etched, thus making a step shape. Examples of the etching gas used to etch the intermediate layer pattern 87 and the semiconductor pattern 72 include the aforementioned mixed gas of CF ₄ and HCl or mixed gas of CF ₄ and O _2. CF ₄ and O _{Using 2} may leave the semiconductor pattern 72 in a uniform thickness. At this time, as shown in FIG. 21B, a portion of the semiconductor pattern 72 may be removed to reduce the thickness, and the second portion 132 of the photoresist pattern may also be etched to a certain thickness at this time. At this time, the etching must be performed under the condition that the gate insulating film 60 is not etched, and the photoresist film is not exposed so that the second portion 132 is etched so that the data lines 92, 94, 95, 96, and 98 underneath are not exposed. It is a matter of course that the pattern is thick.

In this way, the source electrode 95 and the drain electrode 96 are separated, thereby completing the data wirings 92, 94, 95, 96, and 98 and the contact layer patterns 85, 86, and 88 thereunder.

Finally, the photosensitive film second portion 132 remaining in the data wiring portion A is removed. However, the removal of the second portion 132 may be made after removing the conductive portion 97 for the channel portion C source / drain and before removing the intermediate layer pattern 87 thereunder.

As mentioned earlier, wet and dry etching can be alternately used or only dry etching can be used. In the latter case, since only one type of etching is used, the process is relatively easy, but it is difficult to find a suitable etching condition. On the other hand, in the former case, the etching conditions are relatively easy to find, but the process is more cumbersome than the latter.

After the data wirings 92, 94, 95, 96, and 98 are formed in this manner, chemical vapor deposition of low dielectric constant insulating materials such as SiOC or SiOF having a low dielectric constant of 4.0 or less, as shown in FIGS. 22A to 22C, is performed. The protective film 100 is formed by laminating the same. Subsequently, the protective layer 100 is etched together with the gate insulating layer 60 by using a third mask to form the drain electrode 96, the gate pad 54, the data pad 94, and the conductive pattern 98 for the storage capacitor, respectively. The exposed contact holes 101, 102, 103, 104 are formed. In this case, as in the first embodiment of the present invention, the pads 54 and 94 are formed to have a thickness thinner than other portions. Alternatively, although not shown, a plurality of contact holes are formed in the protective film to expose the pads. By doing so, the adhesion between the pad and the drive integrated circuit can be enhanced.

Lastly, as shown in FIGS. 12 to 14, an ITO layer having a thickness of 400 μs to 500 μs is deposited and etched using a fourth mask to form the pixel electrode 112, the auxiliary gate pad 114, and the auxiliary data pad. 116 is formed.

In the second embodiment of the present invention, the data wirings 62, 64, 65, 66, and 68 and the contact layer patterns 55, 56, 58 and the semiconductor pattern 42 below the data wirings 62, 64, 65, 66, and 68, as well as the effects of the first embodiment. , 48) may be formed using one mask, and the source electrode 65 and the drain electrode 66 may be separated in this process to simplify the manufacturing process.

As described above, in the method of manufacturing a thin film transistor substrate for a liquid crystal display according to an exemplary embodiment of the present invention, a protective film around the pad is formed to have a thickness thinner than that of the other parts except the pad, or a plurality of contact holes are exposed in the protective film. The adhesion between the pad and the tab drive integrated circuit can be enhanced.

Claims (10)

Insulation board, A gate wiring formed on the substrate and including a gate line, a gate electrode, and a gate pad; A gate insulating film covering the gate wiring, A semiconductor pattern formed on the gate insulating film of the gate electrode; A data line formed on the semiconductor pattern or the gate insulating layer and including a data line, a source electrode, a drain electrode, and a data pad; A low dielectric constant insulating material covering the data line and the semiconductor pattern and having a low dielectric constant of 4.0 or less and formed by chemical vapor deposition, a first contact hole exposing the drain electrode and a second contact hole exposing the gate pad or the data pad. A protective film having a lower thickness than the other portions of the periphery of the second contact hole; A pixel electrode connected to the drain electrode exposed through the first contact hole Thin film transistor substrate for a liquid crystal display device comprising a. In claim 1, And a black matrix formed on the insulating substrate and having an opening in the pixel defined by the gate line and the data line, and a red, green, and blue color filter on the substrate. A gate wiring formed on an insulating substrate and including a gate line, a gate electrode, and a gate pad, A gate insulating film covering the gate wiring, A semiconductor pattern formed on the gate insulating film of the gate electrode; A data line formed on the semiconductor pattern or the gate insulating layer and including a data line, a source electrode, a drain electrode, and a data pad; A low dielectric constant insulating material covering the data line and the gate insulating film and having a low dielectric constant of 4.0 or less and formed by chemical vapor deposition, each of the gates exposing the first contact hole and the gate pad or the data pad to expose the drain electrode. A protective film having a pad and a second contact hole formed in at least two with respect to the data pad, A pixel electrode connected to the drain electrode exposed through the first contact hole Thin film transistor substrate for a liquid crystal display device comprising a. In claim 3, The second contact hole has a size of 5㎛ or less thin film transistor substrate for a liquid crystal display device. Forming a gate wiring including a gate line, a gate electrode, and a gate pad on the insulating substrate, Forming a gate insulating film covering the gate wiring; Forming a semiconductor pattern on the gate insulating layer of the gate electrode; Forming a data line including a data line, a source electrode, a drain electrode, and a data pad on the semiconductor pattern or the gate insulating layer; Forming a protective film on the data line and the semiconductor pattern by chemical vapor deposition on a low dielectric constant insulating material of 4.0 or less; Forming a passivation layer of the first portion around the gate pad or the data pad to have a thickness thinner than that of the second portion of the remaining portion except for the passivation layer of the first portion; Forming a pixel electrode connected to the drain electrode Method of manufacturing a thin film transistor substrate for a liquid crystal display device comprising a. In claim 5, In the forming of the passivation layer, the passivation layer of the first portion is formed by using a mask having a slit or lattice pattern for controlling the amount of light transmitted to a portion corresponding to the passivation layer of the first portion. Method for manufacturing a thin film transistor substrate for use. In claim 5, And forming a black matrix on the insulating substrate and forming a red, green, and blue color filter on the substrate before the gate wiring forming step. In claim 5, The semiconductor pattern and the data line are formed by a photolithography process using a single mask. Forming a gate wiring including a gate line, a gate electrode, and a gate pad on the insulating substrate, Forming a gate insulating film covering the gate wiring; Forming a semiconductor pattern on the gate insulating layer of the gate electrode; Forming a data line including a data line, a source electrode, a drain electrode, and a data pad on the semiconductor pattern or the gate insulating layer; Forming a protective film on the upper portion of the data line and the semiconductor pattern by chemical vapor deposition on a low dielectric constant insulating material of 4.0 or less on the upper portion; Patterning the passivation layer to form a plurality of first contact holes exposing the drain electrode and a plurality of second contact holes exposing each of the gate pads or the data pads and for each of the gate pads and the data pads; Forming a pixel electrode connected to the drain electrode exposed through the first contact hole Method of manufacturing a thin film transistor substrate for a liquid crystal display device comprising a. In claim 9, The size of the second contact hole is 5㎛ or less manufacturing method of a thin film transistor substrate for a liquid crystal display device.