KR20030029680A - Stacked chip package - Google Patents
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- KR20030029680A KR20030029680A KR1020010061422A KR20010061422A KR20030029680A KR 20030029680 A KR20030029680 A KR 20030029680A KR 1020010061422 A KR1020010061422 A KR 1020010061422A KR 20010061422 A KR20010061422 A KR 20010061422A KR 20030029680 A KR20030029680 A KR 20030029680A
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/12—Mountings, e.g. non-detachable insulating substrates
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/42—Wire connectors; Manufacturing methods related thereto
- H01L24/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L24/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
- H01L2224/321—Disposition
- H01L2224/32135—Disposition the layer connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
- H01L2224/32145—Disposition the layer connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being stacked
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
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- H—ELECTRICITY
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- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/484—Connecting portions
- H01L2224/48463—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond
- H01L2224/48465—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond the other connecting portion not on the bonding area being a wedge bond, i.e. ball-to-wedge, regular stitch
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- H—ELECTRICITY
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- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73251—Location after the connecting process on different surfaces
- H01L2224/73265—Layer and wire connectors
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L2224/85—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a wire connector
- H01L2224/85909—Post-treatment of the connector or wire bonding area
- H01L2224/8592—Applying permanent coating, e.g. protective coating
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/10—Details of semiconductor or other solid state devices to be connected
- H01L2924/1015—Shape
- H01L2924/10155—Shape being other than a cuboid
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/10—Details of semiconductor or other solid state devices to be connected
- H01L2924/1015—Shape
- H01L2924/10155—Shape being other than a cuboid
- H01L2924/10157—Shape being other than a cuboid at the active surface
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/153—Connection portion
- H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
- H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/181—Encapsulation
Abstract
Description
본 발명은 방법에 관한 것으로, 보다 상세하게는 다수의 반도체 칩이 적층된 구조를 가진 적층 칩 패키지 및 그의 제조방법에 관한 것이다.The present invention relates to a method, and more particularly, to a laminated chip package having a structure in which a plurality of semiconductor chips are stacked and a manufacturing method thereof.
전자기기들의 경박단소화 추세에 따라 그의 핵심 소자인 패키지의 고밀도, 고실장화가 중요한 요인으로 대두되고 있으며, 또한 컴퓨터의 경우 기억 용량의 증가에 따른 대용량의 램(Random Access Memory ; RAM) 및 프레쉬 메모리(Flash Memory)와 같이 칩의 크기는 자연적으로 증대되지만 패키지는 상기의 요건에 따라 소형화되는 경향으로 연구되고 있다.With the trend toward thinner and shorter electronic devices, high-density and high-mounted packages are becoming an important factor.In the case of computers, a large amount of random access memory (RAM) and fresh memory as the storage capacity increases. Like the Flash Memory, the size of the chip grows naturally, but the package is being studied to be smaller in accordance with the above requirements.
여기서, 패키지의 크기를 줄이기 위해서 제안되어 온 여러 가지 방안 예를 들면, 복수개의 칩 또는 패키지를 실장된 적층 칩 패키지(Multi Chip Package ; MCP), 적층 칩 모듈(Multi Chip Module ; MCM) 등이 있으며, 주로 반도체 칩 및 패키지가 기판 상에 평면적인 배열 방법으로 실장되기 때문에 제작에 한계가 있었다.Here, various methods that have been proposed to reduce the size of a package include, for example, a multi chip package (MCP) and a multi chip module (MCM) in which a plurality of chips or packages are mounted. In particular, there are limitations in manufacturing the semiconductor chip and the package because they are mounted in a planar arrangement method on the substrate.
이러한 한계를 극복하기 위해서 동일한 기억 용량의 칩을 일체적으로 복수개 적층한 패키지 기술이 제안된 바 있으며, 이것을 통상 적층 칩 패키지(stackedchip package)라 통칭된다.In order to overcome this limitation, a package technology in which a plurality of chips having the same storage capacity are integrally stacked has been proposed, which is commonly referred to as a stacked chip package.
현재 전술된 적층 칩 패키지의 기술은 단순화된 공정으로 적층 칩 패키지의 제조 단가를 낮출 수 있으며, 또한 대량 생산등의 이점이 있는 반면, 칩의 크기증가에 따른 패키지의 내부 리드를 설계하는데 있어서 공간이 부족한 단점이 있다.At present, the above-described stacked chip package technology can reduce the manufacturing cost of the stacked chip package in a simplified process, and also has advantages such as mass production. There is a shortcoming.
도 1은 종래 기술에 따른 적층 칩 패키지의 단면도이다.1 is a cross-sectional view of a stacked chip package according to the prior art.
종래 기술에 따른 적층 칩 패키지(100)는 도 1에 도시된 바와 같이, 기판 (110)을 이용하여 복수개의 반도체 칩(120,130,140)이 평면적으로 실장되어 패키징된 구조를 갖는다.As shown in FIG. 1, the stacked chip package 100 according to the related art has a structure in which a plurality of semiconductor chips 120, 130, and 140 are mounted in a planar manner using a substrate 110.
상기 각각의 반도체 칩(12,130,140)이 기판(110)의 상부면의 실장 영역에 접착제(114)에 의해 부착되어 있으며, 기판(110)에 부착된 면에 대하여 반대되는 면에 복수개의 본딩 패드(122,132,142)가 형성된 구조를 갖는다.Each of the semiconductor chips 12, 130, and 140 is attached to the mounting area of the upper surface of the substrate 110 by an adhesive 114, and a plurality of bonding pads 122, 132, and 142 are provided on the surface opposite to the surface attached to the substrate 110. ) Has a formed structure.
상기 본딩 패드(12,22,32)는 기판(110)의 상부면에 형성된 전도성 패턴(112)와 각각 대응되어 본딩 와이어(124,134,144)에 의해 전기적으로 연결된다.The bonding pads 12, 22, and 32 correspond to the conductive patterns 112 formed on the upper surface of the substrate 110, and are electrically connected to each other by the bonding wires 124, 134, and 144.
그리고, 반도체 칩(120,130,140) 및 기판(110) 상부면에 형성된 전기적 연결 부분을 보호하기 위하여 에폭시 계열의 봉지 수지를 봉지하여 패키지 몸체(150)가 형성된다.In addition, the package body 150 is formed by encapsulating an epoxy-based encapsulating resin in order to protect the electrical connection portions formed on the semiconductor chips 120, 130, 140 and the upper surface of the substrate 110.
상기 기판(110)의 전도성 패턴(112)은 반도체 칩(120,130,140)과 솔더 볼(160)을 전기적으로 연결시키기 위한 배선층이다.The conductive pattern 112 of the substrate 110 is a wiring layer for electrically connecting the semiconductor chips 120, 130, and 140 to the solder balls 160.
반도체 칩(120,130,140)은 기판(110) 상부면에 형성된 회로 패턴에 의해 서로 전기적으로 연결되거나, 전도성 패턴(112)에 반도체 칩의 본딩 패드(12,22,32)가 동시에 본딩 와이어(124,134,144)와 본딩됨으로써 전기적으로 연결될 수도 있다.The semiconductor chips 120, 130, and 140 are electrically connected to each other by a circuit pattern formed on the upper surface of the substrate 110, or the bonding pads 12, 22, and 32 of the semiconductor chip are simultaneously connected to the bonding wires 124, 134, and 144 on the conductive pattern 112. It may be electrically connected by bonding.
종래에는 각각의 반도체 칩에 프로빙(proving) 공정 등의 테스트 작업을 진행한 후에 패키징 공정이 진행된다. 그러나, 패키징공정 및 이후의 번인 테스트를 거치면서 발생되는 불량칩은 사전에 발견할 수 없으며, 이러한 불량칩으로 인한 제품의 손실이 컸었다.Conventionally, a packaging process is performed after a test operation such as a proving process is performed on each semiconductor chip. However, the defective chips generated during the packaging process and subsequent burn-in tests cannot be found in advance, and the loss of the products due to these defective chips was large.
또한, 종래에는 본딩와이어의 사용에 의해 본딩 공간이 많이 차지하게 되는 문제점이 있었다.In addition, there is a problem in that a bonding space takes up a lot by using a bonding wire.
이에 본 발명은 상기 종래의 문제점을 해결하기 위해 안출된 것으로, 좁은 본딩 공간에서도 패키징이 가능하고, 패키징 공정이 진행되기 전에 불량 칩 판별을 실시함으로써 불량칩으로 인한 손실을 줄일 수 있는 적층 칩 패키지 및 그의 제조방법을 제공함에 그 목적이 있다.Accordingly, the present invention has been made to solve the above-mentioned problems, and can be packaged even in a narrow bonding space, and the stacked chip package which can reduce the loss due to the bad chip by performing the bad chip discrimination before the packaging process proceeds. Its purpose is to provide a method for its manufacture.
도 1은 종래 기술에 따른 적층 칩 패키지의 단면도.1 is a cross-sectional view of a laminated chip package according to the prior art.
도 2는 본 발명의 제 1실시예에 따른 적층 칩 패키지의 평면도.2 is a plan view of a stacked chip package according to a first embodiment of the present invention.
도 3은 본 발명의 제 1실시예에 따른 적층 칩 패키지의 일부를 도시한 사시도.3 is a perspective view showing a part of a stacked chip package according to a first embodiment of the present invention.
도 4는 본 발명의 제 1실시예에 따른 적층 칩 패키지의 단면도.4 is a cross-sectional view of a stacked chip package according to a first embodiment of the present invention.
도 5a 내지 도 5f는 본 발명의 제 1실시예에 따른 적층 칩 패키지의 제조과정을 보인 공정단면도.5A through 5F are cross-sectional views illustrating a process of manufacturing a stacked chip package according to a first embodiment of the present invention.
도 6은 본 발명의 제 2실시예에 따른 적층 칩 패키지의 단면도.6 is a cross-sectional view of a stacked chip package according to a second embodiment of the present invention.
도 7은 본 발명의 제 3실시예에 따른 적층 칩 패키지의 단면도.7 is a cross-sectional view of a stacked chip package according to a third embodiment of the present invention.
도 8은 본 발명의 제 4실시예에 따른 적층 칩 패키지의 단면도.8 is a cross-sectional view of a stacked chip package according to a fourth embodiment of the present invention.
도 9a 내지 도 9b는 본 발명의 제 4실시예에 따른 적층 칩 패키지의 일부확대도.9A to 9B are partially enlarged views of a stacked chip package according to a fourth exemplary embodiment of the present invention.
도 10은 본 발명의 제 5실시예에 따른 적층 칩 패키지의 단면도.10 is a cross-sectional view of a stacked chip package according to a fifth embodiment of the present invention.
도 11은 본 발명의 제 6실시예에 따른 적층 칩 패키지의 단면도.11 is a cross-sectional view of a stacked chip package according to a sixth embodiment of the present invention.
도 12는 본 발명의 제 7실시예에 따른 적층 칩 패키지의 단면도.12 is a cross-sectional view of a stacked chip package according to a seventh embodiment of the present invention.
도면의 주요부분에 대한 부호의 설명Explanation of symbols for main parts of the drawings
20, 21, 22, 23. 요입홈 210, 212, 214, 216. 반도체 칩20, 21, 22, 23. Grooves 210, 212, 214, 216. Semiconductor chips
222. 볼랜드 224. 접착제222. Borland 224. Adhesives
240. 본딩와이어 226.도전패턴240. Bonding Wire 226. Conductive Pattern
250. 몰딩체 260. 솔더 볼250. Molded article 260. Solder ball
상기 목적을 달성하기 위한 본 발명의 적층 칩 패키지는 적층 구조를 가진 반도체 칩과, 반도체 칩의 일측 또는 타측에 형성되어, 칩패드와 연결되는 금속배선이 배열된 요입홈과,상면에는 반도체 칩이 부착된 인쇄회로기판과, 인쇄회로기판의 저면에 부착된 제 1도전패턴과, 요입홈의 금속배선과 인쇄회로기판을 연결시키는 제 2도전패턴과, 반도체 칩과 제 2도전패턴을 덮는 몰딩체를 포함한 것을 특징으로 한다.The laminated chip package of the present invention for achieving the above object is a semiconductor chip having a laminated structure, a recess groove formed on one side or the other side of the semiconductor chip, the metal wiring is connected to the chip pad is arranged, the semiconductor chip on the upper surface A printed circuit board to which the printed circuit board is attached, a first conductive pattern attached to the bottom surface of the printed circuit board, a second conductive pattern connecting the metal wiring of the recessed groove and the printed circuit board, and a semiconductor chip and the second conductive pattern Characterized by including.
이하, 본 발명의 바람직한 실시예를 첨부된 도면을 참조하여 상세히 설명하면 다음과 같다.Hereinafter, preferred embodiments of the present invention will be described in detail with reference to the accompanying drawings.
도 2는 본 발명의 제 1실시예에 따른 적층 칩 패키지의 평면도이고, 도 3은 본 발명의 제 1실시예에 따른 적층 칩 패키지의 일부를 도시한 사시도이다.2 is a plan view of a multilayer chip package according to a first embodiment of the present invention, and FIG. 3 is a perspective view showing a part of the multilayer chip package according to the first embodiment of the present invention.
또한, 도 4는 도 2의 Ⅰ-Ⅱ선을 따라 절단한 공정단면도이다.4 is a cross-sectional view taken along the line II of FIG. 2.
본 발명의 적층 칩 패키지는, 도 2 및 도 3에 도시된 바와 같이, 일측에 다수의 제 1요입홈(20)이 형성된 제 1반도체 칩(210)과 타측에 다수의 제 2요입홈(21)이 형성된 제 2반도체칩(212)이 열로 배열되며, 일측에 다수의 제 3요입홈(22)이 형성된 제 3반도체 칩(214), 타측에 다수의 제 4요입홈(23)이 형성된 제 4반도체칩(216)이 제 1반도체 칩(210)과 제 2반도체 칩(212)에 대하여 행으로 배열되어져 있다. 상기 요입홈(20)에는 다수의 칩패드(미도시)가 형성되어져 있다.As shown in FIGS. 2 and 3, the stacked chip package of the present invention includes a first semiconductor chip 210 having a plurality of first recessed grooves 20 formed at one side thereof and a plurality of second recessed grooves 21 at the other side thereof. ) Is formed of a second semiconductor chip 212 is arranged in a row, the third semiconductor chip 214 having a plurality of third recessed grooves 22 formed on one side, the fourth recessed grooves 23 formed on the other side Four semiconductor chips 216 are arranged in rows with respect to the first semiconductor chip 210 and the second semiconductor chip 212. A plurality of chip pads (not shown) are formed in the concave groove 20.
인쇄회로기판(Printed Circuit Board)(220)은, 도 2 및 도 4에 도시된 바와 같이, 상면에 접착제(224)에 의해 각각의 제 1, 제 2, 제 3 및 제 4반도체 칩(210)(212)(214)(216)이 부착되고, 하면에는 볼랜드(222)에 다수의 솔더 볼(260)이 부착되어 있다. 또한, 인쇄회로기판(220)의 상면 일측에는 도전패턴(226)이 형성되어져 있다.As shown in FIGS. 2 and 4, the printed circuit board 220 includes the first, second, third and fourth semiconductor chips 210 each having an adhesive 224 thereon. 212, 214, and 216 are attached, and a plurality of solder balls 260 are attached to the ball land 222 on the bottom surface. In addition, a conductive pattern 226 is formed on one side of the upper surface of the printed circuit board 220.
상기 도전패턴(226)은 각각의 본딩와이어(240)에 의해 반도체 칩의 제 1, 제 2, 제 3 및 제 4요입홈(20)(21(22)(23)의 칩패드와 전기적으로 연결된다.The conductive pattern 226 is electrically connected to the chip pads of the first, second, third and fourth recessed grooves 20, 21, 22, and 23 of the semiconductor chip by respective bonding wires 240. do.
상기 반도체 칩(210)(212)(214)(216)과 본딩와이어(240)는 몰딩체(250)로 덮여져 있다.The semiconductor chips 210, 212, 214, and 216 and the bonding wire 240 are covered with a molding 250.
도 5a 내지 도 5f는 본 발명의 제 1실시예에 따른 적층 칩 패키지의 제조과정을 보인 공정단면도로, 도 5a 내지 도 5c에서는 편의상 반도체 칩 중 제 4반도체 칩의 공정단면도 만을 도시한 것이다.5A through 5F are cross-sectional views illustrating a process of manufacturing a stacked chip package according to a first exemplary embodiment of the present invention. FIGS. 5A through 5C illustrate only process cross-sectional views of fourth semiconductor chips of semiconductor chips for convenience.
상기 구성을 가진 본 발명의 제 1실시예에 따른 적층 칩 패키지의 제조방법은, 도 5a에 도시된 바와 같이, 먼저 기판(10) 전면에 제 1절연막(14)을 증착하고, 상기 제 1절연막(14)을 식각하여 칩패드(12)를 노출시키는 개구부(15)를 형성한다.In the method of manufacturing a multilayer chip package according to the first embodiment of the present invention having the above structure, as shown in FIG. 5A, first, a first insulating layer 14 is deposited on the entire surface of the substrate 10, and the first insulating layer is formed. The 14 is etched to form the openings 15 exposing the chip pads 12.
이어서, 도 5b에 도시된 바와 같이, 제 1절연막(14) 상에 스퍼터링 방법에 의해 금속층을 증착한 후, 상기 금속층을 식각하여 개구부(15)를 덮는 금속배선(16)을 형성한다. 이때, 상기 금속배선(16)은 구리, 니켈, 구리 및 니켈과의 화합물 또는 복합 다층 구조를 가진다.Subsequently, as illustrated in FIG. 5B, after depositing a metal layer on the first insulating layer 14 by a sputtering method, the metal layer is etched to form a metal wiring 16 covering the opening 15. At this time, the metal wiring 16 has a compound or a composite multilayer structure with copper, nickel, copper and nickel.
그 다음, 도 5c에 도시된 바와 같이, 상기 결과의 기판에 에폭시수지 또는 폴리이미드 계열의 수지를 이용하여 5㎛ 두께의 제 2절연막(18)을 증착한 후, 상기 제 2절연막의 일부위를 식각하여 요입홈(23)을 형성하여 도 3에 도시된 바와 같은 반도체 칩 제조 공정을 완료한다.Subsequently, as shown in FIG. 5C, a second insulating film 18 having a thickness of 5 μm is deposited on the resultant substrate using an epoxy resin or a polyimide resin, and then a part of the second insulating film is deposited. The etching process forms the recessed grooves 23 to complete the semiconductor chip manufacturing process as shown in FIG. 3.
이 후, 도 5d에 도시된 바와 같이, 상기 결과의 반도체 칩을 테스트용 소켓(270) 내에 장착한 후, 번인 테스트(burn in test)를 실시함으로써 불량칩의 여부를 확인한다.Thereafter, as shown in FIG. 5D, the resultant semiconductor chip is mounted in the test socket 270, and then burn in test is performed to check whether the defective chip is present.
상기 테스트용 소켓(270)은 저면에 다수의 시그널 탐침핀(274)이 형성되고 반도체 칩이 삽입되는 내부 공간의 내측면에는 각각의 요입홈 상의 금속배선과 연결되는 다수의 콘택핀(216)이 형성되어 있다.The test socket 270 has a plurality of signal probe pins 274 formed on a bottom surface thereof, and a plurality of contact pins 216 connected to metal wires on respective recessed grooves on an inner surface of an inner space into which a semiconductor chip is inserted. Formed.
상기 콘택핀(216)은 탄성을 가지는 고리 또는 스프링 형상으로, 금속배선과 기계적인 탄성력에 의해 전기적 접촉을 할 수 있는 구조를 가진다.The contact pin 216 has an elastic ring or spring shape, and has a structure capable of electrical contact with the metal wiring by a mechanical elastic force.
이어서, 도 5e에 도시된 바와 같이, 상기 테스트를 통해 선별된 양질의 반도체 칩(214)(216)을 접착제(224)에 의해 인쇄회로기판(220)에 부착시킨다.Subsequently, as illustrated in FIG. 5E, the high quality semiconductor chips 214 and 216 selected through the test are attached to the printed circuit board 220 by the adhesive 224.
그 다음, 인쇄회로기판(220)의 도전패턴(226)과 각각의 요입홈(22)(23) 상의 금속배선을 본딩와이어(240)에 의해 본딩시킨다.Next, the conductive pattern 226 of the printed circuit board 220 and the metal wirings on the respective recessed grooves 22 and 23 are bonded by the bonding wire 240.
이 후, 도 5f에 도시된 바와 같이, 에폭시수지 등의 몰딩물질을 이용하여 반도체 칩(214)(216)과 본딩와이어(240)를 덮는 몰딩체(250)을 형성한다.Thereafter, as illustrated in FIG. 5F, a molding member 250 covering the semiconductor chips 214 and 216 and the bonding wire 240 is formed using a molding material such as an epoxy resin.
이어서, 인쇄회로기판(220)의 본딩패드(222)에 솔더 볼(260)을 부착시키어 접층 칩 패키지 제조를 완료한다.Subsequently, the solder balls 260 are attached to the bonding pads 222 of the printed circuit board 220 to complete the manufacturing of the contact chip package.
도 6은 본 발명의 제 2실시예에 따른 적층 칩 패키지의 단면도이다.6 is a cross-sectional view of a stacked chip package according to a second embodiment of the present invention.
본 발명의 제 2실시예는, 도 6에 도시된 바와 같이, 본 발명의 제 1실시예와 동일 방법으로 패키징 공정이 진행되나, 본 발명의 제 1실시예의 솔더 볼 대신 도전핀(282)을 사용한다.In the second embodiment of the present invention, as shown in FIG. 6, the packaging process is performed in the same manner as the first embodiment of the present invention, but instead of the solder ball of the first embodiment of the present invention, the conductive pin 282 is used. use.
도 7은 본 발명의 제 3실시예에 따른 적층 칩 패키지의 단면도이다.7 is a cross-sectional view of a stacked chip package according to a third embodiment of the present invention.
본 발명의 제 3실시예는, 도 7에 도시된 바와 같이, 본 발명의 제 1 및 제 2실시예에서의 본딩와이어 대신 콘택핀(292)을 사용하여 적층 칩 패키지 제조 공정이 진행된다. 이때, 상기 콘택핀(292)은 반도체 칩(214)(216)의 요입홈(22)(23) 상의 금속배선과 전기적으로 연결된다.In the third embodiment of the present invention, as shown in FIG. 7, the manufacturing process of the stacked chip package is performed by using the contact pins 292 instead of the bonding wires in the first and second embodiments of the present invention. In this case, the contact pins 292 are electrically connected to the metal wires on the recesses 22 and 23 of the semiconductor chips 214 and 216.
또한, 기판(290)은 테스트용 소켓으로 사용 가능하며, 상기 기판 하부에는도전핀(298)이 형성된다.In addition, the substrate 290 may be used as a test socket, and a conductive pin 298 is formed under the substrate.
도 8은 본 발명의 제 4실시예에 따른 적층 칩 패키지의 단면도이다.8 is a cross-sectional view of a stacked chip package according to a fourth embodiment of the present invention.
본 발명의 제 4실시예는, 도 8에 도시된 바와 같이, 본 발명의 제 3실시예와 동일 방법으로 패키지 제조 공정이 진행되나, 본 발명의 제 3실시예의 연결핀 대신 솔더 볼(306)이 이용된다.In the fourth embodiment of the present invention, as shown in Figure 8, the package manufacturing process proceeds in the same manner as the third embodiment of the present invention, the solder ball 306 instead of the connecting pin of the third embodiment of the present invention This is used.
상기 연결핀(302)은 도전성 핀(302b)과, 상기 도전성 핀(302b)에 도금처리된 도금층(302a)으로 이루어진다. 이때, 상기 도금층(302a)으로는 솔더(solder)가 이용된다.The connection pin 302 includes a conductive pin 302b and a plating layer 302a plated on the conductive pin 302b. In this case, a solder is used as the plating layer 302a.
도 9a 내지 도 9b는 본 발명의 제 4실시예에 따른 적층 칩 패키지의 일부확대도이다.9A to 9B are partially enlarged views of a stacked chip package according to a fourth exemplary embodiment of the present invention.
연결핀(302)을 금속배선에 부착시키는 과정을 알아보면, 먼저 상기 구성된 연결핀(302)과 반도체 칩(214)의 금속배선(22)과 접촉시킨 후, 도 9a에 도시된 바와 같이, 적외선램프(도시되지 않음) 등을 이용하여 리플로우(reflow)공정을 진행시킴으로써, 도 9b에 도시된 바와 같이, 도금층(302b)이 용융되어 연결핀(302)이 요입홈의 금속배선에 접합된다.Referring to the process of attaching the connecting pin 302 to the metal wiring, first contacting the configured connecting pin 302 and the metal wiring 22 of the semiconductor chip 214, as shown in Figure 9a, infrared By performing a reflow process using a lamp (not shown) or the like, as shown in FIG. 9B, the plating layer 302b is melted and the connecting pin 302 is joined to the metal wiring of the recessed groove.
도 10은 본 발명의 제 5실시예에 따른 적층 칩 패키지의 단면도이다.10 is a cross-sectional view of a stacked chip package according to a fifth embodiment of the present invention.
본 발명의 제 5실시예의 반도체 칩은, 도 10에 도시된 바와 같이, 일측에 다수의 제 1요입홈(40)이 형성된 제 1반도체 칩(410)과 타측에 다수의 제 2요입홈(41)이 형성된 제 2반도체칩(412)이 열로 배열되며, 일측에 다수의 제 3요입홈(42)이 형성된 제 3반도체 칩(414)과 타측에 다수의 제 4요입홈(43)이 형성된 제4반도체칩(416)이 제 1반도체 칩(410)과 제 2반도체 칩(412)에 각각 적층된 구조를 가진다.In the semiconductor chip of the fifth embodiment of the present invention, as shown in FIG. 10, a first semiconductor chip 410 having a plurality of first recessed grooves 40 formed on one side and a plurality of second recessed grooves 41 on the other side thereof. ) Is formed of a second semiconductor chip 412 is arranged in a row, a third semiconductor chip 414 having a plurality of third recessed grooves 42 formed on one side and a plurality of fourth recessed grooves 43 formed on the other side. Four semiconductor chips 416 are stacked on the first semiconductor chip 410 and the second semiconductor chip 412, respectively.
즉, 제 1반도체 칩(410)의 제 1요입홈(40)과 제 3반도체 칩(414)의 제 3요입홈(42)이 각각 대응되고, 제 2반도체 칩(412)의 제 2요입홈(41)과 제 4반도체 칩(416)의 제 4요입홈(43)이 각각 대응된 위치에 있다.That is, the first recessed grooves 40 of the first semiconductor chip 410 and the third recessed grooves 42 of the third semiconductor chip 414 correspond to each other, and the second recessed grooves of the second semiconductor chip 412 correspond to each other. The 41 and the fourth recessed grooves 43 of the fourth semiconductor chip 416 are respectively in corresponding positions.
인쇄회로기판(420)은 상면에는 접착제(424)에 의해 제 1반도체 칩(410)과 제 2반도체 칩(412)가 부착되며, 또한 접착제(424)에 의해 제 1반도체 칩(410)과 제 3반도체 칩(414)이 부착되고 제 2반도체 칩(214)와 제 4반도체 칩(416)이 부착된다.The first semiconductor chip 410 and the second semiconductor chip 412 are attached to the printed circuit board 420 by an adhesive 424 on the upper surface, and the first semiconductor chip 410 and the first semiconductor chip 410 are attached to the printed circuit board 420 by an adhesive 424. The third semiconductor chip 414 is attached, and the second semiconductor chip 214 and the fourth semiconductor chip 416 are attached.
상기 구성된 본 발명의 제 5실시예에 따른 반도체 칩(410)(412)(414)(416)은 본딩와이어(430) 및 도전물질층(440)에 의해 기판(420) 상의 도전패턴(426)과 연결된다. 이때, 상기 기판(420) 하면의 본딩패드(422)에는 솔더 볼(460)이 부착되어 있다.The semiconductor chips 410, 412, 414, and 416 according to the fifth embodiment of the present invention configured as described above are electrically conductive patterns 426 on the substrate 420 by the bonding wires 430 and the conductive material layer 440. Connected with In this case, a solder ball 460 is attached to the bonding pad 422 on the lower surface of the substrate 420.
상기 반도체 칩(410)(412)(414)(416)과 본딩와이어(430)는 몰딩체(450)로 덮여져 있다.The semiconductor chips 410, 412, 414, and 416 and the bonding wire 430 are covered with a molding member 450.
도 11은 본 발명의 제 6실시예에 따른 적층 칩 패키지의 단면도이다.11 is a cross-sectional view of a stacked chip package according to a sixth embodiment of the present invention.
본 발명의 제 6실시예는, 도 11에 도시된 바와 같이, 제 5실시예에서 몰딩체의 형상이 변형된 것이다.In the sixth embodiment of the present invention, as shown in FIG. 11, the shape of the molding body is modified in the fifth embodiment.
본 발명의 제 실시예에 따른 몰딩체(550)는 제 1, 제 2, 제 3 및 제 4반도체 칩(510)(512)(514)(516)과 본딩와이어(530)를 덮고 제 3반도체 칩(514)과 제 4반도체 칩(516)의 일면이 노출된 형상을 가진다. 상기 반도체 칩의 노출된 부위에방열판(도시되지 않음)이 장착된다.The molding body 550 according to the embodiment of the present invention covers the first, second, third, and fourth semiconductor chips 510, 512, 514, 516, and the bonding wire 530, and the third semiconductor. One surface of the chip 514 and the fourth semiconductor chip 516 may be exposed. A heat sink (not shown) is mounted on the exposed portion of the semiconductor chip.
도 12는 본 발명의 제 7실시예에 따른 적층 칩 패키지의 단면도이다.12 is a cross-sectional view of a stacked chip package according to a seventh embodiment of the present invention.
본 발명의 제 7실시예는, 도 12에 도시된 바와 같이, 제 5실시예에서 적층된 반도체 칩의 형상이 변형된 것이다.In the seventh embodiment of the present invention, as shown in Fig. 12, the shape of the semiconductor chips stacked in the fifth embodiment is modified.
본 발명의 제 7실시예에 따른 반도체 칩은, 도 12에 도시된 바와 같이, 일측에 다수의 제 1요입홈(60)이 형성된 제 1반도체 칩(610)과 타측에 다수의 제 2요입홈(61)이 형성된 제 2반도체칩(612)이 열로 배열되며, 일측에 다수의 제 3요입홈(62)이 형성되고 제 1반도체 칩의 크기보다 작은 제 3반도체 칩(614)과 타측에 다수의 제 4요입홈(63)이 형성되고 제 2반도체 칩의 크기보다 작은 제 4반도체칩(616)이 제 1반도체 칩(610)과 제 2반도체 칩(612)에 각각 적층된 구조를 가진다. 상기 제 1반도체 칩과 제 3반도체 칩의 측면과 상기 제 2반도체 칩과 제 4반도체 칩의 측면은 계단형상을 이룬다.In the semiconductor chip according to the seventh exemplary embodiment of the present invention, as shown in FIG. 12, a first semiconductor chip 610 having a plurality of first recessed grooves 60 formed on one side thereof and a plurality of second recessed grooves on the other side thereof is shown. The second semiconductor chip 612 having the 61 is arranged in a row, and the third semiconductor chip 614 is formed on one side and the third semiconductor chip 614 is smaller than the size of the first semiconductor chip and the other on the other side. The fourth recessed groove 63 is formed and the fourth semiconductor chip 616, which is smaller than the size of the second semiconductor chip, is stacked on the first semiconductor chip 610 and the second semiconductor chip 612, respectively. Side surfaces of the first semiconductor chip and the third semiconductor chip and side surfaces of the second semiconductor chip and the fourth semiconductor chip form a step shape.
또한, 제 1본딩와이어(670)에 의해 제 1반도체 칩(610)의 금속배선과 도전패턴(626)이 연결되고, 제 2본딩와이어(672)에 의해 제 2반도체 칩(612)의 금속배선과 도전패턴(626)이 연결된다.In addition, the metal wiring of the first semiconductor chip 610 and the conductive pattern 626 are connected by the first bonding wire 670, and the metal wiring of the second semiconductor chip 612 is connected by the second bonding wire 672. And the conductive pattern 626 are connected.
그리고, 제 3본딩와이어(674)에 의해 제 3 반도체 칩(614)의 금속배선과 제 1반도체 칩(610)의 금속배선이 연결되고, 제 4본딩와이어(676)에 의해 제 4반도체 칩(616)의 금속배선과 제 2반도체 칩(612)의 금속배선이 연결된다.In addition, the metal wiring of the third semiconductor chip 614 and the metal wiring of the first semiconductor chip 610 are connected by the third bonding wire 674, and the fourth semiconductor chip 676 is connected by the fourth bonding wire 676. The metal wire of 616 and the metal wire of the second semiconductor chip 612 are connected.
이상에서와 같이, 본 발명에서는 반도체 칩의 적층 구조를 통해 반도체 칩의집적도를 향상시킬 수 있다.As described above, in the present invention, the integration degree of the semiconductor chip can be improved through the stacked structure of the semiconductor chip.
또한, 본 발명에서는 불량 칩 판별을 실시한 후 패키징 공정이 수반되므로, 불량 칩에 의한 제품의 손실을 막을 수 있다.In addition, in the present invention, since the packaging process is performed after the determination of the defective chip, loss of the product due to the defective chip can be prevented.
그리고 반도체 칩의 요입홈을 이용하여 좁은 공간에서도 본딩이 가능하다.In addition, bonding is possible in a narrow space by using the recess of the semiconductor chip.
기타, 본 발명은 그 요지를 일탈하지 않는 범위에서 다양하게 변경하여 실시할 수 있다.In addition, this invention can be implemented in various changes within the range which does not deviate from the summary.
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| KR10-2001-0061422A KR100470387B1 (en) | 2001-10-05 | 2001-10-05 | stacked chip package |
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Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US7847419B2 (en) | 2007-08-20 | 2010-12-07 | Hynix Semiconductor Inc. | Semiconductor package with pad parts electrically connected to bonding pads through re-distribution layers |
| US8604615B2 (en) | 2011-01-28 | 2013-12-10 | Samsung Electronics Co., Ltd. | Semiconductor device including a stack of semiconductor chips, underfill material and molding material |
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| Publication number | Priority date | Publication date | Assignee | Title |
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| US5323060A (en) * | 1993-06-02 | 1994-06-21 | Micron Semiconductor, Inc. | Multichip module having a stacked chip arrangement |
| JP3943165B2 (en) * | 1996-07-26 | 2007-07-11 | ハネウェル・インターナショナル・インコーポレーテッド | Placement of chip stack and capacitor mounting |
| KR100533761B1 (en) * | 1999-04-14 | 2005-12-06 | 앰코 테크놀로지 코리아 주식회사 | semi-conduSSor package |
| JP2001257307A (en) * | 2000-03-09 | 2001-09-21 | Sharp Corp | Semiconductor device |
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US7847419B2 (en) | 2007-08-20 | 2010-12-07 | Hynix Semiconductor Inc. | Semiconductor package with pad parts electrically connected to bonding pads through re-distribution layers |
| US8178975B2 (en) | 2007-08-20 | 2012-05-15 | Hynix Semiconductor Inc. | Semiconductor package with pad parts electrically connected to bonding pads through re-distribution layers |
| US8604615B2 (en) | 2011-01-28 | 2013-12-10 | Samsung Electronics Co., Ltd. | Semiconductor device including a stack of semiconductor chips, underfill material and molding material |
| US9343432B2 (en) | 2011-01-28 | 2016-05-17 | Samsung Electronics Co., Ltd. | Semiconductor chip stack having improved encapsulation |
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