KR20030002726A - Method of manufacturing semiconductor device - Google Patents

Abstract

PURPOSE: A method for manufacturing a semiconductor device is provided to enlarge the area of a capacitor by forming a concave and convex structure on an upper area of a junction region. CONSTITUTION: A channel region and a capacitor region are defined by forming an isolation layer(22) at a semiconductor substrate(21). A junction region(23) is then formed on the substrate(21) of the capacitor region. A concave and convex region is formed by selectively etching the upper surface of the junction region(23). After forming a channel oxide layer(24) on the resultant structure, the channel oxide layer(24) located on a tunnel region is selectively removed. Then, a tunnel oxide layer(25) is formed between the substrate(21) and the channel oxide layer(24). A gate electrode(26a) is formed on the entire surface of the resultant structure, thereby forming a transistor and a capacitor.

Description

Method of manufacturing semiconductor device

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a semiconductor device, and more particularly, to a method for manufacturing a semiconductor device capable of improving program characteristics within the same area in a single poly nonvolatile memory.

A single poly electrically erasable programmable read only memory (EEPROM) cell is a non-volatile memory cell that uses a single layer of poly, unlike a stack gate EEPROM using two polys.

A typical, single poly EEPROM is described in detail with reference to FIGS. 1, 2A and 2B as follows.

1 is a plan view of a memory cell, FIG. 2A is a cross-sectional view taken along the line A1-A1 of FIG. 1, and FIG. 2B is a cross-sectional view taken along the line A2-A2 of FIG.

1, 2A, and 2B, a semiconductor substrate 11 is provided, and an isolation layer 13 is formed in the semiconductor substrate 11 to define an active region 12. Subsequently, an impurity ion implantation process using an impurity ion implantation mask is performed to form a junction region 14 at a predetermined portion of the active region. Then, after the tunnel oxide film 15 and the polysilicon layer 16 are sequentially formed on the entire structure, an etching process using a gate mask is performed to move the polysilicon layer 16 and the tunnel oxide film 15 in one direction. By etching, the gate electrode 10 is formed. In this process, a channel region is formed in the tunnel oxide layer 15 between the polysilicon layer 16 and the active region 12, and a tunnel oxide layer between the polysilicon layer 16 and the junction region 14 is formed. A capacitor region is formed at 15, and a tunnel region is formed between the portion protruding downward of the polysilicon layer 16 and the tunnel oxide layer 15 between the junction region 14. Subsequently, a source / drain ion implantation process using a source / drain ion implantation mask is performed to form a source region 17 and a drain region 18 in the active region 12.

In the cell having the above structure, as the capacitor region is formed between the polysilicon layer 16 and the junction region 14, the capacitor region area is limited, thereby showing a limitation in increasing the capacitance of the capacitor. For this reason, the characteristics of the cell program cannot be improved when the cell is programmed. Therefore, there is an urgent need to develop new technologies that can increase the capacitor area within a limited area.

Accordingly, the present invention has been made to solve the above problems, by forming a junction region by performing an impurity ion implantation process on a semiconductor substrate, and then forming an uneven structure on the upper surface of the junction region by performing an etching process The purpose of the present invention is to increase the area of the capacitor region formed by a subsequent process, thereby improving the program characteristics within the same area.

1 is a plan view of a general semiconductor device.

FIG. 2A is a cross-sectional view of the semiconductor device taken along the line A1-A1 in FIG. 1. FIG.

FIG. 2B is a cross-sectional view of the semiconductor device taken along the line 'A2-A2' of FIG. 1.

3A to 3H are cross-sectional views of semiconductor devices in accordance with an embodiment of the present invention.

<Explanation of symbols for the main parts of the drawings>

11, 21: semiconductor substrate 12: active region

13, 22: isolation layer 14, 23: junction region

15, 25: tunnel oxide film 16, 26: polysilicon layer

10, 26a: gate electrode 17: source region

18 drain region 24 channel oxide film

The present invention includes forming a device isolation film on a semiconductor substrate to define a channel region and a capacitor region; Forming a junction region in the semiconductor substrate of the capacitor region; Etching the upper surface of the junction region to form an uneven structure; Forming a channel oxide film on the entire structure; Removing the channel oxide layer of the tunnel region included in the capacitor region; Forming a tunnel oxide film between the semiconductor substrate and the channel oxide film; And forming a polysilicon layer over the entire structure, then patterning, forming source and drain regions to form transistors and capacitors.

Hereinafter, with reference to the accompanying drawings will be described in detail the present invention.

3A to 3H are cross-sectional views illustrating manufacturing steps of a semiconductor device in accordance with an embodiment of the present invention.

Referring to FIG. 3A, a semiconductor substrate 21 is provided, and an isolation layer 22 is formed on the semiconductor substrate 21 to define an active region (not shown). Subsequently, after the photoresist is applied over the entire structure, an exposure process using a photo mask is performed to pattern the photoresist to be used as an impurity ion implantation mask. 100) is formed. Subsequently, an impurity ion implantation process using the first photoresist pattern 100 is performed to form a junction region 23 in the active region. Then, the first photoresist pattern 100 is removed by a predetermined stripping process.

Referring to FIGS. 3B and 3C, after the photoresist is applied over the entire structure, an exposure process using a predetermined photo mask is performed to pattern the photoresist that is applied to the portion where the capacitor region is to be formed in the subsequent process. The photoresist is patterned to form a second photoresist pattern 200 having an uneven structure. Subsequently, an etching process using the second photoresist pattern 200 as a mask is performed to etch the junction region 23, thereby forming an uneven structure on the upper surface of the junction region 23. Then, the second photoresist pattern 200 is removed by a predetermined stripping process.

3D to 3E, a channel oxide film 24 for forming a channel region is formed on the entire structure. The channel oxide film 24 is formed by growing through a thermal process, or is deposited by a deposition process. Subsequently, after the photoresist is applied over the entire structure, an exposure process using a predetermined photo mask is performed, and the third photoresist pattern 300 is patterned by patterning the photoresist so that only a portion where a tunnel region is to be formed in a subsequent process is opened. Is formed. Next, an etching process using the third photoresist pattern 300 as a mask is performed to etch the channel oxide layer 24 in the portion where the tunnel region is to be formed to expose a predetermined portion of the junction region 23. Then, the third photoresist pattern 300 is removed by a predetermined stripping process.

Referring to FIG. 3F, a tunnel oxide film 25 for forming a tunnel region between the semiconductor substrate 21 and the channel oxide film 24 is formed by performing a thermal oxidation process. Here, by growing the tunnel oxide layer 25 by thermal oxidation, a single layer of the tunnel oxide layer 25 is formed in the tunnel region, and the channel region and the capacitor region except for the tunnel region are formed of the tunnel oxide layer 25 and A laminated structure of the channel oxide film 24 is formed.

3G and 3H, after the polysilicon layer 26 is formed on the entire structure, the polysilicon layer 26 is etched by performing an etching process using a gate mask to separate devices. 26a is formed. Subsequently, a source / drain ion implantation process using a source / drain ion implantation mask is performed to form a source and a drain region (not shown) in the active region to form a transistor, and a capacitor in the capacitor region.

do. The subsequent process is the same as the general process and will be omitted.

According to the present invention, after the impurity ion implantation process is performed on a semiconductor substrate to form a junction region, an etching process is performed to form an uneven structure on the upper surface of the junction region, thereby increasing the area of the capacitor region formed by a subsequent process. It is possible to improve the program characteristics in the same area.

Claims (4)

Forming a device isolation layer on the semiconductor substrate to define a channel region and a capacitor region; Forming a junction region in the semiconductor substrate of the capacitor region; Etching the upper surface of the junction region to form an uneven structure; Forming a channel oxide film on the entire structure; Removing the channel oxide layer of the tunnel region included in the capacitor region; Forming a tunnel oxide film between the semiconductor substrate and the channel oxide film; And Forming a polysilicon layer over the entire structure, and then patterning and forming source and drain regions to form transistors and capacitors. The method of claim 1, The channel oxide film is a method of manufacturing a semiconductor device, characterized in that formed by growing in a thermal oxidation process. The method of claim 1, The tunnel oxide film is a method of manufacturing a semiconductor device, characterized in that formed by growing in a thermal oxidation process. The method of claim 1, The tunnel region is a semiconductor device manufacturing method, characterized in that formed by a single layer of the tunnel oxide film.