KR20040000888A - salicide layer forming method in semiconductor device - Google Patents
salicide layer forming method in semiconductor device Download PDFInfo
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- KR20040000888A KR20040000888A KR1020020035891A KR20020035891A KR20040000888A KR 20040000888 A KR20040000888 A KR 20040000888A KR 1020020035891 A KR1020020035891 A KR 1020020035891A KR 20020035891 A KR20020035891 A KR 20020035891A KR 20040000888 A KR20040000888 A KR 20040000888A
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- Prior art keywords
- salicide
- region
- film
- photoresist
- reaction prevention
- Prior art date
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- 238000000034 method Methods 0.000 title claims abstract description 33
- 239000004065 semiconductor Substances 0.000 title claims abstract description 22
- 230000008569 process Effects 0.000 claims abstract description 22
- 229910052751 metal Inorganic materials 0.000 claims abstract description 16
- 239000002184 metal Substances 0.000 claims abstract description 16
- 238000004519 manufacturing process Methods 0.000 claims abstract description 15
- 229920002120 photoresistant polymer Polymers 0.000 claims abstract description 14
- 230000000903 blocking effect Effects 0.000 claims abstract description 12
- 125000006850 spacer group Chemical group 0.000 claims abstract description 8
- 239000000758 substrate Substances 0.000 claims abstract description 6
- 239000010408 film Substances 0.000 claims description 54
- NRTOMJZYCJJWKI-UHFFFAOYSA-N Titanium nitride Chemical compound [Ti]#N NRTOMJZYCJJWKI-UHFFFAOYSA-N 0.000 claims description 10
- 230000002265 prevention Effects 0.000 claims description 10
- 239000010409 thin film Substances 0.000 claims description 9
- 238000002955 isolation Methods 0.000 claims description 6
- 230000008018 melting Effects 0.000 claims description 5
- 238000002844 melting Methods 0.000 claims description 5
- RTAQQCXQSZGOHL-UHFFFAOYSA-N Titanium Chemical compound [Ti] RTAQQCXQSZGOHL-UHFFFAOYSA-N 0.000 claims description 3
- 238000010438 heat treatment Methods 0.000 claims description 3
- 239000010936 titanium Substances 0.000 claims description 3
- 229910052719 titanium Inorganic materials 0.000 claims description 3
- 230000004913 activation Effects 0.000 claims description 2
- 238000000576 coating method Methods 0.000 claims 1
- 238000005137 deposition process Methods 0.000 claims 1
- 230000004888 barrier function Effects 0.000 abstract 3
- 238000005468 ion implantation Methods 0.000 description 6
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 5
- 238000005530 etching Methods 0.000 description 5
- 229910052710 silicon Inorganic materials 0.000 description 5
- 239000010703 silicon Substances 0.000 description 5
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 4
- 229920005591 polysilicon Polymers 0.000 description 4
- 230000008859 change Effects 0.000 description 3
- 230000007547 defect Effects 0.000 description 3
- 238000000151 deposition Methods 0.000 description 2
- 238000001312 dry etching Methods 0.000 description 2
- 150000002500 ions Chemical class 0.000 description 2
- 230000000873 masking effect Effects 0.000 description 2
- 239000012528 membrane Substances 0.000 description 2
- 238000000206 photolithography Methods 0.000 description 2
- 229910021332 silicide Inorganic materials 0.000 description 2
- FVBUAEGBCNSCDD-UHFFFAOYSA-N silicide(4-) Chemical compound [Si-4] FVBUAEGBCNSCDD-UHFFFAOYSA-N 0.000 description 2
- 230000002159 abnormal effect Effects 0.000 description 1
- 230000015572 biosynthetic process Effects 0.000 description 1
- 239000010941 cobalt Substances 0.000 description 1
- 229910017052 cobalt Inorganic materials 0.000 description 1
- GUTLYIVDDKVIGB-UHFFFAOYSA-N cobalt atom Chemical compound [Co] GUTLYIVDDKVIGB-UHFFFAOYSA-N 0.000 description 1
- 238000007796 conventional method Methods 0.000 description 1
- 230000005347 demagnetization Effects 0.000 description 1
- 230000008021 deposition Effects 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
- 238000009792 diffusion process Methods 0.000 description 1
- 239000002019 doping agent Substances 0.000 description 1
- 230000008570 general process Effects 0.000 description 1
- 230000010354 integration Effects 0.000 description 1
- 239000000463 material Substances 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 238000005121 nitriding Methods 0.000 description 1
- WFKWXMTUELFFGS-UHFFFAOYSA-N tungsten Chemical compound [W] WFKWXMTUELFFGS-UHFFFAOYSA-N 0.000 description 1
- 239000010937 tungsten Substances 0.000 description 1
- 229910052721 tungsten Inorganic materials 0.000 description 1
Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
- H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
- H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
- H01L21/8232—Field-effect technology
- H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
- H01L21/8238—Complementary field-effect transistors, e.g. CMOS
- H01L21/823814—Complementary field-effect transistors, e.g. CMOS with a particular manufacturing method of the source or drain structures, e.g. specific source or drain implants or silicided source or drain structures or raised source or drain structures
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
- H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
- H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
- H01L21/8232—Field-effect technology
- H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
- H01L21/8238—Complementary field-effect transistors, e.g. CMOS
- H01L21/823828—Complementary field-effect transistors, e.g. CMOS with a particular manufacturing method of the gate conductors, e.g. particular materials, shapes
- H01L21/823835—Complementary field-effect transistors, e.g. CMOS with a particular manufacturing method of the gate conductors, e.g. particular materials, shapes silicided or salicided gate conductors
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/665—Unipolar field-effect transistors with an insulated gate, i.e. MISFET using self aligned silicidation, i.e. salicide
Abstract
Description
본 발명은 반도체 소자의 제조에 관한 것으로, 특히 반도체 소자의 살리사이드 막 제조방법에 관한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to the manufacture of semiconductor devices, and more particularly to a method for producing salicide films in semiconductor devices.
통상적으로 반도체 소자의 고집적화 및 고속 동작화에 따라, 모오스 트랜지스터와 같은 반도체 소자의 특정 영역 예컨대 소오스/드레인 또는 게이트 영역의 상부에 셀프얼라인으로 실리사이드 막을 형성하는 기술이 공지되어 있는데, 이에 따라 형성된 실리사이드 막을 살리사이드 막이라고 칭하고 있다.In general, according to high integration and high-speed operation of semiconductor devices, a technique of forming a silicide film in a self-aligned manner over a specific region of a semiconductor device such as a source transistor, such as a source / drain or a gate region, is known. The membrane is called the salicide membrane.
전형적인 살리사이드 막을 형성하고 있는 종래의 반도체 소자의 단면구조가도 1에 도시되어 있다. 도면을 참조하면, 필드 절연막(20)을 경계로 살리사이드 블록킹 영역(30: 이하 "SBL")과 살리사이드 영역(20)이 나뉘어져 있고, 살리사이드 영역(20)에 형성된 모오스 트랜지스터는 폴리실리콘으로 이루어진 게이트 영역(44)의 상부와 소오스/드레인 영역(40,42)의 상부에 각기 살리사이드 막(46,41,43)을 갖는다. 한편, SBL 영역(30)에 형성된 모오스 트랜지스터는 폴리실리콘으로 이루어진 게이트 영역(44)의 상부 및 소오스/드레인 영역(50,52)의 상부에 살리사이드 막을 갖지 않는다.The cross-sectional structure of a conventional semiconductor device forming a typical salicide film is shown in FIG. Referring to the drawings, the salicide blocking region 30 (hereinafter, “SBL”) and the salicide region 20 are divided by the field insulating film 20, and the MOS transistor formed in the salicide region 20 is made of polysilicon. Salicide films 46, 41, and 43 are formed on the gate region 44 and the source / drain regions 40 and 42, respectively. On the other hand, the MOS transistor formed in the SBL region 30 does not have a salicide film on the gate region 44 made of polysilicon and on the source / drain regions 50 and 52.
상기 도 1에서, I/O 단자와 아날로그 고저항을 유지하기 위하여 상기 SBL 영역(30)을 형성할 때 식각공정을 진행하는데, 이로 인하여 반도체 소자의 식각 디메지가 심하게 발생된다. 그러한 SBL 식각 손상에 의해 폴리실리콘 게이트 영역(54)의 에지부분에서 발생되는 소오스/드레인 영역(50,52)의 비정상적인 실리콘 리세스드 프로파일은 모오스 트랜지스터의 S/D 연장부위의 접합 깊이를 다르게 하므로, 트랜지스터 소자의 전기적인 특성을 크게 변화시킬 수 있는 요인이 된다.In FIG. 1, an etching process is performed when the SBL region 30 is formed in order to maintain an I / O terminal and analog high resistance, thereby causing an etch image of the semiconductor device to be severely generated. The abnormal silicon recessed profile of the source / drain regions 50 and 52 generated at the edge portion of the polysilicon gate region 54 by such SBL etch damage varies the junction depth of the S / D extension of the MOS transistor. It is a factor that can greatly change the electrical characteristics of the transistor element.
또한, 도면에서 SBL 식각의 불량으로 더블 스페이서(45)를 생성함으로써 좁은 영역의 금속박막 살리사이드 불량을 발생시킨다. 또한 종래에는 SBL 공정에서 MTO+SiN 데포를 고온으로 진행하고 있는데, 여기서 발생하는 고온은 이온주입 되어진 도판트의 확산을 야기하여 열다발에 기인되는 전기적 특성을 변화시키며, MTO +SiN 데포의 장기적인 진행시간으로 공정비용이 증가되는 문제점이 있다.In addition, in the drawing, the double spacers 45 are generated due to the poor SBL etching, thereby generating the metal thin film salicide defect in the narrow region. In addition, in the conventional SBL process, the MTO + SiN depot is advanced to a high temperature. The high temperature generated here causes the diffusion of the ion implanted dopant to change the electrical properties caused by the thermal bundle, and the long running time of the MTO + SiN depot. As a result, the process cost is increased.
따라서, 본 발명의 목적은 종래의 문제를 해결할 수 있는 반도체 소자 제조방법을 제공함에 있다.Accordingly, an object of the present invention is to provide a method of manufacturing a semiconductor device that can solve the conventional problems.
본 발명의 다른 목적은 반도체 소자의 개선된 살리사이드 막 제조방법을 제공함에 있다.Another object of the present invention is to provide an improved salicide film production method of a semiconductor device.
본 발명의 또 다른 목적은 살리사이드 블로킹 영역의 공정을 단순화하기 위하여 MTO+SiN 데포 및 SBL 에치공정을 생략할 수 있는 방법을 제공함에 있다.It is still another object of the present invention to provide a method in which the MTO + SiN depot and SBL etch processes can be omitted to simplify the process of the salicide blocking region.
본 발명의 또 다른 목적은 소오스/드레인 연장영역의 실리콘 리세스 및 에치에 의한 디메지를 방지할 수 있는 방법을 제공함에 있다.It is still another object of the present invention to provide a method capable of preventing demagnetization by silicon recess and etching of the source / drain extension region.
본 발명의 또 다른 목적은 열다발로 인해 발생될 수 있는 소자의 전기적 특성변화를 방지할 수 있는 반도체 소자의 살리사이드 형성방법을 제공함에 있다.Still another object of the present invention is to provide a method for forming a salicide of a semiconductor device which can prevent a change in electrical characteristics of a device that can be generated due to a thermal bundle.
상기한 목적들을 달성하기 위한 본 발명에 따라, 반도체 소자의 살리사이드 막 형성방법은, 반도체 기판에 형성된 소자분리 막을 경계로 정의된 살리사이드 영역과 살리사이드 블로킹 영역에 측벽 스페이서를 갖는 모오스 트랜지스터들을 형성하는 단계와; 상기 살리사이드 영역에 존재하는 모오스 트랜지스터에만 네거티브 슬롭을 갖는 감광막을 형성한 후 전체적으로 살리사이드 반응 방지막을 도포하는 단계와; 리프트 오프 공정으로 상기 살리사이드 영역에 존재하는 상기 살리사이드 반응 방지막 및 상기 감광막을 제거하는 단계와; 전체적으로 고융점 금속을 도포하고 살리사이드 반응을 위한 열처리를 수행하여 상기 살리사이드 영역의 모오스 트랜지스터의 게이트 영역 및 활성화 영역의 상부에만 살리사이드 막이 형성되도록 하고 상기 살리사이드 블로킹 영역의 모오스 트랜지스터에는 상기 살리사이드 반응방지막에 의해 살리사이드 막이 생성되지 않도록 하는 단계와; 상기 살리사이드 블로킹 영역에 존재하는 고융점 금속 막 및 상기 살리사이드 반응 방지막을 제거하는 단계를 구비함을 특징으로 한다.According to the present invention for achieving the above objects, a method of forming a salicide film of a semiconductor device, forming a MOS transistor having a sidewall spacer in the salicide region and the salicide blocking region defined by the device isolation film formed on the semiconductor substrate Making a step; Forming a photoresist film having negative slope only on the MOS transistors present in the salicide region, and then applying the salicide reaction prevention film as a whole; Removing the salicide reaction prevention film and the photosensitive film present in the salicide region by a lift-off process; Applying a high melting point metal as a whole and performing a heat treatment for the salicide reaction to form a salicide film only on the gate region and the activation region of the MOS transistor of the salicide region, and the salicide in the MOS transistor of the salicide blocking region. Preventing the salicide film from being produced by the reaction prevention film; And removing the high melting point metal film and the salicide reaction prevention film present in the salicide blocking region.
본 발명의 다른 기술적 사상에 따라, 반도체 소자의 살리사이드 제조방법은, 금속 박막 살리사이드가 요구되는 영역에 네거티브 스톱을 형성하기 위해 더블 포토레지스트를 진행하고, 노광 및 현상공정을 진행한 다음, 질화티타늄 막 데포를 전면적으로 저온 진행한 후, 살리사이드 영역에만 살리사이드 막을 형성하는 것을 특징으로 한다.According to another technical idea of the present invention, in the method of manufacturing a salicide of a semiconductor device, a double photoresist is performed to form a negative stop in a region where a metal thin film salicide is required, and an exposure and development process are performed, followed by nitriding. After the low temperature of the entire titanium film depot, the salicide film is formed only in the salicide region.
도 1은 종래 기술에 따른 반도체 소자의 단면구조도1 is a cross-sectional structure diagram of a semiconductor device according to the prior art
도 2 내지 도 7은 본 발명의 실시 예들에 따른 반도체 소자의 제조공정을 보인 단면 구조도들2 to 7 are cross-sectional structural views showing a manufacturing process of a semiconductor device according to embodiments of the present invention
이하에서는 본 발명에 따른 반도체 소자의 살리사이드 막 제조방법에 대한 바람직한 실시 예가 첨부한 도면을 참조로 상세히 설명될 것이다.Hereinafter, a preferred embodiment of a salicide film production method of a semiconductor device according to the present invention will be described in detail with reference to the accompanying drawings.
도 2를 참조하면, CMOS 트랜지스터를 형성하기 위해 실리콘 기판(10)위에 통상적인 소자분리 공정 예컨대 샬로우 트렌치 아이솔레이션(STI)공정을 진행하여 소자분리 막(20)을 형성한 것이 보여진다. 이후, 웰 형성을 위한 P- 웰 이온주입과, 문턱전압 제어를 위해 소오스/드레인 영역들(40,42,50,52)에 채널 이온주입, 그리고 아이솔레이션 특성강화를 위한 필드영역(20)에 필드이온을 주입을 행한다. 이 후 게이트 산화막(21,51)을 성장시킨 후, 게이트 폴리 실리콘을 증착하여 게이트 영역들(44,54)을 형성한다. 게이트 영역의 패턴을 위한 사진공정과 건식식각 공정을 진행한 후, LDD 이온주입을 진행한다. 다음 게이트 스페이서(45,53)의 형성을위해 MTO+SiN을 데포하고 사진공정과 건식식각 공정을 진행한 다음, 디프 S/D 이온주입을 진행하면, 도 2와 같은 결과물을 얻는다. 즉, 도 2는 상기와 같은 공정들을 순차로 행하여 디프 S/D 이온주입 공정까지 완료된 후의 소자 패턴을 도시한다. 상기 도 2의 도면은 CMOS 제조에서 게이트 스페이서 식각 및 디프 소오스/드레인 이온주입까지는 그대로 일반공정을 진행하는 것을 가리킨다.Referring to FIG. 2, a device isolation film 20 is formed by performing a conventional device isolation process such as a shallow trench isolation (STI) process on a silicon substrate 10 to form a CMOS transistor. Thereafter, P-well ion implantation for well formation, channel ion implantation in source / drain regions 40, 42, 50, and 52 for threshold voltage control, and field in field region 20 for enhancement of isolation characteristics Ions are implanted. After the gate oxide layers 21 and 51 are grown, gate polysilicon is deposited to form gate regions 44 and 54. After performing the photolithography process and the dry etching process for the pattern of the gate region, LDD ion implantation is performed. Next, MTO + SiN is depoted to form the gate spacers 45 and 53, the photolithography process and the dry etching process are performed, and the deep S / D ion implantation is performed to obtain a result as shown in FIG. 2. That is, FIG. 2 shows the device pattern after the processes described above are completed in order to complete the deep S / D ion implantation process. 2 shows that the general process proceeds as it is until the gate spacer etching and deep source / drain ion implantation in CMOS fabrication.
도 3은 후속의 공정에서 리프트 오프 공정을 적용하기 위해 더블 포토레지스트를 증착하여 살리사이드 영역(20)에 네거티브 슬롭을 형성한 구조를 보인 것이다. 도면에서 보여지는 네거티브 슬롭은 감광막인 포토레지스트를 2개의 막(22,24) 으로 도포한 후, 노광 및 현상을 진행한 결과이다.3 shows a structure in which a double photoresist is deposited to form a negative slop in the salicide region 20 in order to apply a lift-off process in a subsequent process. The negative slop shown in the figure is the result of applying the photoresist as a photoresist film to the two films 22 and 24 and then performing exposure and development.
도 4는 SBL 영역(30)에서 살리사이드 막이 형성되지 않도록 하기 위해 살리사이드 막을 마스킹하는 막으로서 질화 티타늄 막(25, 26)을 전체적으로 데포한 구조를 보인 것이다. 상기 질화 티타늄 막(25,26)은 사안에 따라 50 내지 3000옹그스트롱의 두께를 갖는 저온증착 물질로 대치될 수 있다.FIG. 4 shows a structure in which the titanium nitride films 25 and 26 are depoted as a film for masking the salicide film so that the salicide film is not formed in the SBL region 30. The titanium nitride films 25 and 26 may be replaced with a low temperature deposition material having a thickness of 50 to 3000 Angstroms, depending on the case.
도 5는 리프트 오프방식을 적용하여 금속박막 영역(20)위의 포토레지스트(24,22) 및 질화티타늄 막(25)을 스트립한 결과를 보인 것이다. 여기서, 네거티브 슬롭에 의해 상기 살리사이드 영역(20)의 상부의 포토레지스트(24,22) 및 질화티타늄 막(25)은 제거되나, 상기 SBL 영역(30)의 상부에 있는 질화티타늄 막(26)은 그대로 잔존함을 알 수 있다.5 shows the result of stripping the photoresist 24 and 22 and the titanium nitride film 25 on the metal thin film region 20 by applying the lift-off method. Here, the photoresist 24 and 22 and the titanium nitride film 25 on the salicide region 20 are removed by the negative slope, but the titanium nitride film 26 on the SBL region 30 is removed. You can see that it remains as it is.
도 6은 도 5의 결과물에 고융점 금속 예컨대 텅스텐, 코발트, 티타늄 등의 금속박막을 데포지션하고 급속 열처리(RTS)를 행하여 살리사이드 반응을 얻는 것을보여준다. 여기서, 상기 SBL 영역(30)에 잔존하는 상기 질화티타늄 막(26)은 상기 데포지션된 금속박막과 하부의 소오스/드레인 영역(50,52)을 격리시키는 역할을 하므로 살리사이드 반응은 일어나지 않는다. 결국, 상기 질화티타늄 막(26)은 살리사이드마스킹 막으로서 기능한다. 한편, 상기 살리사이드 영역(20)의 게이트 영역(44),소오스/드레인 영역들(40,42)의 상부에는 셀프 얼라인된 실리사이드 막 즉, 살리사이드 막(46,41,43)이 형성된다.FIG. 6 shows that a salicide reaction is obtained by depositing a metal thin film of high melting point metal such as tungsten, cobalt, titanium, etc. and performing rapid heat treatment (RTS) on the resultant of FIG. 5. Here, the titanium nitride film 26 remaining in the SBL region 30 isolates the deposited metal thin film from the source / drain regions 50 and 52 below, so that a salicide reaction does not occur. As a result, the titanium nitride film 26 functions as a salicide masking film. On the other hand, a self-aligned silicide layer, that is, a salicide layer 46, 41, 43 is formed on the gate region 44 and the source / drain regions 40 and 42 of the salicide region 20. .
도 7은 SBL 영역(30) 상부의 금속 박막(28) 및 그 하부의 질화티타늄 막(26)을 습식 및 H2O2 스트립 공정을 실시하여 제거한 후의 단면을 결과적으로 보여준다.FIG. 7 consequently shows the cross section after removal of the metal thin film 28 over the SBL region 30 and the titanium nitride film 26 underneath by performing wet and H 2 O 2 strip processes.
상기한 살리사이드 막 제조방법에 따르면, 종래에 비해 제조공정이 단순화되어 소자의 제조에 걸리는 시간을 단축할 수 있고, 열다발(thermal budget)을 감소시킬 수 있다. 또한 SBL 의 과도식각에 따른 소오스/드레인 식각 손상을 최소화하여 실리콘 리세스(recess)가 감소된다. 더블 스페이서를 형성하지 않으므로 좁은 지역에서의 금속박막 살리사이드 불량을 방지 또는 최소화한다.According to the salicide film production method described above, the manufacturing process is simplified compared to the conventional method, it is possible to shorten the time required to manufacture the device, it is possible to reduce the thermal budget (thermal budget). In addition, silicon recesses are reduced by minimizing source / drain etch damage due to over-etching of SBL. It does not form a double spacer to prevent or minimize metal thin film salicide defects in narrow areas.
상기한 설명에서는 본 발명의 바람직한 실시예를 도면을 참조하여 설명하였지만, 해당 기술 분야의 숙련된 당업자는 아래의 특허 청구의 범위에 기재된 본 발명의 기술적 사상 및 영역으로부터 벗어나지 않는 범위 내에서 본 발명을 다양하게 수정 및 변경시킬 수 있음을 이해할 수 있을 것이다.In the foregoing description, a preferred embodiment of the present invention has been described with reference to the drawings, but those skilled in the art will appreciate the present invention without departing from the spirit and scope of the present invention as set forth in the claims below. It will be understood that various modifications and changes can be made.
상기한 바와 같이, 본 발명에 따르면, 종래에 비해 제조공정이 단순화되어 소자의 제조에 걸리는 시간을 단축할 수 있고, 열다발을 감소시킬 수 있는 효과가 있다. 또한 살리사이드 블로킹 영역의 형성시 과도식각에 따른 소오스/드레인 식각 손상을 최소화하여 실리콘 리세스가 감소된다. 그리고, 더블 스페이서를 형성하지 않으므로 좁은 지역에서의 금속박막 살리사이드 불량을 방지 또는 최소화한다.As described above, according to the present invention, the manufacturing process is simplified as compared with the prior art, it is possible to shorten the time required to manufacture the device, it is possible to reduce the heat bundle. In addition, silicon recesses are reduced by minimizing source / drain etch damage due to overetching in forming the salicide blocking region. In addition, since the double spacer is not formed, the metal thin film salicide defect in a narrow area is prevented or minimized.
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| KR100774830B1 (en) * | 2006-07-14 | 2007-11-07 | 동부일렉트로닉스 주식회사 | Patterning method of nonsalicidation region for semiconductor manufacturing |
| KR100821478B1 (en) * | 2006-08-23 | 2008-04-10 | 동부일렉트로닉스 주식회사 | CMOS image sensor and the method of fabricating thereof |
| KR100859489B1 (en) * | 2007-06-08 | 2008-09-24 | 주식회사 동부하이텍 | Method for manufacturing of semiconductor device |
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Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
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| KR100774830B1 (en) * | 2006-07-14 | 2007-11-07 | 동부일렉트로닉스 주식회사 | Patterning method of nonsalicidation region for semiconductor manufacturing |
| KR100821478B1 (en) * | 2006-08-23 | 2008-04-10 | 동부일렉트로닉스 주식회사 | CMOS image sensor and the method of fabricating thereof |
| KR100859489B1 (en) * | 2007-06-08 | 2008-09-24 | 주식회사 동부하이텍 | Method for manufacturing of semiconductor device |
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