KR20030002600A - 반도체소자의 금속배선 형성방법 - Google Patents
반도체소자의 금속배선 형성방법 Download PDFInfo
- Publication number
- KR20030002600A KR20030002600A KR1020010038271A KR20010038271A KR20030002600A KR 20030002600 A KR20030002600 A KR 20030002600A KR 1020010038271 A KR1020010038271 A KR 1020010038271A KR 20010038271 A KR20010038271 A KR 20010038271A KR 20030002600 A KR20030002600 A KR 20030002600A
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- KR
- South Korea
- Prior art keywords
- forming
- teos
- contact hole
- via contact
- organic sog
- Prior art date
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Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
- H01L21/76829—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing characterised by the formation of thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers
- H01L21/76831—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing characterised by the formation of thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers in via holes or trenches, e.g. non-conductive sidewall liners
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
- H01L21/76802—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics
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- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
Abstract
Description
Claims (2)
- 제1금속배선을 형성하고 전체표면 상부에 제1TEOS막을 형성하는 공정과,전체표면상부를 평탄화시키는 유기 SOG 계 박막을 형성하는 공정과,상기 유기 SOG 계 박막 상부에 제2TEOS막을 형성하는 공정과,상기 제2TEOS막 및 유기 SOG 계 박막을 식각하여 상기 제1금속배선을 노출시키는 비아콘택홀을 형성하는 공정과,상기 비아콘택홀 측벽에 제3TEOS막으로 스페이서를 형성하는 공정을 포함하는 반도체소자의 금속배선 형성방법.
- 제 1 항에 있어서,상기 제3TEOS 막은 300 ∼ 500 Å 두께로 형성하는 것을 특징으로하는 반도체소자의 금속배선 형성방법.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
KR1020010038271A KR100735628B1 (ko) | 2001-06-29 | 2001-06-29 | 반도체소자의 금속배선 형성방법 |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
KR1020010038271A KR100735628B1 (ko) | 2001-06-29 | 2001-06-29 | 반도체소자의 금속배선 형성방법 |
Publications (2)
Publication Number | Publication Date |
---|---|
KR20030002600A true KR20030002600A (ko) | 2003-01-09 |
KR100735628B1 KR100735628B1 (ko) | 2007-07-04 |
Family
ID=27712307
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
KR1020010038271A KR100735628B1 (ko) | 2001-06-29 | 2001-06-29 | 반도체소자의 금속배선 형성방법 |
Country Status (1)
Country | Link |
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KR (1) | KR100735628B1 (ko) |
Family Cites Families (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
KR100197121B1 (ko) * | 1995-12-26 | 1999-06-15 | 김영환 | 반도체 소자의 제조방법 |
JPH10163317A (ja) * | 1996-11-28 | 1998-06-19 | Mitsubishi Electric Corp | 半導体装置及びその製造方法 |
KR19980043737A (ko) * | 1996-12-04 | 1998-09-05 | 김영환 | 반도체 장치의 층간 절연막 형성방법 |
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2001
- 2001-06-29 KR KR1020010038271A patent/KR100735628B1/ko active IP Right Grant
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Publication number | Publication date |
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KR100735628B1 (ko) | 2007-07-04 |
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