KR20030000848A - method for fabricating semiconductor device - Google Patents

method for fabricating semiconductor device Download PDF

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Publication number
KR20030000848A
KR20030000848A KR1020010037002A KR20010037002A KR20030000848A KR 20030000848 A KR20030000848 A KR 20030000848A KR 1020010037002 A KR1020010037002 A KR 1020010037002A KR 20010037002 A KR20010037002 A KR 20010037002A KR 20030000848 A KR20030000848 A KR 20030000848A
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KR
South Korea
Prior art keywords
layer
buried contact
contact part
contact portion
semiconductor device
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KR1020010037002A
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Korean (ko)
Inventor
유영호
김도우
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주식회사 하이닉스반도체
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Priority to KR1020010037002A priority Critical patent/KR20030000848A/en
Publication of KR20030000848A publication Critical patent/KR20030000848A/en

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
    • H01L21/28008—Making conductor-insulator-semiconductor electrodes
    • H01L21/28017—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon
    • H01L21/28026—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor
    • H01L21/28035—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor the final conductor layer next to the insulator being silicon, e.g. polysilicon, with or without impurities
    • H01L21/28044—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor the final conductor layer next to the insulator being silicon, e.g. polysilicon, with or without impurities the conductor comprising at least another non-silicon conductive layer
    • H01L21/28052—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor the final conductor layer next to the insulator being silicon, e.g. polysilicon, with or without impurities the conductor comprising at least another non-silicon conductive layer the conductor comprising a silicide layer formed by the silicidation reaction of silicon with a metal layer
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B10/00—Static random access memory [SRAM] devices

Abstract

PURPOSE: A fabrication method of a semiconductor device is provided to easily form a buried contact part at junction portion of cell node between an access and drive transistor. CONSTITUTION: After forming a field oxide(205) in a semiconductor substrate(200), a gate oxide(208) and a first doped polysilicon layer(210) are sequentially formed on the resultant structure. A buried contact part(240) is formed by implanting dopants into the exposed substrate(200). An oxidation preventing layer is formed on the first doped polysilicon layer(210) except for the buried contact part(240). Metal, such as titanium is deposited on the exposed buried contact part(240) by using the oxidation preventing layer as a mask. A silicide layer(262) is formed on the buried contact part(240) by annealing the resultant structure. Then, a gate pattern(230) is formed on the resultant structure.

Description

반도체장치의 제조방법{method for fabricating semiconductor device}Method for fabricating semiconductor device

본 발명은 반도체장치의 제조방법에 관한 것으로, 보다 상세하게는 에스램(SRAM)의 엑세스(Access)트랜지스터(transistor)와 드라이브(Drive) 트랜지스터의 셀 노드(cell node)의 접합부위에 매몰콘택부를 용이하게 제조할 수 있는 반도체장치의 제조방법에 관한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of manufacturing a semiconductor device, and more particularly, an investment contact portion is easily connected to a junction between an access transistor of an SRAM and a cell node of a drive transistor. It relates to a method of manufacturing a semiconductor device that can be manufactured easily.

일반적으로 알려진 바와 같이, 에스램의 엑세스 트랜지스터와 드라이브 트랜지스터는 폴리실리콘층 등의 도전배선에 의해 접합되고, 상기 드라이브 트랜지스터와 도전배선 간의 접합부위에는 매립콘택부를 형성하여 전류통로(current path)가 형성되며, 상기 엑세스 트랜지스터와 드라이브 트랜지스터가 전기적으로 서로 연결된다.As is generally known, an access transistor and a drive transistor of SRAM are bonded by a conductive wiring such as a polysilicon layer, and a buried contact portion is formed at a junction between the drive transistor and the conductive wiring to form a current path. The access transistor and the drive transistor are electrically connected to each other.

도 1a 내지 도 1d는 종래 기술에 따른 반도체장치의 제조과정을 보인 공정순서도이다.1A to 1D are process flowcharts showing a manufacturing process of a semiconductor device according to the prior art.

종래 기술에 따른 반도체장치의 제조방법은, 도 1a에 도시된 바와 같이, 반도체기판(100) 상에 완충막(104)을 형성한다. 상기 완충막(104)은 패드산화층(미도시)과 질화막(미도시)을 차례로 증착하여 형성한다.In the method of manufacturing a semiconductor device according to the related art, as shown in FIG. 1A, a buffer film 104 is formed on a semiconductor substrate 100. The buffer film 104 is formed by sequentially depositing a pad oxide layer (not shown) and a nitride film (not shown).

이어서, 상기 완충막(104) 상에 감광막을 도포한 후, 노광 및 현상하여 소자의 격리영역을 노출시키는 제 1감광막패턴(106)을 형성한다.Subsequently, after the photosensitive film is coated on the buffer film 104, the photosensitive film pattern 106 is formed by exposing and developing to expose the isolation region of the device.

그 다음, 제 1감광막패턴(106)을 마스크로 하여 완충막을 식각한 후, 로코스(Local Oxidization of Silicon) 공정에 의해 필드산화층(105)을 형성한다.Next, after the buffer film is etched using the first photoresist pattern 106 as a mask, the field oxide layer 105 is formed by a local oxide process of silicon.

이 후, 도 1b에 도시된 바와 같이, 제 1감광막패턴을 제거하고, 별도의 불순물 주입 공정을 통해 웰(102)을 형성한다.Thereafter, as shown in FIG. 1B, the first photoresist layer pattern is removed and a well 102 is formed through a separate impurity implantation process.

이어서, 상기 필드산화층(105)을 포함한 기판 전면에 게이트산화층(108)과 불순물이 도핑된 다결정실리콘층(110)을 차례로 증착한 후, 상기 불순물이 도핑된다결정실리콘층(110) 상에 매립콘택영역을 개구시키는 제 2감광막패턴(120)을 형성한다.Subsequently, the gate oxide layer 108 and the polysilicon layer 110 doped with impurities are sequentially deposited on the entire surface of the substrate including the field oxide layer 105, and then the impurities are doped with buried contacts on the crystal silicon layer 110. A second photosensitive film pattern 120 for opening an area is formed.

그 다음, 상기 제 2감광막패턴(120)을 마스크로 하여 상기 불순물이 도핑된 다결정실리콘층 및 게이트절연층(208)을 식각 공정을 진행시킨 후, 상기 식각 공정에 의해 노출된 부위에 불순물 주입(150) 공정을 진행하여 매립콘택부(140)를 형성한다.Subsequently, the second photoresist pattern 120 is used as a mask, and the impurity-doped polysilicon layer and the gate insulating layer 208 are etched, and then impurity implantation is performed in a portion exposed by the etch process. 150 to form a buried contact portion 140.

이 후, 도 1c에 도시된 바와 같이, 제 2감광막패턴을 제거한다.Thereafter, as shown in FIG. 1C, the second photoresist pattern is removed.

그리고 상기 매립콘택부(140)를 포함한 기판 전면에 불순물이 도핑된 제 2 다결정실리콘층(112), 텅스텐금속층(114) 및 절연층(116)을 차례로 증착한 후, 상기 절연층 상에 게이트영역을 정의하는 제 3감광막패턴(122)을 형성한다.After depositing a second polysilicon layer 112, a tungsten metal layer 114, and an insulating layer 116 doped with impurities on the entire surface of the substrate including the buried contact portion 140, a gate region is formed on the insulating layer. A third photosensitive film pattern 122 is formed.

이어서, 상기 제 3감광막패턴(122)을 마스크로 하여 절연층(116), 텅스텐금속층(114), 제 2불순물이 도핑된 다결정실리콘층(112) 및 제 1불술물이 도핑된 다결정실리콘층(110)을 식각하여, 도 1d에 도시된 바와 같이, 게이트(130)를 형성한다. 그 다음, 제 3감광막패턴을 제거한다.Subsequently, the insulating layer 116, the tungsten metal layer 114, the polycrystalline silicon layer 112 doped with the second impurity, and the polycrystalline silicon layer doped with the first impurity are formed using the third photoresist pattern 122 as a mask. The 110 is etched to form the gate 130, as shown in FIG. 1D. Then, the third photoresist pattern is removed.

그러나, 종래의 방법에서는 게이트 형성을 위한 식각 공정 진행 시, 약간의 오정렬 등의 식각불량이 발생되더라도 매립콘택부가 손실되는 문제점이 발생되었다.However, in the conventional method, when the etching process for forming the gate is performed, a problem arises in which the buried contact portion is lost even if a slight misalignment such as misalignment occurs.

이에 본 발명은 상기 종래의 문제점을 해결하기 위해 안출된 것으로, 게이트 형성을 위한 식각 공정 진행 시, 매몰콘택부의 손실을 방지할 수 있는 반도체장치의 제조방법을 제공함에 그 목적이 있다.Accordingly, an object of the present invention is to provide a method of manufacturing a semiconductor device capable of preventing the loss of an investment contact portion during an etching process for forming a gate.

도 1a 내지 도 1d는 종래 기술에 따른 반도체장치의 제조과정을 보인 공정순서도.1A to 1D are process flowcharts showing a manufacturing process of a semiconductor device according to the prior art.

도 2a 내지 도 2f는 본 발명에 따른 반도체장치의 제조과정을 보인 공정순서도.2A to 2F are process flowcharts showing a manufacturing process of a semiconductor device according to the present invention;

도면의 주요부분에 대한 부호의 설명Explanation of symbols for main parts of the drawings

200. 반도체기판 202. 웰200. Semiconductor substrate 202. Well

205. 필드산화층 208. 게이트절연층205. Field oxide layer 208. Gate insulation layer

210, 212. 불순물이 도핑된 다결정실리콘층 220, 224, 226. 감광막패턴210, 212. Polycrystalline silicon layers doped with impurities 220, 224, 226. Photoresist pattern

230. 게이트 240 매립콘택부230. Gate 240 Landfill

250. 불순물주입 252. 열처리250. Impurity injection 252. Heat treatment

260. 산화방지층 262. 실리사이드층260. Antioxidant layer 262. Silicide layer

상기 목적을 달성하기 위한 본 발명의 반도체장치의 제조방법은 반도체기판 상에 매립콘택부를 가진 제 1도전층을 형성하는 단계와, 매립콘택부를 제외한 제 1도전층에 산화방지층을 형성하는 단계와, 매립콘택부에 금속층을 형성하는 단계와, 산화방지층을 마스크로 하고 금속층에 열처리를 진행하여 실리사이드층을 형성하는 단계와, 산화방지층을 제거하는 단계와, 상기 결과물 상에 제 2도전층, 제 3도전층 및 절연층을 차례로 증착하는 단계와, 절연층, 제 3도전층, 제 2도전층 및 제 1도전층을 소정부위 식각하여 게이트를 형성하는 단계를 포함한 것을 특징으로 한다.A method of manufacturing a semiconductor device of the present invention for achieving the above object comprises the steps of forming a first conductive layer having a buried contact portion on the semiconductor substrate, forming an antioxidant layer on the first conductive layer except for the buried contact portion; Forming a silicide layer by forming a metal layer on the buried contact portion, heat-treating the metal layer with an antioxidant layer as a mask, removing the anti-oxidation layer, and forming a second conductive layer and a third conductive layer on the resultant. And depositing a conductive layer and an insulating layer in sequence, and etching a predetermined portion of the insulating layer, the third conductive layer, the second conductive layer, and the first conductive layer to form a gate.

이하, 본 발명의 바람직한 실시예를 첨부된 도면을 참조하여 상세히 설명하면 다음과 같다.Hereinafter, preferred embodiments of the present invention will be described in detail with reference to the accompanying drawings.

도 2a 내지 도 2f는 본 발명에 따른 반도체장치의 제조과정을 보인 공정순서도이다.2A to 2F are process flowcharts showing a manufacturing process of a semiconductor device according to the present invention.

본 발명의 반도체장치의 제조방법은, 도 2a에 도시된 바와 같이, 먼저, 반도체기판(200) 상에 패드산화막 및 질화막으로 구성된 완충막(204)을 형성한 후, 상기 완충막(204) 상에 소자의 격리영역을 노출시키는 제 1감광막패턴(106)을 형성한다.In the method of manufacturing a semiconductor device of the present invention, as shown in FIG. 2A, first, a buffer film 204 composed of a pad oxide film and a nitride film is formed on a semiconductor substrate 200, and then on the buffer film 204. A first photosensitive film pattern 106 is formed in the semiconductor substrate to expose the isolation region of the device.

이어서, 상기 제 1감광막패턴(106)을 마스크로 하여 상기 완충막(106)을 식각하고, 로코스 공정을 통해 필드산화층(105)을 형성한다.Subsequently, the buffer layer 106 is etched using the first photoresist layer pattern 106 as a mask, and the field oxide layer 105 is formed through a LOCOS process.

그 다음, 도 2b에 도시된 바와 같이, 제 1감광막패턴 및 완충막을 제거하고나서 불순물 주입 공정을 거쳐서 웰(102)을 형성한다.Next, as shown in FIG. 2B, the wells 102 are formed through the impurity implantation process after removing the first photoresist layer pattern and the buffer layer.

이 후, 상기 결과의 기판 상에 게이트절연층(208)과 제 1불순물이 도핑된 다결정실리콘층(210)을 차례로 형성한다.Thereafter, the gate insulating layer 208 and the polysilicon layer 210 doped with the first impurity are sequentially formed on the resultant substrate.

이어서, 상기 제 1불순물이 도핑된 다결정실리콘층(210) 상에 감광막을 도포한 후, 노광 및 현상하여 매립콘택 영역을 노출시키는 제 2감광막패턴을 형성한다.Subsequently, a photoresist film is coated on the polysilicon layer 210 doped with the first impurity, and then exposed and developed to form a second photoresist pattern exposing the buried contact region.

그 다음, 상기 제 2감광막패턴(220)을 마스크로 하여 제 1불순물이 도핑된 다결정실리콘층(210) 및 게이트절연층(208)을 식각한 후, 노출된 부위에 불순물 주입(250) 공정을 진행하여 매립콘택부(240)를 형성한다.Next, the polysilicon layer 210 and the gate insulating layer 208 doped with the first impurity are etched using the second photoresist pattern 220 as a mask, and then impurity implantation 250 is performed on the exposed portions. Proceeding to form the buried contact portion 240.

상기 불순물 주입(150) 공정을 진행하는 이유는 상기 제 1불순물이 도핑된 다결정실리콘층(210) 및 게이트절연층(208) 식각 공정 시, 식각으로 인한 기판의 불순물의 손실을 막고, 아울러 콘택저항을 낮추기 위함이다.The impurity implantation process 150 is performed in order to prevent the loss of impurities in the substrate due to etching during the etching process of the polysilicon layer 210 and the gate insulating layer 208 doped with the first impurity, and the contact resistance. To lower the

이 후, 도 2c에 도시된 바와 같이, 제 2감광막패턴을 제거한다.Thereafter, as shown in FIG. 2C, the second photoresist pattern is removed.

그리고나서 매립콘택부(240)를 포함한 제 1불순물이 도핑된 다결정실리콘층(220) 상에 질화막 또는 산화막 등의 제 1절연층을 증착한 후, 상기 제 1절연층(260) 상에 상기 제 2감광막패턴과 동일 형상을 가진 제 3감광막패턴(224)을 형성한다.Then, after depositing a first insulating layer such as a nitride film or an oxide film on the polysilicon layer 220 doped with the first impurity including the buried contact portion 240, the first insulating layer 260 on the first insulating layer 260 A third photoresist pattern 224 having the same shape as the second photoresist pattern is formed.

이어서, 상기 제 3감광막패턴(224)을 마스크로 하여 상기 제 1절연층을 식각하여 산화방지층(260)을 형성한다. 이때, 산화방지층(260)은 이 후의 실리사이드층 형성 공정에서, 하부의 층이 실리사이드화되는 것을 막아주는 역할을 한다.Subsequently, the first insulating layer is etched using the third photoresist pattern 224 as a mask to form an antioxidant layer 260. At this time, the antioxidant layer 260 serves to prevent the lower layer from being silicided in the subsequent silicide layer forming process.

그 다음, 도 2d에 도시된 바와 같이, 제 3감광막패턴을 제거한다. 그리고나서 산화방지층(260)을 포함한 기판 전면에 티타늄(Ti) 등을 스퍼터링(sputtering)에 의해 증착하여 금속층(미도시)을 형성한 다음, 상기 금속층을 감광막(미도시) 등을 이용하여 매립콘택부(240)에만 잔류되도록 식각한다.Next, as shown in FIG. 2D, the third photoresist pattern is removed. Then, titanium (Ti) or the like is deposited on the entire surface of the substrate including the anti-oxidation layer 260 by sputtering to form a metal layer (not shown), and then the metal layer is embedded using a photoresist film (not shown). The etching is performed so that only the portion 240 remains.

이 후, 상기 결과물을 500∼800℃의 온도범위에서 열처리(252)하여 실리사이드층(262)을 형성한다.Thereafter, the resultant is heat treated 252 at a temperature in the range of 500 to 800 ° C. to form the silicide layer 262.

이어서, 도 2e에 도시된 바와 같이, 산화방지층(26)을 제거한다.Then, as shown in FIG. 2E, the antioxidant layer 26 is removed.

그리고나서 실리사이드층을 포함한 상기 기판 전면에 제 2불순물이 도핑된 다결정실리콘층(212), 텅스텐금속층(214), 제 2절연층(216)을 차례로 증착한 후, 상기 제 2절연층(216) 상에 게이트영역을 정의하는 제 3감광막패턴(226)을 형성한다.Then, after depositing a polysilicon layer 212, a tungsten metal layer 214, and a second insulating layer 216 doped with a second impurity on the entire surface of the substrate including the silicide layer, the second insulating layer 216 A third photoresist pattern 226 defining a gate region is formed on the substrate.

그 다음, 상기 제 3감광막패턴(226)을 마스크로 하여 제 2절연층, 텅스텐금속층, 불순물이 도핑된 다결정실리콘층을 식각하여, 도 2f에 도시된 바와 같이, 게이트(130)를 형성한다. 이 후, 제 3감광막패턴을 제거한다.Next, the second insulating layer, the tungsten metal layer, and the polysilicon layer doped with impurities are etched using the third photoresist pattern 226 as a mask to form a gate 130 as shown in FIG. 2F. Thereafter, the third photosensitive film pattern is removed.

본 발명은 매립콘택부 상에 실리사이드층을 형성함으로써, 게이트 식각 공정 진행 시, 상기 실리사이드층에 의해 식각에 의한 기판(즉, 매립콘택부)가 손실되는 것을 방지한다.The present invention forms a silicide layer on the buried contact portion, thereby preventing the substrate (ie, the buried contact portion) from being lost by the silicide layer during the gate etching process.

이상에서와 같이, 본 발명의 반도체장치의 제조방법은 매립콘택부 상에 실리사이드층을 형성함으로써, 게이트 형성을 위한 식각 공정 진행할 시에 상기 실리사이드층이 매립콘택부의 식각을 방지하는 역할을 하므로, 기판의 손실이 없다.As described above, the method of manufacturing the semiconductor device of the present invention forms a silicide layer on the buried contact portion, so that the silicide layer prevents etching of the buried contact portion during the etching process for forming the gate. There is no loss.

또한, 매립콘택부를 제외한 제 1도전층 상에 산화방지층을 형성함으로써, 실리사이드 공정 진행 시, 상기 산화방지층에 의해 제 1도전층이 산화되는 것이 방지된다.In addition, by forming an antioxidant layer on the first conductive layer except for the buried contact portion, the oxidation of the first conductive layer is prevented by the antioxidant layer during the silicide process.

기타, 본 발명은 그 요지를 일탈하지 않는 범위에서 다양하게 변경하여 실시할 수 있다.In addition, this invention can be implemented in various changes within the range which does not deviate from the summary.

Claims (2)

반도체기판 상에 매립콘택부를 가진 제 1도전층을 형성하는 단계와,Forming a first conductive layer having a buried contact portion on the semiconductor substrate; 상기 매립콘택부를 제외한 상기 제 1도전층에 산화방지층을 형성하는 단계와,Forming an antioxidant layer on the first conductive layer except for the buried contact portion; 상기 매립콘택부에 금속층을 형성하는 단계와,Forming a metal layer on the buried contact portion; 상기 산화방지층을 마스크로 하고, 상기 금속층에 열처리를 진행하여 실리사이드층을 형성하는 단계와,Forming an silicide layer by performing heat treatment on the metal layer using the antioxidant layer as a mask; 상기 산화방지층을 제거하는 단계와,Removing the antioxidant layer; 상기 결과물 상에 제 2도전층, 제 3도전층 및 절연층을 차례로 증착하는 단계와,Sequentially depositing a second conductive layer, a third conductive layer, and an insulating layer on the resultant; 상기 절연층, 제 3도전층, 제 2도전층 및 제 1도전층을 소정부위 식각하여 게이트를 형성하는 단계를 포함하여 구성되는 것을 특징으로 하는 반도체장치의 제조방법.And etching a predetermined portion of the insulating layer, the third conductive layer, the second conductive layer, and the first conductive layer to form a gate. 제 1항에 있어서, 상기 금속층은 티타늄이고, 상기 실리사이드층은 티타늄실리사이드층인 것을 특징으로 하는 반도체장치의 제조방법.The method of claim 1, wherein the metal layer is titanium, and the silicide layer is a titanium silicide layer.
KR1020010037002A 2001-06-27 2001-06-27 method for fabricating semiconductor device KR20030000848A (en)

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