KR20020092570A - Method of a via hole of semiconductor device - Google Patents
Method of a via hole of semiconductor device Download PDFInfo
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- KR20020092570A KR20020092570A KR1020010031244A KR20010031244A KR20020092570A KR 20020092570 A KR20020092570 A KR 20020092570A KR 1020010031244 A KR1020010031244 A KR 1020010031244A KR 20010031244 A KR20010031244 A KR 20010031244A KR 20020092570 A KR20020092570 A KR 20020092570A
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- insulating layer
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- 238000000034 method Methods 0.000 title claims abstract description 42
- 239000004065 semiconductor Substances 0.000 title claims abstract description 11
- 239000010410 layer Substances 0.000 claims abstract description 77
- 229910052751 metal Inorganic materials 0.000 claims abstract description 40
- 239000002184 metal Substances 0.000 claims abstract description 40
- 238000005530 etching Methods 0.000 claims abstract description 14
- 239000011229 interlayer Substances 0.000 claims abstract description 14
- 239000000758 substrate Substances 0.000 claims abstract description 13
- 238000000059 patterning Methods 0.000 claims abstract description 4
- 230000015572 biosynthetic process Effects 0.000 claims abstract 2
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims description 7
- 238000009413 insulation Methods 0.000 claims description 7
- 229910052814 silicon oxide Inorganic materials 0.000 claims description 7
- 229910052581 Si3N4 Inorganic materials 0.000 claims description 6
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 claims description 6
- 238000000151 deposition Methods 0.000 claims description 5
- 238000000206 photolithography Methods 0.000 claims description 5
- 239000000463 material Substances 0.000 claims description 4
- 229910004298 SiO 2 Inorganic materials 0.000 claims description 2
- BOTDANWDWHJENH-UHFFFAOYSA-N Tetraethyl orthosilicate Chemical compound CCO[Si](OCC)(OCC)OCC BOTDANWDWHJENH-UHFFFAOYSA-N 0.000 claims description 2
- 238000000623 plasma-assisted chemical vapour deposition Methods 0.000 claims 1
- 239000012212 insulator Substances 0.000 abstract description 4
- 239000011521 glass Substances 0.000 abstract 1
- 230000007547 defect Effects 0.000 description 6
- 238000005229 chemical vapour deposition Methods 0.000 description 4
- 230000007423 decrease Effects 0.000 description 2
- 238000005516 engineering process Methods 0.000 description 2
- 239000000126 substance Substances 0.000 description 2
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 description 1
- 229910052782 aluminium Inorganic materials 0.000 description 1
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 1
- 230000000295 complement effect Effects 0.000 description 1
- 239000004020 conductor Substances 0.000 description 1
- 229910052802 copper Inorganic materials 0.000 description 1
- 239000010949 copper Substances 0.000 description 1
- 239000003989 dielectric material Substances 0.000 description 1
- 229910044991 metal oxide Inorganic materials 0.000 description 1
- 150000004706 metal oxides Chemical class 0.000 description 1
- 238000001465 metallisation Methods 0.000 description 1
- 238000012544 monitoring process Methods 0.000 description 1
- 238000005498 polishing Methods 0.000 description 1
- 238000004544 sputter deposition Methods 0.000 description 1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
- H01L21/76802—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02107—Forming insulating materials on a substrate
- H01L21/02109—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates
- H01L21/02112—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer
- H01L21/02123—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon
- H01L21/02164—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon the material being a silicon oxide, e.g. SiO2
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02107—Forming insulating materials on a substrate
- H01L21/02109—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates
- H01L21/02112—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer
- H01L21/02123—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon
- H01L21/0217—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon the material being a silicon nitride not containing oxygen, e.g. SixNy or SixByNz
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02107—Forming insulating materials on a substrate
- H01L21/02225—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer
- H01L21/0226—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process
- H01L21/02263—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process deposition from the gas or vapour phase
- H01L21/02271—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process deposition from the gas or vapour phase deposition by decomposition or reaction of gaseous or vapour phase compounds, i.e. chemical vapour deposition
- H01L21/02274—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process deposition from the gas or vapour phase deposition by decomposition or reaction of gaseous or vapour phase compounds, i.e. chemical vapour deposition in the presence of a plasma [PECVD]
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02107—Forming insulating materials on a substrate
- H01L21/02296—Forming insulating materials on a substrate characterised by the treatment performed before or after the formation of the layer
- H01L21/02299—Forming insulating materials on a substrate characterised by the treatment performed before or after the formation of the layer pre-treatment
- H01L21/02304—Forming insulating materials on a substrate characterised by the treatment performed before or after the formation of the layer pre-treatment formation of intermediate layers, e.g. buffer layers, layers to improve adhesion, lattice match or diffusion barriers
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- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3105—After-treatment
- H01L21/31051—Planarisation of the insulating layers
- H01L21/31053—Planarisation of the insulating layers involving a dielectric removal step
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
- H01L21/76819—Smoothing of the dielectric
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Abstract
Description
본 발명은 반도체장치의 비아홀 형성방법에 관한것으로서, 특히, 금속배선상에 식각정지층을 형성한후 비아홀을 형성하여 금속배선 측벽의 절연층이 과식각되는 것을 방지하기 위한것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of forming a via hole in a semiconductor device, and more particularly, to form an via hole after forming an etch stop layer on a metal wiring to prevent over-etching of the insulating layer on the sidewall of the metal wiring.
0.25㎛이하의 서브마이크론(submicron) CMOS(Complementary Metal Oxide Semiconductor) 기술의 백엔드(Backend) 기술은 낮은 배선저항과 배선간의 낮은 정전용량(capacitance)을 확보하여 동작속도의 저하를 억제하는 것이 관건이다. 이를 위해서 비유전상수가 낮은 유전체를 사용하여 SOG(spin on class)방식으로 절연층을 형성한다.The backend technology of submicron Complementary Metal Oxide Semiconductor (CMOS) technology having a thickness of 0.25 μm or less is key to securing a low wiring resistance and a low capacitance between wirings to suppress a decrease in operating speed. To this end, an insulating layer is formed by a spin on class (SOG) method using a dielectric having a low dielectric constant.
SOG 방식으로 형성한 절연층은 CVD(chemical Vapor Deposition)방식으로 형성한 절연층보다 상대적으로 기계적, 화학적 특성이 약한다. 즉 비아의 식각시 식각속도가 높아서 보더리스 비아를 허용하는 0.25㎛이하의 초미세 공정에서는 도 1b 에서와 같은 에치 프로파일(etch profile)이 발생한다. 이러한 불량은 0.15㎛급에서는 더욱 공정마진이 줄어들어 더욱 빈번히 일어난다.The insulating layer formed by the SOG method is relatively weak mechanical and chemical properties than the insulating layer formed by the CVD (chemical vapor deposition) method. In other words, in the etching process of the via, the etching rate is high, so that an etch profile as shown in FIG. Such defects occur more frequently because the process margin is reduced in the 0.15㎛ class.
비아의 크기는 디자인 룰 스트린크(design rule shrink)에 따라 줄어드는 반면, 층간의 정전용량 증가를 억제하기 위해서 절연층의 두께는 줄일수없다. 이로인해, 미스얼라인(misalign)에 의한 에치프로파일과 같은 불량은 제어하기가 힘들어진다. 또한, 이러한 불량은 전체 칩내의 불특정 다수지역에서 발생되므로 라인모니터링의 문제점도 크다. 이는 백엔드 공정에서의 불량을 모니터링하는 장비가 실제 진행되는 칩내의 불량 포인트를 찾아내는 능력이 낮기 때문이다.While the via size decreases with design rule shrink, the thickness of the insulating layer cannot be reduced in order to suppress the increase in capacitance between the layers. As a result, defects such as etch profiles due to misalignment become difficult to control. In addition, since such defects occur in an unspecified number of regions within the entire chip, the problem of line monitoring is also great. This is because equipment that monitors defects in the back-end process is less capable of finding defect points in the chip that are actually going on.
도1a내지 도1b 는 종래의 보더리스비아가 형성되는 공정을 나타낸 공정 단면도이다.1A to 1B are cross-sectional views illustrating a process of forming a conventional borderless via.
도1a에서와 같이, 기판(10)상에 금속을 증착하여 금속층을 형성하고 포토리소그래피 방법으로 패터닝하여 금속배선(12)을 형성한후, 금속배선이 형성된 기판(10)전면에 SOG방식으로 유전체를 증착하여 배선절연층(13)을 형성한다.As shown in FIG. 1A, a metal layer is formed by depositing a metal on the substrate 10 and patterned by a photolithography method to form the metal wiring 12, and then a SOG dielectric on the entire surface of the substrate 10 on which the metal wiring is formed. Is deposited to form the wiring insulation layer 13.
그리고 제1층간절연층상에 PE-TEOS를 증착하여 층간절연층(14)을 형성한다.Then, PE-TEOS is deposited on the first interlayer insulating layer to form the interlayer insulating layer 14.
도1b에서와 같이, 층간절연층(14)을 패터닝하여 포토리소그래피 방법으로 금속배선(12)의 상부가 노출될때까지 식각하여 비아홀(16)을 형성한다.As shown in FIG. 1B, the interlayer insulating layer 14 is patterned and etched until the upper portion of the metal wiring 12 is exposed by photolithography to form a via hole 16.
이때, 형성된 비아홀(16)은 금속배선(12)의 측벽부분의 배선절연층(13)이 과식각되어있다.At this time, in the formed via hole 16, the wiring insulation layer 13 of the sidewall portion of the metal wiring 12 is overetched.
따라서, 본 발명은 금속배선 형성방법에 관한 것으로 특히, SOG방식으로 형성한 절연층상에 식각정지층을 형성하여 비아공정 불량을 개선시키기 위해 제안된 금속배선 형성방법이다.Accordingly, the present invention relates to a metal wiring forming method, and in particular, a metal wiring forming method proposed to improve the defect of the via process by forming an etch stop layer on the insulating layer formed by the SOG method.
상기 목적들을 달성하기 위한 본 발명에 따른 반도체장치의 금속배선 형성 방법은 기판상에 금속층을 형성한후 패터닝하여 금속배선을 형성하는 제1단계와; 상기 금속배선이 형성된 기판전면에 배선절연층을 형성한후 마스크없이 에치백하여 금속배선상부를 노출하는 제2단계와; 상기 노출된 금속배선상에 식각정지층, 층간절연층, 상부절연층을 순차적으로 증착하여 형성하는 제3단계와; 상기 상부절연층상에 CMP를 진행한후, 패터닝하여 비아홀을 형성하는 제4단계를 포함하여 이루어진다.According to another aspect of the present invention, there is provided a method of forming a metal wiring in a semiconductor device, the method including: forming a metal layer on a substrate and then patterning the metal wiring to form a metal wiring; Forming a wiring insulation layer on the entire surface of the substrate on which the metal wiring is formed, and then etching back without a mask to expose the upper portion of the metal wiring; A third step of sequentially depositing an etch stop layer, an interlayer insulating layer, and an upper insulating layer on the exposed metal wiring; And performing a CMP on the upper insulating layer and patterning the via holes to form via holes.
도1a 내지 도1b는 종래의 보더리스비아가 형성되는 공정을 나타낸 공정 단면도1A to 1B are cross-sectional views illustrating a process of forming a conventional borderless via.
도2a 내지 도2d는 본 발명에 따른 반도체장치의 배선 형성방법을 도시한 공정 단면도2A to 2D are cross sectional views showing a wiring forming method of a semiconductor device according to the present invention.
*도면의 주요 부분에 대한 부호의 설명 *Explanation of symbols on the main parts of the drawings
30. 기판 32. 금속배선30. Substrate 32. Metallization
34. 배선절연층 36. 식각정지층34. Wiring insulation layer 36. Etch stop layer
38. 층간절연층 40. 상부절연층38. Interlayer insulation layer 40. Upper insulation layer
42. 비아홀42. Via Hole
이하, 첨부한 도면을 참조하여 본 발명을 상세히 설명한다.Hereinafter, the present invention will be described in detail with reference to the accompanying drawings.
도2a내지 2d는 본 발명에 따른 반도체장치의 배선 형성방법을 도시한 공정 단면도이다.2A to 2D are cross-sectional views illustrating a method of forming wirings in a semiconductor device according to the present invention.
본 발명은 먼저, 도 2a에서와 같이, 기판(30)상에 도전물질 즉 주로 금속인 알루미늄, 구리등을 CVD방법이나, 스퍼터링 방법등으로 증착하여 제1금속층(도시되지 않음)을 형성하고 제1 금속층을 포토리소그래피방법으로 패터닝하여 금속배선(32)을 형성한다First, as shown in FIG. 2A, a first metal layer (not shown) is formed by depositing a conductive material, that is, mainly aluminum, copper, or the like, on a substrate 30 by a CVD method or a sputtering method. 1 metal layer is patterned by photolithography method to form metal wiring 32
기판(30)은 회로소자들이 이미 형성된 것을 사용하여 그 위에 배선을 형성하는 것이거나 또는 먼저 배선부터 형성하고 그위에 회로소자들을 형성하는 것이어도 된다.The substrate 30 may be formed by using circuits on which circuit elements have already been formed, or may be formed by first forming wirings and forming circuit elements thereon.
도2b 에서와 같이, 금속배선(32)이 형성된 기판(30)전면에 SOG방식으로 유전체를 증착하여 배선절연층(34)을 형성한후 배선절연층(34)을 금속배선의 표면이 노출될때까지 마스크없이 에치백한다.As shown in FIG. 2B, when the dielectric layer is deposited on the entire surface of the substrate 30 on which the metal wiring 32 is formed by forming a wiring insulating layer 34 by the SOG method, the surface of the metal wiring is exposed to the wiring insulating layer 34. Etch back without mask.
도2c 에서와 같이, 금속배선(32)이 노출된 기판(30)전면에 PECVD(plasma enchaned chemical vapor deposition)방식으로 질화실리콘(silicon nitride)을 증착하여 식각정지층(36)을 형성한다.As shown in FIG. 2C, an etch stop layer 36 is formed by depositing silicon nitride on the entire surface of the substrate 30 on which the metal wiring 32 is exposed by plasma-enchaned chemical vapor deposition (PECVD).
이때, 질화실리콘은 SiH4/NH3를 반응물질로 사용하며 금속배선(32)이 노출된 기판(30)전면에 증착하여 500Å정도의 두께로 식각정지층(36)을 형성한다. 또한, 식각정지층은 산화실리콘(silicon oxide)으로 형성하여도 무방하며 이때, 산화실리콘은 TEOS 또는 SiH4/N2O를 반응물질로 사용하며 500-1000Å정도의 두께로 식각정지층(36)을 형성한다.In this case, the silicon nitride is SiH 4 / NH 3 as a reaction material and is deposited on the entire surface of the substrate 30 exposed the metal wiring 32 to form an etch stop layer 36 to a thickness of about 500Å. In addition, the etch stop layer may be formed of silicon oxide (silicon oxide), wherein the silicon oxide uses TEOS or SiH 4 / N 2 O as a reaction material, the etch stop layer 36 to a thickness of about 500-1000Å To form.
산화실리콘가 질화실리콘보다 더 두껍게 형성하는 것은 산화실리콘이 질화실리콘보다 식각선택비가 낮기 때문이다.Silicon oxide is formed thicker than silicon nitride because silicon oxide has a lower etching selectivity than silicon nitride.
도2d에서와 같이, 다시 식각정지층(36)상에 SOG방식으로 유전체를 증착하여 층간절연층(38)을 형성한후 층간절연층(38)상에 SiO2막을 증착하여 상부절연층(40)(top dielectric)을 형성한다. 그리고, 상부절연층(40)상에 CMP(chemical mechanical polishing)를 진행하여 평탄화한후 포토리소그래피방법으로 패터닝하여 상부절연층(40), 층간절연층(38), 식각정지층(36)을 순차적으로 식각하여 비아홀(42)을 형성한다. 식각정지층이 형성되지 않았을때는 SOG방식으로 형성한 절연층의 식각선택비가 낮아 식각속도의 조절이 어려워 과식각을 피하기 어려웠으나 본 발명에 따른 식각선택비가 높은 물질을 식각정지층(36)으로 형성함으로 인해 금속배선 측벽주위의 SOG 방식으로 형성한 절연층이 과식각되는 현상이 발생되지 않는다.As shown in FIG. 2D, a dielectric layer is deposited on the etch stop layer 36 by SOG to form an interlayer dielectric layer 38, and then an SiO 2 film is deposited on the interlayer dielectric layer 38 to form an upper dielectric layer 40. to form a top dielectric. In addition, the CMP (chemical mechanical polishing) is performed on the upper insulating layer 40 and planarized, and then patterned by a photolithography method to sequentially process the upper insulating layer 40, the interlayer insulating layer 38, and the etch stop layer 36. Etching to form a via hole (42). When the etch stop layer was not formed, the etching selectivity of the insulating layer formed by the SOG method was difficult to control the etch rate because it is difficult to control the etching rate, but the material having the high etch selectivity according to the present invention is formed as the etch stop layer 36. Therefore, the phenomenon in which the insulating layer formed by the SOG method around the metal wiring sidewall is not etched does not occur.
배선절연층 및 층간절연층에 사용된 절연체는 하부 금속배선과 상부 금속배선 간의 정전용량이 증가되는 것을 억제하기 위하여 비유전상수가 낮은 유전체를 사용한다. 비유전상수가 낮은 유전체를 사용하여 신호전달지연(signal propagation delay)이 감소되는 것을 최소화한다.Insulators used in the wiring insulating layer and the interlayer insulating layer use a dielectric having a low dielectric constant to suppress an increase in capacitance between the lower metal wiring and the upper metal wiring. The use of low dielectric constant dielectrics minimizes signal propagation delay.
식각정지층이 형성되지 않았을때는 SOG방식으로 형성한 절연층의 식각선택비가 낮아 식각속도를 조절하기 힘들어 과식각을 피하기 어려웠으나 본 발명에 따른 식각선택비가 높은 물질을 식각정지층으로 형성함으로 인해 금속배선 측벽주위의 SOG 방식으로 형성한 절연층이 과식각되는 현상이 발생되지 않는다. 식각정지층이 형성되어 금속배선간의 절연층이 과도식각되지 않으므로 비아저향의 감소, 비아연결성의 불량등을 줄일수있으므로 공정의 신뢰성을 높인다.When the etch stop layer was not formed, it was difficult to control the etch rate because the etch selectivity of the insulating layer formed by the SOG method was low, but it was difficult to avoid over-etching. The phenomenon that the insulating layer formed by the SOG method around the wiring sidewall is overetched does not occur. Since the etch stop layer is formed so that the insulating layer between the metal wires is not over-etched, it is possible to reduce via deflection and poor via connectivity, thereby improving process reliability.
Claims (7)
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| KR1020010031244A KR20020092570A (en) | 2001-06-04 | 2001-06-04 | Method of a via hole of semiconductor device |
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| KR1020010031244A KR20020092570A (en) | 2001-06-04 | 2001-06-04 | Method of a via hole of semiconductor device |
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