KR20020083034A - Forming method of interlayer flat structure in semiconductor device - Google Patents

Forming method of interlayer flat structure in semiconductor device Download PDF

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KR20020083034A
KR20020083034A KR1020010022306A KR20010022306A KR20020083034A KR 20020083034 A KR20020083034 A KR 20020083034A KR 1020010022306 A KR1020010022306 A KR 1020010022306A KR 20010022306 A KR20010022306 A KR 20010022306A KR 20020083034 A KR20020083034 A KR 20020083034A
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film
metal
interlayer
insulating film
metal pattern
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KR1020010022306A
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Korean (ko)
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KR100406731B1 (en
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이대근
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아남반도체 주식회사
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H01L21/76829—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing characterised by the formation of thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers
    • H01L21/76834—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing characterised by the formation of thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers formation of thin insulating films on the sidewalls or on top of conductors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H01L21/76819—Smoothing of the dielectric

Abstract

PURPOSE: A method for planarizing inter-metal layers of a semiconductor device is provided to reduce via resistance and to improve film properties of the interlayer dielectric by forming a spacer made of inorganic insulating material at both sidewalls of metal patterns. CONSTITUTION: The first interlayer dielectric(12) having contact pads(13) is formed on a semiconductor substrate(10) having a transistor. A plurality metal patterns(15) are formed to connect with the contact pads(13). Spacers made of an inorganic insulating material are formed at both sidewalls of the metal patterns(15), thereby locally planarizing portions(51,52,53) between the metal patterns without using TEOS processing. Then, the second interlayer dielectric is deposited on the resultant structure and planarized.

Description

반도체 소자의 층간막 평탄화 구조의 형성 방법 {FORMING METHOD OF INTERLAYER FLAT STRUCTURE IN SEMICONDUCTOR DEVICE}Formation method of interlayer film planarization structure of semiconductor device {FORMING METHOD OF INTERLAYER FLAT STRUCTURE IN SEMICONDUCTOR DEVICE}

본 발명은 반도체 소자의 층간막 평탄화 구조 형성 방법에 관한 것이다.The present invention relates to a method for forming an interlayer film planarization structure of a semiconductor device.

반도체 소자의 제조 공정에서 반도체 기판 위에 한 층만의 배선을 형성하는 경우에는 배선 패턴 설계상의 자유도가 작아 실질적인 배선이 길어짐으로써 웨이퍼 내 반도체 소자의 레이아웃에도 큰 제약이 가해진다.When only one layer of wiring is formed on the semiconductor substrate in the manufacturing process of the semiconductor device, the degree of freedom in designing the wiring pattern is small, and thus the actual wiring is long, which places a significant limitation on the layout of the semiconductor device in the wafer.

이에 반해, 금속 배선을 다층화하면 아주 효율이 높은 설계가 가능하다. 즉, 반도체 칩 위에 배선을 통과시키는 스페이스를 고려하지 않고 각 반도체 소자가 레이아웃되기 때문에 집적도 및 밀도가 향상되어 반도체 칩 사이즈를 축소할 수 있다. 그리고, 배선의 자유도가 증가하고, 패턴 설계가 용이해짐과 함께 배선 저항이나 전류 용량 등의 설정을 여유를 가지고 할 수 있게 된다.On the other hand, if the metal wiring is multilayered, a very efficient design is possible. That is, since each semiconductor element is laid out without considering a space for allowing wiring to pass on the semiconductor chip, the degree of integration and density can be improved and the size of the semiconductor chip can be reduced. This increases the degree of freedom in wiring, facilitates pattern design, and allows setting of wiring resistance, current capacity, and the like with a margin.

이러한 금속 배선의 다층화에서는 금속 배선층과 금속 배선층 사이의 전기적절연을 위한 층간 절연막 표면의 요곡이 심해짐에 따라 표면에서의 배선의 오픈이나 쇼트 등이 발생하게 되는 데, 이를 방지하기 위하여 층간 절연막을 평탄화하고 있다.In the multilayering of the metal wirings, as the curvature of the interlayer insulating film surface for electrical insulation between the metal wiring layer and the metal wiring layer becomes deeper, opening or shorting of the wirings on the surface occurs. Doing.

층간 절연막의 평탄화를 위하여 금속 배선층 형성을 위한 금속 박막 패턴이 형성된 하부 박막 상부에 TEOS(tetraethylorthosilicate)를 이용하여 평탄화 정도가 양호한 산화막을 형성하여 층간 절연막을 형성하고 있다.In order to planarize the interlayer insulating film, an oxide film having a good degree of planarization is formed by using tetraethylorthosilicate (TEOS) on the lower thin film on which the metal thin film pattern for forming the metal wiring layer is formed.

이 경우, 콘택(contact)이 형성된 하부 절연막 상부에 금속 박막을 증착하고 패터닝(patterning)하여 금속 배선층을 형성한 후, 금속 박막 패턴을 포함한 하부 절연막 상부에 TEOS를 이용하여 산화막을 증착한다. 이 때, TEOS는 후술되는 SOG 또는, USG에 의한 금속 패턴의 손상을 방지하기 위하여 형성된다.In this case, a metal thin film is deposited on the lower insulating film on which the contact is formed and patterned to form a metal wiring layer, and then an oxide film is deposited on the lower insulating film including the metal thin film pattern using TEOS. At this time, TEOS is formed in order to prevent damage of the metal pattern by SOG or USG mentioned later.

그리고, 금속 박막 패턴에 의한 지역적인 단차를 최소화하기 위하여 각 금속 박막 패턴 사이의 갭(gap)에 SOG(spin on glass), USG(un-doped silicate glass) 등을 충진한다. 이어, 하부 절연막 상부 전면에 재차 TEOS에 의해 산화막을 증착하고 화학 기계적 연마 공정(chemical mechanical polishing)에 의해 평탄화함으로써 층간 절연막을 완성한다.In addition, in order to minimize local steps due to the metal thin film pattern, a gap on each metal thin film pattern is filled with a spin on glass (SOG), an un-doped silicate glass (USG), or the like. Subsequently, an oxide film is deposited on the entire upper surface of the lower insulating film by TEOS and planarized by chemical mechanical polishing to complete the interlayer insulating film.

이와 같이, 금속 패턴간 부분의 지역적인 평탄화를 위하여 수분 함량이 높은 SOG, USG 등을 각 금속 박막 패턴 사이 갭에 충진하는 공정을 진행한다. 그러나, 이러한 기술은 후속 접촉 구멍의 식각 후 베리어 메탈(barrier metal)을 증착하는 공정에서 SOG, USG 등에서 발생하는 수분 등에 의해 베리어 메탈이 제대로 증착되지 않거나 수분에 대한 부식 등에 의해 접촉 저항이 높게 되거나, 구형 미립자가생기는 등의 SOG막 또는, USG막의 막불량을 유발한다.As such, the process of filling the gap between the metal thin film patterns with SOG and USG having a high moisture content is performed in order to planarize the region between the metal patterns. However, such a technique is that the barrier metal is not properly deposited due to moisture generated in SOG, USG, etc. in the process of depositing a barrier metal after etching the subsequent contact hole, or the contact resistance is high due to corrosion to moisture, or the like. Spherical microparticles | fine-particles generate | occur | produce a film defect of an SOG film | membrane, such as USG film | membrane, or the like.

본 발명은 층간막의 막특성이 향상되는 반도체 소자의 층간막 평탄화 구조 형성 방법을 제공하고자 한다.The present invention is to provide a method for forming an interlayer film planarization structure of a semiconductor device in which the film properties of the interlayer film are improved.

도 1a부터 도 1d는 본 발명의 실시예에 따른 반도체 소자의 층간막 평탄화 구조를 형성하기 위한 공정도이다.1A to 1D are process diagrams for forming an interlayer film planarization structure of a semiconductor device according to an embodiment of the present invention.

이러한 기술적 과제를 해결하기 위하여, 본 발명에서는 금속 패턴과 금속 패턴 사이의 갭에 충진되는 층간막을 무기 절연 물질로 형성한다.In order to solve this technical problem, in the present invention, an interlayer film filled in the gap between the metal pattern and the metal pattern is formed of an inorganic insulating material.

상세하게, 본 발명에 따른 반도체 소자의 층간막 평탄화 구조를 형성하기 위하여, 콘택 또는 비아를 포함하는 반도체 기판 상부에 상기 콘택 또는 비아에 접속되는 다수개의 금속 패턴을 형성하고, 금속 패턴을 포함하는 반도체 기판 상부에 절연막을 증착한다. 이어, 절연막을 에치백하여 금속 패턴 측벽에 스페이서를 형성한 후, 스페이서 및 금속 패턴을 포함하는 반도체 기판 상부에 층간막을 증착하고 평탄화한다.Specifically, in order to form the interlayer film planarization structure of the semiconductor device according to the present invention, a plurality of metal patterns connected to the contacts or vias are formed on the semiconductor substrate including the contacts or vias, and the semiconductor includes a metal pattern. An insulating film is deposited on the substrate. Subsequently, the insulating layer is etched back to form a spacer on the metal pattern sidewall, and then an interlayer film is deposited and planarized on the semiconductor substrate including the spacer and the metal pattern.

여기서, 절연막의 증착은 금속 패턴 사이의 최소 간격 갭을 채우도록 하는 것이 바람직하다. 이 때, 절연막은 산화막 또는, 질화막으로 형성할 수 있고, 절연막의 에치백은 금속 패턴의 상단이 드러날 때를 에치백의 정지점으로 설정할 수 있다. 또한, 절연막을 에치백하는 과정에서, 절연막이 금속 패턴과 평탄화가 되는 정도로 식각되도록 에치백 시간을 설정할 수 있다.Here, the deposition of the insulating film preferably fills the minimum gap gap between the metal patterns. At this time, the insulating film can be formed of an oxide film or a nitride film, and the etchback of the insulating film can be set as the stop point of the etchback when the upper end of the metal pattern is exposed. In addition, in the process of etching back the insulating film, the etch back time may be set so that the insulating film is etched to the extent that the insulating film is planarized.

이하, 첨부된 도면을 참조하여 본 발명을 상세히 설명한다.Hereinafter, with reference to the accompanying drawings will be described in detail the present invention.

도 1a부터 도 1d는 본 발명의 실시예에 따른 반도체 소자의 층간막 평탄화구조를 형성하기 위한 공정도이다.1A to 1D are process diagrams for forming an interlayer film planarization structure of a semiconductor device according to an embodiment of the present invention.

우선, 도 1a에 도시한 바와 같이, 반도체 소자(11)가 형성된 반도체 기판(10)에 BPSG(borophosphosilicate glass) 등을 사용하여 평탄화된 제1 절연막(12)을 형성한다. 이어, 제1 절연막(12)을 선택적으로 제거한 후, 제거된 부분에 반도체 기판(10)의 소자 전극과 이후에 설명될 금속 패턴을 전기적으로 접속하기 위한 접촉 패턴(13)을 형성한다.First, as shown in FIG. 1A, a planarized first insulating film 12 is formed on a semiconductor substrate 10 on which the semiconductor element 11 is formed using BPSG (borophosphosilicate glass) or the like. Subsequently, after the first insulating film 12 is selectively removed, a contact pattern 13 for electrically connecting the element electrode of the semiconductor substrate 10 and the metal pattern to be described later is formed in the removed portion.

다음, 도 1b에 도시한 바와 같이, 접촉 패턴(13) 및 절연막(12) 상부 전면에 금속 배선층 형성을 위한 금속 박막을 형성하고, 패터닝하여 회로 형성을 위한 금속 패턴(15)을 형성한다. 금속 패턴(15)은 하부에 위치하는 반도체 소자(11)와 전기적으로 연결된다.Next, as shown in FIG. 1B, a metal thin film for forming a metal wiring layer is formed on the entire upper surface of the contact pattern 13 and the insulating layer 12, and patterned to form a metal pattern 15 for forming a circuit. The metal pattern 15 is electrically connected to the semiconductor element 11 disposed below.

이어, 금속 패턴(15)을 포함하는 기판 전면에 산화막 또는 질화막과 같은 제2 절연막(16)을 형성한다. 이 때, 제2 절연막(16)의 두께는 금속 패턴(15)과 금속 패턴(15) 사이의 간격(이하, 금속 패턴간 간격)이 가장 작은 부분은 완전히 메워질 정도로 산화막 또는 질화막을 증착하여 설정하는 것이 바람직하다.Next, a second insulating film 16 such as an oxide film or a nitride film is formed on the entire surface of the substrate including the metal pattern 15. In this case, the thickness of the second insulating layer 16 is set by depositing an oxide film or a nitride film so that the portion having the smallest gap between the metal pattern 15 and the metal pattern 15 (hereinafter, the metal pattern gap) is completely filled. It is desirable to.

설명의 편의를 위하여, 금속 패턴간 부분을 각각 제1, 제2 및 제3 금속 패턴간 부분(51, 52, 53)이라 각각 지칭할 때, 제3 금속 패턴간 부분(53)이 나머지 제1 및 제2 금속 패턴간 부분(51, 52)보다 금속 패턴간 간격이 작다고 하면, 제2 절연막(16)은 제3 금속 패턴간 부분(53)을 충분히 채울 수 있는 정도의 두께로 형성하는 것이 바람직하다.For convenience of description, when the intermetallic portions are referred to as first, second, and third intermetallic portions 51, 52, and 53, respectively, the third intermetallic portion 53 is the remaining first intermetallic portion. And when the distance between the metal patterns is smaller than that between the second metal inter-pattern portions 51 and 52, the second insulating film 16 may be formed to a thickness sufficient to sufficiently fill the third inter-pattern portions 53. Do.

다음, 도 1c에 도시한 바와 같이, 제2 절연막(16)을 에치백한다. 이 때,제2 절연막의 에치백의 에치 정지점은 금속 패턴(15)의 상단에서 식각정지점을 검출(detect)하면서 정하거나, 제2 절연막의 두께를 감안하여 금속 패턴(15) 상부에서 에치가 정지되도록 식각 시간을 정하여 설정할 수 있다.Next, as shown in FIG. 1C, the second insulating film 16 is etched back. At this time, the etch stop point of the etch back of the second insulating film is determined while detecting an etch stop point at the upper end of the metal pattern 15, or the etch stop is formed on the upper portion of the metal pattern 15 in consideration of the thickness of the second insulating film. You can set the etching time to stop.

이 과정에서, 금속 패턴간 간격이 가장 좁은 제3 금속 패턴간 부분(53)에는 제2 절연막(16)이 채워져서 금속 패턴(15)과 평평한 상단을 유지하게 되며, 금속 패턴간 간격이 가장 넓은 제1 및 제2 금속 패턴간 부분(51, 52)에는 양쪽 금속 패턴에 제2 절연막의 일부가 남아 측벽 스페이서가 된다.In this process, the third inter-pattern portion 53 having the smallest gap between the metal patterns is filled with the second insulating layer 16 to maintain a flat top with the metal pattern 15, and the gap between the metal patterns is widest. A portion of the second insulating film remains on both metal patterns in the first and second metal pattern portions 51 and 52 to form sidewall spacers.

여기서, 제2 절연막은 산화막 또는 질화막과 같은 무기 절연막으로 형성하는 것이 바람직하다. 이와 같이 본 발명에서는, 무기 절연막으로 금속 패턴 측벽에 스페이서를 형성하여 금속 패턴간 부분을 지역적 평탄화하고 후속 공정에서 층간 절연막을 형성하기 때문에, 무기 절연막이 아닌 수분 함량이 높은 SOG막 또는, USG막을 사용함으로써 야기되는 막불량 및 접촉 불량을 방지할 수 있다. 또한, 본 발명에서는, 금속 패턴(15)을 형성한 후에, 금속 패턴간 부분(51, 52, 53)에 형성되는 절연막(16, 17)을 SOG 또는, USG로 형성하지 않기 때문에 SOG 또는, USG로 야기되는 금속 패턴의 손상을 방지하기 위한 TEOS 형성 공정을 생략할 수 있어서, 공정을 단순화할 수 있다.Here, the second insulating film is preferably formed of an inorganic insulating film such as an oxide film or a nitride film. As described above, in the present invention, since the spacers are formed on the metal pattern sidewalls with the inorganic insulating film to locally planarize the portions between the metal patterns, and the interlayer insulating film is formed in the subsequent step, the SOG film or the USG film having a high moisture content is used instead of the inorganic insulating film. This can prevent film defects and poor contact caused. In the present invention, since the insulating films 16 and 17 formed on the intermetallic portions 51, 52 and 53 are not formed of SOG or USG after the metal pattern 15 is formed, SOG or USG The TEOS forming process for preventing damage to the metal pattern caused by the process can be omitted, thereby simplifying the process.

다음, 도 1d에 도시한 바와 같이, 측벽 스페이서를 포함한 금속 패턴(15) 및 제2 절연막(16)의 상부 전면에 TEOS를 사용하여 산화막(19)을 형성하고, 화학 기계적 연마 공정(chemical mechanical polishing)에 의해 평탄화한다.Next, as illustrated in FIG. 1D, an oxide film 19 is formed on the upper surface of the metal pattern 15 including the sidewall spacers and the second insulating film 16 using TEOS, and a chemical mechanical polishing process is performed. Planarization by

이후, 평탄화된 산화막(19)에 금속 패턴(15)을 드러내는 홀(20)을 형성하고,이 홀(20)에 금속 패턴(15)과 이후에 형성될 또 다른 금속 패턴(도면 미표시)을 연결하는 접촉 패턴(도면 미표시)을 형성하는 등의 후속 공정을 진행한다.Thereafter, a hole 20 exposing the metal pattern 15 is formed in the planarized oxide film 19, and the metal pattern 15 and another metal pattern to be formed later (not shown) are connected to the hole 20. Subsequent processes, such as forming a contact pattern (not shown), are performed.

상술한 바와 같이, 본 발명에서는 금속 패턴의 측벽에 무기 절연 물질로 스페이서를 형성하여 지역적 평탄화함으로써, 수분 함량이 높은 SOG막 또는, USG막을 사용하는 종래 기술과 비교하여, 후속막의 증착 불량 및 비아 저항을 감소시킬 수 있으며, 금속 패턴간 부분을 채우는 층간막의 막특성을 향상시킬 수 있다. 또한, 금속 패턴을 형성한 후에, 금속 패턴간 부분에 형성되는 절연막을 SOG 또는, USG로 형성하지 않기 때문에 SOG 또는, USG로 야기되는 금속 패턴의 손상을 방지하기 위한 TEOS 형성 공정을 생략할 수 있어서, 공정을 단순화할 수 있다.As described above, in the present invention, by forming a spacer with an inorganic insulating material on the sidewall of the metal pattern and locally planarizing, the deposition defect and the via resistance of the subsequent film are higher than those of the prior art using the SOG film having the high moisture content or the USG film. Can be reduced, and the film properties of the interlayer film filling the intermetallic portions can be improved. In addition, after forming the metal pattern, since the insulating film formed in the intermetallic portion is not formed of SOG or USG, the TEOS forming step for preventing damage to the SOG or metal pattern caused by USG can be omitted. The process can be simplified.

Claims (5)

콘택 또는 비아를 포함하는 반도체 기판 상부에 상기 콘택 또는 비아에 접속되는 다수개의 금속 패턴을 형성하는 단계,Forming a plurality of metal patterns connected to the contacts or vias on the semiconductor substrate including the contacts or vias, 상기 금속 패턴을 포함하는 반도체 기판 상부에 절연막을 증착하는 다나계,Dana system for depositing an insulating film on the semiconductor substrate including the metal pattern, 상기 절연막을 에치백하여 상기 금속 패턴 측벽에 스페이서를 형성하는 단계.Etching back the insulating layer to form a spacer on the sidewall of the metal pattern. 상기 스페이서 및 금속 패턴을 포함하는 반도체 기판 상부에 층간막을 증착하고 평탄화하는 단계Depositing and planarizing an interlayer film on the semiconductor substrate including the spacer and the metal pattern 를 포함하는 반도체 소자의 층간막 평탄화 구조의 형성 방법.Method of forming an interlayer film planarization structure of a semiconductor device comprising a. 제1항에서,In claim 1, 상기 절연막의 증착은 상기 금속 패턴 사이의 최소 간격 갭을 채우도록 하는 반도체 소자의 층간막 평탄화 구조의 형성 방법.And depositing the insulating layer to fill the minimum gap gap between the metal patterns. 제1항 또는, 제2항에서,The method according to claim 1 or 2, 상기 절연막은 산화막 또는, 질화막으로 형성하는 반도체 소자간 층간막 평탄화 구조의 형성 방법.And the insulating film is an oxide film or a nitride film. 제3항에서,In claim 3, 상기 절연막의 에치백은 상기 금속 패턴의 상단이 드러날 때를 에치백의 정지점으로 설정하는 반도체 소자간 층간막 평탄화 구조의 형성 방법.The method of forming the interlayer interlayer film planarization structure of the interlayer film between the etchback of the insulating layer is set when the upper end of the metal pattern is exposed to the stop point of the etchback. 제3항에서,In claim 3, 상기 절연막을 에치백하는 과정에서, 상기 절연막이 상기 금속 패턴과 평탄화가 되는 정도로 식각되도록 에치백 시간을 설정하여 반도체 소자간 층간막 평탄화 구조의 형성 방법.In the process of etching back the insulating film, a method of forming an interlayer semiconductor film planarizing structure by setting the etch back time so that the insulating film is etched to the extent that the insulating film is planarized.
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USRE46398E1 (en) 2007-04-13 2017-05-09 Lg Electronics Inc. Digital broadcasting system and data processing method
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