KR20020059469A - 기판과 컨택 패드간의 컨택 저항을 줄인 컨택 구조체 및그 형성방법 - Google Patents
기판과 컨택 패드간의 컨택 저항을 줄인 컨택 구조체 및그 형성방법 Download PDFInfo
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76897—Formation of self-aligned vias or contact plugs, i.e. involving a lithographically uncritical step
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
- H01L21/283—Deposition of conductive or insulating materials for electrodes conducting electric current
- H01L21/285—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation
- H01L21/28506—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers
- H01L21/28512—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers on semiconductor bodies comprising elements of Group IV of the Periodic Table
- H01L21/28525—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers on semiconductor bodies comprising elements of Group IV of the Periodic Table the conductive layers comprising semiconducting material
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
- H01L21/76895—Local interconnects; Local pads, as exemplified by patent document EP0896365
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
- H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
- H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
- H01L21/8232—Field-effect technology
- H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
- H01L21/823418—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type with a particular manufacturing method of the source or drain structures, e.g. specific source or drain implants or silicided source or drain structures or raised source or drain structures
- H01L21/823425—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type with a particular manufacturing method of the source or drain structures, e.g. specific source or drain implants or silicided source or drain structures or raised source or drain structures manufacturing common source or drain regions between a plurality of conductor-insulator-semiconductor structures
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
- H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
- H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
- H01L21/8232—Field-effect technology
- H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
- H01L21/823475—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type interconnection or wiring or contact manufacturing related aspects
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- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
- Insulated Gate Type Field-Effect Transistor (AREA)
Abstract
Description
Claims (12)
- 소정 간격으로 이격된 두 게이트 패턴 사이의 기판의 소정 소스/드레인 영역과 상부 도전층을 연결하는 컨택 구조체에 있어서,상기 각 게이트 패턴의 측벽에 형성되고, 상기 기판에 접하는 부위에서 상기 각 게이트 패턴 양쪽으로 소정 길이로 연장되며, 상기 두 게이트 패턴 사이의 기판의 소스/드레인 영역을 소정 폭으로 노출하는 절연막;상기 노출된 소스/드레인 영역의 표면으로부터 상기 절연막의 두께보다는 두껍게 형성되고, 그 측벽이 상기 절연막이 게이트 패턴 양쪽으로 연장된 상기 소정 길이만큼 상기 절연막의 측벽과 이격된, 상기 기판과 동일한 물질로 에피택셜 성장된 하부 패드층; 및상기 절연막과 하부 패드층에 의해 한정되는 상기 두 게이트 패턴 사이의 영역을 메우는 도전물질로 이루어진 상부 도전층을 포함하는 것을 특징으로 하는 컨택 구조체.
- 제1항에 있어서, 상기 하부 패드층은 상부 표면 중앙에서 리세스된 것을 특징으로 하는 컨택 구조체.
- 제1항에 있어서, 상기 상부 도전층을 이루는 도전물질은 불순물이 고농도로 도핑된 다결정 실리콘인 것을 특징으로 하는 컨택 구조체.
- 제1항에 있어서, 상기 상부 도전층을 이루는는 도전물질은 금속인 것을 특징으로 하는 컨택 구조체.
- 제4항에 있어서,상기 하부 패드층과 상부 도전층 사이에 형성된 장벽층을 더 포함하는 것을 특징으로 하는 컨택 구조체.
- 소정 간격으로 이격하여 기판 상에 게이트 절연막을 개재하여 게이트 패턴들을 형성하는 단계;상기 기판 전면에 소정 두께로 제1절연막을 형성하는 단계;상기 기판 전면에 상기 제1절연막과 식각선택비가 있는 물질로 소정 두께의 제2절연막을 형성하는 단계;상기 제2절연막을 이방성 식각하여 상기 제1절연막 측벽에 제2절연막 스페이서를 형성하는 단계;상기 제2절연막 스페이서 사이에 노출된 상기 제1절연막을 식각하여 상기 기판을 노출시키는 단계;상기 노출된 기판 표면으로부터 상기 제1절연막의 두께보다는 두껍게 상기 기판과 동일한 물질을 에피택셜 성장시켜 상기 제2절연막 스페이서에 자기정렬된 하부 패드층을 형성하는 단계;상기 제2절연막 스페이서를 제거하는 단계; 및상기 하부 패드층과 제1절연막에 의해 한정되는 상기 게이트 패턴들 사이의 영역을 도전물질로 메워 상부 도전층을 형성하는 단계를 포함하는 것을 특징으로 하는 컨택 구조체의 형성방법.
- 제6항에 있어서, 상기 하부 패드층을 형성하는 단계와 상기 제2절연막 스페이서를 제거하는 단계 사이에,상기 하부 패드층이 형성된 결과물 상에 제3절연막을 형성하고 이방성 식각하여 상기 제2절연막 스페이서 측벽에 제3절연막 스페이서를 형성하는 단계;상기 제3절연막 스페이서를 식각마스크로 하여 상기 하부 패드층을 소정 깊이로 식각하여, 상기 하부 패드층을 상부 표면 중앙에서 리세스시키는 단계; 및상기 제3절연막 스페이서를 제거하는 단계를 더 포함하는 것을 특징으로 하는 컨택 구조체의 형성방법.
- 제7항에 있어서, 상기 제3절연막은 상기 제2절연막과 동일한 물질로 이루어지고, 상기 제3절연막 스페이서를 제거하는 단계와 상기 제2절연막 스페이서를 제거하는 단계는 동일한 식각 공정으로 연속하여 수행되는 것을 특징으로 하는 컨택 구조체의 형성방법.
- 제6항에 있어서, 상기 상부 도전층을 형성하는 도전물질은 불순물이 고농도로 도핑된 다결정 실리콘으로 이루어지는 것을 특징으로 하는 컨택 구조체의 형성방법.
- 제6항에 있어서, 상기 상부 도전층을 형성하는 도전물질은 금속으로 이루어지는 것을 특징으로 하는 컨택 구조체의 형성방법.
- 제10항에 있어서, 상기 상부 도전층을 형성하는 단계 이전에,상기 제2절연막 스페이서가 제거된 결과물 상에 장벽층을 형성하는 단계를 더 포함하는 것을 특징으로 하는 컨택 구조체의 형성방법.
- 제6항에 있어서, 상기 제1절연막을 형성하는 단계와 상기 제2절연막을 형성하는 단계 사이에,상기 기판 전면에 상기 게이트 패턴들 사이의 영역을 모두 메우며 덮는 층간절연막을 형성하는 단계; 및상기 게이트 패턴들 사이의 층간절연막을 자기정렬 방식으로 식각하여 상기 제1절연막을 노출하는 컨택홀을 형성하는 단계를 더 포함하는 것을 특징으로 하는컨택 구조체의 형성방법.
Priority Applications (3)
Application Number | Priority Date | Filing Date | Title |
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KR1020010000845A KR100363097B1 (ko) | 2001-01-06 | 2001-01-06 | 기판과 컨택 패드간의 컨택 저항을 줄인 컨택 구조체 및그 형성방법 |
US10/038,967 US6689654B2 (en) | 2001-01-06 | 2002-01-08 | Methods of manufacturing integrated circuit devices having reduced contact resistance between a substrate and a contact pad while maintaining separation of the substrate and the contact pad |
US10/741,751 US7009257B2 (en) | 2001-01-06 | 2003-12-19 | Methods of manufacturing integrated circuit devices having reduced contact resistance between a substrate and a contact pad while maintaining separation of the substrate and the contact pad and integrated circuit devices formed thereby |
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KR1020010000845A KR100363097B1 (ko) | 2001-01-06 | 2001-01-06 | 기판과 컨택 패드간의 컨택 저항을 줄인 컨택 구조체 및그 형성방법 |
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Cited By (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
KR100414947B1 (ko) * | 2001-06-29 | 2004-01-16 | 주식회사 하이닉스반도체 | 반도체 소자의 콘택 플러그 형성 방법 |
KR101414076B1 (ko) * | 2008-09-10 | 2014-07-02 | 삼성전자주식회사 | 반도체 소자 및 이의 제조 방법 |
KR20140111133A (ko) * | 2013-03-07 | 2014-09-18 | 삼성전자주식회사 | 도전성 플러그를 포함하는 반도체 소자 |
Families Citing this family (12)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
KR100506055B1 (ko) * | 2001-12-31 | 2005-08-05 | 주식회사 하이닉스반도체 | 반도체 소자의 트랜지스터 및 그의 제조 방법 |
KR100500473B1 (ko) * | 2003-10-22 | 2005-07-12 | 삼성전자주식회사 | 반도체 소자에서의 리세스 게이트 트랜지스터 구조 및형성방법 |
KR100751580B1 (ko) * | 2004-02-13 | 2007-08-27 | 샌디스크 코포레이션 | 플로팅 게이트들 간의 크로스 커플링을 제한하기 위한 쉴드플레이트 |
US7355237B2 (en) * | 2004-02-13 | 2008-04-08 | Sandisk Corporation | Shield plate for limiting cross coupling between floating gates |
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JP2918278B2 (ja) | 1990-04-11 | 1999-07-12 | 沖電気工業株式会社 | 半導体装置の製造方法 |
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JP3042444B2 (ja) * | 1996-12-27 | 2000-05-15 | 日本電気株式会社 | 半導体装置の製造方法 |
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JP2000269488A (ja) * | 1999-03-15 | 2000-09-29 | Toshiba Corp | 半導体装置の製造方法 |
-
2001
- 2001-01-06 KR KR1020010000845A patent/KR100363097B1/ko active IP Right Grant
-
2002
- 2002-01-08 US US10/038,967 patent/US6689654B2/en not_active Expired - Lifetime
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2003
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Cited By (3)
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KR100414947B1 (ko) * | 2001-06-29 | 2004-01-16 | 주식회사 하이닉스반도체 | 반도체 소자의 콘택 플러그 형성 방법 |
KR101414076B1 (ko) * | 2008-09-10 | 2014-07-02 | 삼성전자주식회사 | 반도체 소자 및 이의 제조 방법 |
KR20140111133A (ko) * | 2013-03-07 | 2014-09-18 | 삼성전자주식회사 | 도전성 플러그를 포함하는 반도체 소자 |
Also Published As
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US20020090786A1 (en) | 2002-07-11 |
KR100363097B1 (ko) | 2002-12-05 |
US20040129981A1 (en) | 2004-07-08 |
US6689654B2 (en) | 2004-02-10 |
US7009257B2 (en) | 2006-03-07 |
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