KR20020056896A - Time-delayed-integration imaging with active pixel sensors - Google Patents

Abstract

The imaging technique and apparatus 100 of the present invention performs time delay integration based on the active pixel sensor 110. The integrator 120 on chip with the active pixel sensor 110 performs correlated double sampling and the signals are summed based on the capacitor switched bank.

Description

Apparatus and method for integrating time delay integrated with an active pixel sensor {TIME-DELAYED-INTEGRATION IMAGING WITH ACTIVE PIXEL SENSORS}

Image sensors are widely used in various fields to generate images of various objects. Imaging circuits often include a two-dimensional array of photosensors designed to generate an output signal in response to photons. Each photosensor may be used to form some or all of one pixel of an image. Individual photosensors can be scanned to read and process output signals for various imaging operations.

One type of solid state image sensor includes an array of active pixel sensors (APS) formed on a semiconductor substrate. APS is an optical sensing device having a sensing circuit in each pixel. Each active pixel includes a sensing element formed in a semiconductor substrate to convert an optical signal into an electronic signal. When photons strike the surface of the photoactive region within each active pixel, free charge carriers are generated and collected. Once collected, the charge carriers are converted into electrical signals within each pixel. Thus, unlike charge coupled device (CCD) or metal oxide semiconductor (MOS) diode arrays, APS devices do not transfer charge from one pixel to another for reading. The APS can convert the photocharge into an electronic signal before transferring the signal to a common conductor that conducts the electronic signal to the output node.

APS devices can be fabricated in a manner compatible with complementary metal oxide semiconductor (CMOS) processes. With compatibility with CMOS processes, multiple signal processing functions and operation controls can be integrated at relatively low cost on an APS chip. CMOS circuits also enable the use of simple power supplies and consequently reduce power consumption. Moreover, the active pixels of the APS device enable nondestructive reading, simplified digital interfaces, and random access.

This application claims priority to a US provisional application filed on October 5, 1999 under the name "LOW POWER ACCURACY TIME-DELAYED-INTERGRATION IMAGER IMPLEMENTATION USING CMOS IMAGING APPROACH."

The invention has been completed by conducting research under a contract with NASA and is subject to the provisions of Public Law 96-517 (35 U.S.C. 202) selected by the contractor to retain rights.

TECHNICAL FIELD The present invention relates to an imaging apparatus and an imaging technique, and more particularly, to an imaging apparatus and an imaging technique based on a semiconductor sensor.

1A is an illustration of time delay integration.

1B illustrates an embodiment of an active pixel sensing device having a time delay integration circuit.

FIG. 1C is a table illustrating the mapping from the sense array to the integrator array for three consecutive frames in the apparatus of FIG. 1B. FIG.

FIG. 2A illustrates one embodiment of a differentially switched capacitor integrator as the building block for the integrator array shown in FIG.

2B is an operation timing diagram of the integrator shown in FIG. 2A.

3A, 3B, 4A, 4B, 5A, and 5B illustrate an embodiment of a capacitor switched integrator based on a fully differential amplifier and respective timing diagrams for operating the switches thereof.

6 illustrates an embodiment of an all-motor amplifier.

7A and 7B show capacitor switched integrators based on a single-ended amplifier.

7C is a timing diagram for operating the switch of the device shown in FIGS. 7A and 7B.

Like reference numerals in the drawings denote like elements.

The present invention includes an imaging device having a light sensing array and an integrator array. The photosensitive array includes sensing pixels arranged in rows and columns. Each pixel includes an optical sensing element that generates charge in response to incident photons from an object, and an in-pixel circuit that converts the charge into an electric pixel signal representing the charge. The integrator array has an integrator arranged in the same number of rows and columns as the photosensitive array. The integrators in each column are combined to receive electrical pixel signals from only one specified column of sensing pixels in the photosensitive array, and time delay integrated signals representing the object after each sensing pixel is sampled and read for the number of rows in the photosensitive array. Can be generated.

Time delay integration is used herein to accumulate electrical output signals sequentially generated by a series of active sense pixels in a CMOS APS array to produce a sum signal. Since the electrical signal constituting the sum signal is obtained by each pixel at different times delayed with respect to each other by a fixed amount of delay time due to the scanning operation, the sum signal is called a "time delay integration" signal.

One example of applying the time delay integration is imaging an object moving relative to the imaging device. In regular "snapshot" imaging operations, the sensing pixel is controlled to collect photons from the object for a given exposure time. Output signals from different pixels are independent of each other and represent different pixels in the output image. When the object and the imaging device are fixed relative to each other, the exposure time can be long to increase the signal to noise ratio by collecting more photons if the object is not bright enough. Alternatively, multiple snapshots may be taken for one scene in a fixed imaging situation. Then, multiple snapshots or frames are simply synthesized together to produce the final image with an improved signal to noise ratio.

However, when the object moves with respect to the imaging device, extended exposure imaging cannot be performed because the exposure time is too long and when photons from one location of the object are collected by two or more adjacent pixels along the relative direction of movement. For example, the captured image may be blurred. Simply synthesizing multiple frames causes blurring problems because different frames are taken at different times and the image of the object moves from one position on the sensing array to another during that time.

The time delay integration of the present invention partially transforms the integration of the plurality of frames to synthesize pixel signals from other sensed pixels in other frames corresponding to the same image to produce a suitably integrated image. At other times, multiple frames are also taken. However, after the other frames are shifted with respect to each other according to the relative direction of movement to account for the movement, the shifted frames are combined together. Thus, imaging blur due to relative movement is reduced to achieve the desired signal to noise ratio in the final integrated image.

1A illustrates the time delay integration technique of capturing images of a ground scene using an imaging array device mounted on an aircraft. Seven consecutive frames photographed by the imaging device are shown. Due to the movement of the aircraft, the ground scene projects at different locations on the imaging array along the direction of travel. However, if the frame is spatially shifted by one pixel between any two consecutive frames, the sensed pixels in other frames with the same terrestrial scene can be aligned and thus synthesized to form a suitable integrated image without blur.

1B illustrates one exemplary APS imaging device 100 having an on-chip time delay integration circuit, according to one embodiment. The APS imaging apparatus 100 includes an APS array 110 and an analog integrator array 120 having APS sensing pixels arranged in m columns and n rows, wherein the two arrays are fabricated on a common substrate. . In operation, the imaging device 100 may be oriented in such a way that the column direction is substantially parallel to the imaging direction of the object to be imaged, relative to the imaging device 100. Integrator array 120 is designed to implement the time delay integration and interfaces with the APS array 110.

APS array 110 may be formed in any suitable APS design. Each APS sensing pixel includes photoactive elements such as photogates or photodiodes to collect photons and generate charge in response to the collected photons. The charge is then transferred to an in-pixel circuit that internally converts charge into a pixel electrical signal. In one embodiment, the intra-pixel circuitry may include a transfer gate and an isolated diffusion region located between the photoactive element and the diffusion region. The diffusion region accepts charge and sends the corresponding electrical signal to the pixel amplifier for further processing.

The APS array 110 may be formed of a CMOS-compatible active pixel sensor integrated on a semiconductor substrate. The integrator can also be integrated with the APS array 110 on the same substrate using CMOS technology to perform time delay integration. Therefore, such a CMOS imaging device can combine a time delay integration mechanism with various advantages and on-chip processing functionality of CMOS APS technology. Since each APS pixel internally converts photon induced charge into an electrical signal, charge transfer from one pixel to another is prevented.

One specific example of an APS based on photogates is disclosed in US Pat. No. 5,471,515 to Fossum et al., Which is incorporated herein by reference. One characteristic of such an APS array is the correlated double sampling mechanism. Fossum's patent discloses a readout circuit fabricated outside the APS sensor on a sensor substrate. In the readout circuit, the signal sample and hold circuit is used to sample the potential of the floating diffusion region at the end of each integration period to obtain the entire signal from the pixel. Another reset sample and hold circuit is used to reset the diffusion region and then resample the potential of the floating diffusion region to obtain a reset potential value. Differential circuits are connected to the two sample and hold circuits to produce an output representing the difference between the full signal and the reset signal. This double sampling significantly reduces read noise, such as KTC noise. The double sampling is performed in the apparatus 100 of the present invention in another way using the integrator array 120.

Integrator array 120 includes m × n analog integrators that are also arranged in m columns and n rows. Integrator array 120 is coupled to APS array 110 in a column-parallel fashion such that one column of integrators is coupled to receive a signal from only one column of APS sensing pixels. Each integrator may be designed such that the column-parallel shape can be used to perform n APS sensing pixels and n-stage time delay integrations from n integrators in the same column. Thus, the n output signals generated from n different APS sensing pixels in the same column at different times are integrated together to generate one pixel signal of the output image representing an image of one location on the object. The cross-track range is provided by m APS sense pixels in each row. The column-parallel design allows signal processing in different columns to be processed in parallel at the same time.

Analog-to-digital conversion can also be performed in the APS imaging apparatus 100. An ADC array 130 of m ADCs can be fabricated on the same substrate in thermal-parallel fashion such that each analog-to-digital converter (ADC) is designated to convert a time delay signal from one column of integrator array 120. Can be. Alternatively, a single ADC can be used to convert the signals from the entire integrator array 120, or an ADC array of mn ADCs can be used to digitize all of the output signals from the mn integrators in parallel.

Hereinafter, the circuit and operation of the integrator array 120 will be described in detail. In the column-parallel form, the signal level of the APS sensing pixels of a given row may be added to any one of the integrators in the column corresponding to the sensing pixels. Different integrators in the column store pixel values of consecutive positions on the object that are collected by other APS sensing pixels and accumulate for n frame times. Frame time is defined as the time required to read the entire APS array 110. In this configuration, the frame time is the integration time per pixel and the time spent reading one line of the image of the object at the final output.

When performing n-stage time delay integration, the APS array 110 is controlled to generate multiple consecutive frames at different times, as shown in FIG. 1A. However, the pixel signal of each frame is copied to the integrator array 120 by shifting in the column direction one row at a time, as shown in FIG. 1A.

1C is a table illustrating the mapping between APS sensing pixels in a column for integrators in the same column for three consecutive frames. In any given frame, APS sensing pixels and integrators in the same column have a 1: 1 mapping relationship. In any given integrator the mapping varies between two consecutive frames. In particular, the coupling between integrator array 120 and APS array 110 is controlled such that successive APS sensing pixels in any given column are each connected in a continuous frame form to a designated integrator. The designated integrator then generates one time delay integrated signal for one pixel of the final output image. This configuration allows any given point on the object to be mapped to the selected integrator, thus reducing imaging blur due to relative movement.

Therefore, according to the mapping, during any given frame time, the signal from the pixel in any given row k is added to the contents of the integrator in any given row j of the same column. In order to generate a single line image of an object, n integrations are required, so pixel values must be sampled at a sampling rate n times faster than the frame rate to provide a line image for every frame. Thus, for a given frame time, one row of integrators are ready to accumulate and read signals from all n previous frames.

The integrator array 120 is also controlled to read the APS array 110 twice during each frame to correct offset effects. After all the sensed pixels in the APS array are reset, the integrator array 120 samples each pixel reset value. Then, after the light guide signal is dumped from the photosensitive device and converted into an electric pixel signal, the integrator array 120 samples each APS pixel for a second time to obtain each signal. Thereafter, each integrator in the array 120 operates to subtract two values to maintain a differential value. This completes one integration for one frame. The double sampling and derivative are repeated for each frame. An example implementation based on a capacitor switched design is described below.

The time delay integration imaging apparatus 100 may request high speed processing on the integrator array 120. For example, assuming the line scanning speed is L, integration and readout should be processed at a rate of n × L for n-stage time delay integration. In addition, each integrator typically requires two clock cycles to complete one integration, one clock cycle for reset and another clock cycle for accumulation. Each pixel may also require multiple clock cycles to complete the sampling operation. In one implementation of an APS array based on photogates, pixel operation includes at least four clock cycles: pixel reset (RST), reset sampling (SHR), photogate dump (PG), and signal sampling (SHS). Include. Thus, a total of 6n clock cycles are needed to complete the time delay integration for one line. Assuming line rate L = 50k lines / sec and n is 32, the clock speed is on the order of 10 MHz. Noise performance in reading can be compromised at such high clock rates. In addition, the thermal-parallel design may limit the physical size of each integrator within the array 120 to the size of the APS sensing pixel (eg, a pitch of about 10 microns). These physical limitations make it difficult to achieve low noise and high speed integrators.

One feature of the apparatus 100 of the present invention is to implement a specific integrator array 120 such that signal processing for one pixel in a column temporarily terminates with signal processing for adjacent pixels. Temporary pipeline operation of other rows in a column, in combination with column-parallel processing, can reduce the requirement for a high speed clock while maintaining the overall operating speed of the imaging device 100.

Another feature of device 100 is that it reduces noise, such as offset and parasitic effects, in signal processing. The correlated double sampling mechanism of the APS array 110 significantly reduces the noise from the APS array 110. However, due to time delay integration operation and the presence of the integrator array 120, additional noise issues such as offsets and parasitic effects originally present in the integrator also occur.

This and other problems are solved in the design of integrator array 120. In particular, a special capacitor switched integrator is implemented to reduce additional noise. Hereinafter, some design of the integrator array 120 will be described.

FIG. 2A illustrates one embodiment of a differentially switched capacitor integrator column 200 showing each column of integrators in integrator array 120 as a building block. FIG. 2B shows a timing diagram when operating integrator 200 coupled to a column of APS sense pixels in a photogate design. Integrator column 200 contains all n integrators in one column. Only one differential operational amplifier 210 is used for all n integrators in that row. The differential operational amplifier 210 is coupled to receive two different input signals such that whenever a pixel is sampled, the reference level is also sampled and ensures differential sampling and integration, the two different input signals being derived from each pixel. A second input from one input and a reference level. During one frame time, each pixel is sampled twice to send the reset level and signal level to the first input of the differential op amp 210 at two different times. Each input of opamp 210, i.e., non-inverting input 211a and inverting input 211b, is connected to two alternative sampling capacitors C + s1, C + s2, and C-s1, C-s2. Enable pipeline processing. A total of n pairs of integral capacitors (C-1 and C + 1, C-2 and C + 2, ....., Cn and C + n) are connected to two differential outputs 212a and 212b. Form an array of n integrators in rows. Switches 1 and 2 are used to couple the sampling capacitor to the APS array 110, the reference signal and the common potential (Vcm). The switches R1 and S1, R2 and S2, ..., Rn and Sn are implemented to properly couple n pairs of integrating capacitors.

In operation, when one sampling capacitor set (e.g., C + s1 and C-s1) is switched to sample the reset level from the pixels in row k, dump from the corresponding pixel in the previous row k-1. The levels are summed in the switch transistor integrator. Therefore, desired high-speed processing is achieved by simultaneously performing sampling in one pixel and summing in adjacent pixels without having the high-speed clock required in other cases.

Capacitor-switched integrators are implemented in full-automatic topology to eliminate common-mode noise, including clock connections, ground noise, and charge feedthrough. However, using two alternating sampling capacitor sets disables the sampling of the input signal for the opamp input. This prevents automatic offset correction because the bottom plate potential of each sampling capacitor is no longer held at the same potential during the sample phase and the integration phase. Instead, the bottom plate potential changes from V _cm to V _cm + V _off where V _off is the input induced offset. In a typical time delay integrated imaging environment the signal level from each pixel is generally low and can be less than a typical opamp offset. Therefore, it is desirable to achieve an integral without offset without sacrificing speed and power.

The imaging device 200 is partially designed to achieve the desired offset elimination while maintaining pixel integration at high speed. The signal from the pixel is generated by dumping the optoelectronic on the imaging device and then subtracting the reset potential from the sense node potential (dump potential). This is accomplished by sampling and integrating the reset potential for a given pixel, followed by sampling and integrating the dump potential. The timing diagram of FIG. 2B shows the high speed operation by resetting all the pixels simultaneously. At this time, the reset voltage of the subsequent row are each open to the tank capacitor such form is integrated on a continuous ^{(C1 + & C1 -, ...} -, C2 + & C2). This is done by successively pulsed R1, R2, ..., and Rn.

Once all reset values are stored in the capacitor, photoelectric charge from all pixels is dumped simultaneously on each sense node. Then, the sense node potential (dump potential) is continuously integrated on the same capacitor set. The offset charge accumulated during the sample and integration of the reset potential is eliminated during the sample and integration of the dump potential by connecting the feedback capacitor with the plates of the capacitor placed in reverse, as indicated by the switching of S1, S2, ..., and Sn. Therefore, this design allows for integration without offset.

FIG. 3A illustrates another embodiment of the differentially switched capacitor integrator row 300. This design improves the imaging device 200 shown in FIG. 2A by reducing the parasitic capacitance effect. When a typical VLSI capacitor is implemented, the parasitic capacitance of the bottom plate may be quite high in some circumstances, for example about 25% of the total capacitance. Therefore, the inversion of the capacitor plate between the two phases results in a differential charge of the parasitic capacitance to another potential determined by the signal level. Since continuous integration is performed by successive pixels, the presence of voltage dependent charge on parasitic capacitances can lead to nonlinearity of integration and pixel to pixel blur. Therefore, it is desirable to reduce the influence of parasitic capacitance.

The design of FIG. 3A can be used to achieve this goal without generating a recognizable offset or without significantly reducing operating speed. This technique involves inverting the polarity of the sampling capacitor and the integration capacitor. As a result, the parasitic capacitance connected to the opamp input is due to, but not all of, the feedback capacitor or the sampling capacitor. Therefore, the charging of parasitic capacitance is compensated in every phase one phase. This can essentially eliminate the associated parasitic effects. To prevent pixel-to-pixel blurring, use an additional switch connected to V _cm . Thereby the parasitic capacitance is charged to V _cm irrespective of the output potential at the previous phase, thus eliminating signal dependent charge injection from the parasitic capacitor.

3B shows a timing diagram of operating a switch in device 300.

The operation of the apparatus 300 can be understood in the simple circuit shown in Figures 4A and 4B. Each integration cycle comprises two phases, of which the first phase (R-phase) is the reset level (V _m ). Is a phase for sampling and integrating the second phase and the second phase (D-phase) is for the dump level V _dn . The charge preservation before and after switching off in the R phase of the nth cycle follows the sampling of the reset signal yield as

Where V _cm is the common mode voltage, Is the potential of the sampling capacitor after the sampling capacitor is shorted in the nth phase, Is the input relative offset for the non-inverting (inverting) input, Is the n-th cycle, the R-phase noninverting (inverting) output, and α is the ratio between the parasitic capacitance and the actual capacitance.

In the next phase, both the sampling capacitor and the feedback capacitor are of opposite polarities, so that the parasitic capacitances exchange their positions. That positional exchange ensures that the total parasitic capacitance at the opamp input remains the same. Charge preservation in the D-phase is achieved by the following equation.

Therefore, the charge stored in the feedback capacitor after the end of the D-phase is the integrated value and opamp offset of all previous n-cycles, where each cycle represents a signal value from consecutive pixels, and the effects of parasitic capacitance are completely eliminated. . At the end of the cycle, the output of the capacitor is simply connected to V _cm to eliminate any signal dependencies. The output is written as

The remaining offset is due to the integrator reset phase, where the input and output of the opamp are at their initial levels. Are linked together to provide them. In the process, the charge stored in the feedback capacitor is completely removed. The offset can be easily removed by connecting one end of the feedback capacitor to the opamp input and connecting the other end to V _cm to perform an integrator reset. This ensures that the offset is stored in the capacitor and correctly removed in subsequent phases. Since each feedback capacitor is connected to V _cm via one switch anyway, no further switches are needed.

FIG. 5A illustrates another integrator column 500 as an alternative to the integrator column 300 shown in FIG. 3A. In this way the position of the feedback capacitor is exchanged between the inverting and non-inverting sides of the amplifier for every half cycle, as indicated by the timing diagram shown in FIG. 5B. Therefore, the offset charge accumulated during the R-phase is accurately compensated for by the same amount of charge of opposite polarity during the D-phase. The capacitor is designed in such a way that its bottom plate (shown as a curve in the figure) is always connected to the low impedance line and not to the opamp input. The design ensures that parasitic capacitances do not cause any nonlinearities or other errors. The capacitor is connected between the inverting input and the non-inverting output, or between the non-inverting input and the inverting output. This circuit can work equally well if the capacitor connections are reversed. This design is simpler to configure with fewer switches and simpler timing than the integrator row 300 shown in FIG. 3A, but in the design of FIG. 3A the capacitor is never switched from one side of the pre-differential amplifier to the other. Less crosstalk

The apparatus of FIGS. 3A and 5A can remove the opamp offset during all summing operations, but still has a residual offset. This residual offset is the initial level at which the input and output of the opamp Generated in the integrator reset phase when connected together to provide. In this process, the charge stored in the feedback capacitor is completely removed. The offset can also be eliminated by connecting one end of the feedback capacitor to the opamp input and the other end to V _cm to perform an integrator reset. This ensures that the offset is stored in the capacitor and correctly removed in subsequent phases. Since each feedback capacitor is connected to V _cm through one switch anyway, no further switches are needed.

The differential operational amplifier 210 used in the design for common mode correction is used to drive the capacitor of the integrator capacitor bank. Since the amplifier 210 has both out + and out− outputs, this amplifier is called full differential.

6 illustrates one embodiment of an amplifier 210. The two outputs move symmetrically from the common mode voltage to have the following values.

Amplifier 210 is designed to be completely symmetrical to remove common mode noise. This design is the design of a single stage telescopic cascade amplifier.

The key to this amplifier 210 is that it consists of differential pairs formed by NFETs M1 and M2 with their sources connected together. The common source current is set by load FE7 (M3), whose gate is biased by voltage biasN. The differential pair is also connected as a current mirror and to a set of PFET load transistors M4 and M5 which are biased by a voltage biasP. The voltage biasN determines the load current in M3. The sum of the currents of M1 and M2 should equal the fixed load current, but the current is divided between M1 and M2 based on the input voltages (in +, in−). The current through M1 and M2 determines the current throughout the left or right branch of the circuit. The impedances of M4 and M5 convert the branch current back to their respective voltages (out + and out-) to create an amplifier action.

The NFET transistors M6 and M7 and the PFET transistors M8 and M9 are cascade transistors. These transistors maintain the drain and PFET load transistors of the NFET differential pair at a nearly constant voltage so that the current in the FETs does not change when the output voltage swings. This increases the effective impedance of the FETs and correspondingly increases the gain. The bias voltage of the PFET cascade is introduced directly from biasCasP. The voltage of the NFET cascade is generated from biasP by the combination of M10 and M11.

The amplifier 210 has a common mode feedback circuit that maintains a fixed common mode voltage, that is, maintains a constant V _{common mode} in the feedback mechanism. The opamp includes two common mode feedback circuit blocks, one of which is connected to each output (out +, out-). One end of the primary capacitor of each block is connected to its respective output, and the other ends of the capacitors are connected together. The common node averages the output voltage and senses and provides a measurement of the actual common mode voltage with ac. The common node, denoted "cmfb" in the figure, is connected to the gate of transistor M12 to provide common mode feedback. When the actual common mode voltage drifts up, the gate voltage of M12 increases to increase the current in the left and right branches of the amplifier, forcing the common mode voltage to decrease again. Conversely, if the actual common mode voltage drifts down, the current through M12 is reduced, forcing the common mode voltage to increase again. In this way, the common mode voltage is stabilized.

When sensed with d.c., the switchable capacitor sets a fixed offset between the common mode voltage and the cmfb voltage at the gate of M12. This is done by cycling the switch voltages phi_CMpull and phi_CMpush. The flying capacitor is connected to biasN, the bias of the VcmO and load FET M3 by the phi_CMpull phase. This causes the flying capacitor to charge with the difference between the potentials. The voltage is "pushed" to the primary capacitor by the phi_CMpush phase.

For any given phase, there is a shared charge between the capacitors, so that when the capacitors are combined, the combined voltage divides the difference between the previous primary capacitor voltage and the desired push voltage. However, every cycle moves the composite voltage closer to the push value, and after a few cycles the voltage is substantially set to the push value.

It is also contemplated that the integrator array 120 of the imaging device 100 of FIG. 1 is implemented using a single-ended opamp to reduce the physical size of the integrator array 210. The differential integrator requires common mode feedback in order to maintain the full differential opamp in a biased state. Such a feedback circuit can occupy a significant area of the chip area. 7A and 7B illustrate one embodiment of a switched capacitor integrator 700 using a discontinued opamp 710. 7C shows a timing diagram for operating the switch. Integrator 700 performs correlated double sampling to reduce the offset. Only the integrated difference between the reset level and the signal level is stored in the integral capacitor.

Many specific embodiments have been described so far. Nevertheless, various modifications may be made without departing from the scope of the following claims.

Claims (19)

A light configured by arranging rows and columns of a plurality of sensing pixels, each having a photosensitive element for generating a charge in response to an incident photon from an object and an in-pixel circuit for converting the charge into an electric pixel signal representing the charge A sense array; An integrator array comprising a plurality of integrators each arranged in the same number of rows and columns as the rows and columns of the photosensitive array, The integrator of each column is combined to receive an electric pixel signal from only one designated column of sensing pixels in the photosensitive array, and after each sensing pixel has been sampled and read the same number of times as the number of rows in the photosensitive array. And generate a time delay integrated signal representing the object. The imaging device of claim 1, wherein each integrator of the integrator array comprises a capacitor switched integrator. The image pickup apparatus according to claim 2, wherein the operation of one integrator with respect to a signal generated in one sensing pixel is temporarily overlapped with another operation of an adjacent integrator with respect to another signal generated in each adjacent sensing pixel. The second switching capacitor of claim 2, wherein the capacitor switchable integrator comprises: a first sampling capacitor whose first input terminal stores a first signal generated by the first sensing pixel and a second sensing pixel which is adjacent to the first sensing pixel; And a first sampling capacitor, wherein the first and second signals are generated at different times. 3. The imaging device of claim 2, wherein the capacitor switchable integrator is a differential integrator having a first input terminal for receiving an electric pixel signal and a second input terminal for receiving a reference signal. 3. The circuit of claim 2, wherein the capacitor switchable integrator comprises a single-ended amplifier having an output coupled to a circuit having a reset sampling capacitor, an integrating capacitor and a plurality of switches, wherein the plurality of switches comprise a reset potential and a signal potential from the pixel. And in the circuitry to connect the integral capacitor and the reset sampling capacitor to store only the difference between the integrated capacitors. 2. An imaging device according to claim 1, wherein said in-pixel circuit comprises an amplifier. An image pickup apparatus according to claim 1, wherein the photosensitive element comprises a photogate or a photodiode. The imaging device of claim 1, wherein the sensing pixels are reset at the same time. 2. The imaging device of claim 1, further comprising at least one analog-to-digital converter coupled to digitize the output from the integrator array. The imaging device according to claim 1, wherein each sensing pixel is sampled for a first time to generate a reset value, and after the light guidance signal is generated, it is sampled for a second time to generate a signal value for each reading. . A substrate formed of a semiconductor; A sensing array consisting of n rows and m columns fabricated on the first region of the substrate and generating an electric pixel signal in response to photons; An integrator array fabricated on a second region of said substrate adjacent said first region with m amplifiers each electrically connected to said m columns of active pixel sensors; And each amplifier is connected to n pairs of capacitors such that each pair of capacitors accumulates electric pixel signals from n different active pixel sensors in each column generated at different times to generate a sum signal. 13. The imaging device according to claim 12, wherein each amplifier samples each sensing pixel twice during each reading to obtain a differential pixel signal between the photon induced signal value and the reset value of each sensing pixel. 15. The imaging device of claim 13, wherein each capacitor pair is coupled to each amplifier in such a way that one capacitor receives the reset value and the other capacitor receives the photon induced signal value. 15. The imaging device of claim 14, wherein each amplifier is a differential amplifier having a first input coupled to a designated column of an active pixel sensor and a second input coupled to a reference level. Using a linear sense pixel array along the direction to capture radiation from an object moving relative to the sense array along a predetermined direction; Internally converting radiation induced charges of each pixel of the array into an electrical pixel signal; Coupling a linear integrator array of integrators to the sense array to sample multiple frames of an image of an object generated by the sense array; Recalling the mapping from the sense array to the integrator array when sampling another frame to generate a sum signal summed from pixel positions of other frames of other frames corresponding to a common image from any position on the object. And spatially shifting along a predetermined direction. 17. The method of claim 16, further comprising sampling each pixel twice in each frame to obtain a differential value between the signal level and the reset level of each pixel. 18. The method of claim 17, further comprising: temporarily overlapping a reset level of a first pixel and a signal level of a second adjacent pixel. 17. The method of claim 16, wherein each integrator comprises a capacitor switched integrator.