JP3421096B2 - Solid-state imaging device - Google Patents

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a solid-state image pickup device which can realize low-noise reading by slow scanning and can also perform high-scan reading without sacrificing the low-noise characteristic.

[0002]

2. Description of the Related Art FIG. 5 shows a conventional charge coupled device (CCD).
3 shows a configuration of a solid-state image pickup device reading section using the. A plurality of transfer electrodes 101 are formed on the semiconductor substrate 100.
Are arranged. The signal charges in the surface layer portion of the semiconductor substrate 100 transferred to the right in the drawing by the transfer electrode 101 are
The floating diffusion region 1 provided on the right side of the transfer electrode 101, passing below the output gate 106 provided on the right end of the transfer electrode 101.
02 collected.

The floating diffusion region 102 is connected to the source of the reset gate MOSFET 105.
By periodically inputting a clock pulse to the gate of the OSFET 105 in response to the transfer of the signal charge (at the time of high level), the signal charge of the floating diffusion region 102 flows out to the outside via the terminal RD. When the clock pulse is at a low level, the signal charges collected in the floating diffusion region 102 are input to the gate of the charge-voltage conversion MOSFET 103 and converted into a voltage by the load resistor 104 connected to this source. This voltage as a whole appears at the output terminal V _O as a signal corresponding to the optical input from the outside.

One such reset MOSFET
The charge amplifier provided in the output section of the CCD composed of 105 and one charge-voltage converting MOSFET 103 is generally a floating diffusion amplifier FD.
A (Floating Diffusion Ampl)
The amplifier performance is often dictated by the signal-to-noise ratio of a solid-state amplifier. That is, such F
In DA, a coefficient (μV / e ⁻ ; 1) for converting charge into voltage
If the voltage output corresponding to the charge of electrons is large, high sensitivity can be realized in the solid-state imaging device as a whole. In addition, the FDA unit is particularly used for charge-voltage conversion MO.
The noise of the SFET 103 becomes the final noise of the solid-state image sensor. Therefore, the solid-state imaging device capable of reading out a very low-noise signal, which is mainly used for scientific measurement in recent years, reduces the influence of the read-out noise due to the thermal noise of the output MOSFET. 50 kHz (2
A slow scan of about 0 μs) is performed.

However, in the entire system using such a readout solid-state image pickup device, for example, 1024 × 10 2
When a CCD having 4 pixels is used, 20 μs × 1024 × 1024> 2 for reading one image.
Since it takes more than 0 seconds, when using it as a camera, it is necessary to wait 20 seconds or more after reading the image while shifting the focus.
There is a drawback that the actual focusing is very troublesome. As described above, there is a trade-off relationship between the noise reduction of the solid-state image sensor and the scanning speed.
In the FDA using the charge-voltage converting MOSFETs of the stages, it is difficult to make the scanning speed and the noise level suitable at the same time.

Further, the FDA single-stage charge-voltage conversion MO
In the SFET circuit (source follower circuit), if an attempt is made to increase the scanning speed, the frequency characteristics of the source follower circuit deteriorate. That is, it is M of the source follower circuit that determines the frequency characteristic of the source follower circuit.
The mutual conductance gm (rate of minute change in drain current with respect to minute change in gate voltage) at the operating point of the OSFET and the load capacitance C _L connected to the output terminal, and the frequency characteristic is proportional to gm / C _L.

To improve the frequency characteristics, the load capacitance C _L
However, it is necessary to reduce C _L and increase the transconductance gm, but C _L cannot be reduced because it depends on the wiring capacitance for connecting the source follower circuit and the circuit in the next stage (for example, amplifier) and the input form of the circuit in the next stage. Have difficulty. Further, even if C _L is reduced, if gm does not increase, C
It is difficult for a CD as a whole to operate at a high speed of 5 MHz or more. On the other hand, when gm is increased, a large current must be passed through the output MOSFET, so that the flicker noise (1 / f noise) component increases due to the effect of the interface state between the substrate silicon of the MOSFET and the oxide film, and CCD It is difficult to have low noise as a whole. This is a one-step MO
The FDA composed of SFETs cannot perform high-speed operation, but can perform low-noise reading by slow scan.

On the other hand, as a method of reading out the signal charge of CCD by high scan, there is FDA composed of two-stage MOSFET. This is one in which the gate of the second-stage MOSFET is connected to the output terminal of the first-stage MOSFET. In the case of such an FDA source follower circuit, gm / C _L can be increased by using a MOSFET having a large mutual conductance gm for the second-stage MOSFET, and the load capacitance connected to the output terminal thereof. Also, the influence of the wiring load capacitance connected to the first stage can be reduced. As a result, the frequency characteristic is improved and high-speed operation can be easily realized, but since a large gm is used, 1 / f noise increases as described above.

Since the voltage of the effective value of thermal noise is proportional to the square root of the frequency band, if a high-bandwidth amplifier for high-speed operation is connected to the output terminal of the source follower circuit for speeding up, read noise will occur. It has the drawback of rising.
As described above, when the FDA including the two-stage MOSFETs is used, high scan is possible, but it is not suitable for slow scan with a low noise level.

In order to solve the above problems, FIG.
It has been proposed to provide a circuit 210 for low noise and a circuit 220 for high speed on both ends of a plurality of transfer electrodes 101 of a CCD as shown in FIG. In such a device, when low noise characteristics are required, the signal charges are transferred to the left side of the drawing and input to the circuit 210 for low noise, and when high speed characteristics are required, the signal charges are transferred to the right side of the drawing. Circuit 22 for high speed
Input to 0.

Further, in Japanese Patent Laid-Open No. 62-056551, C
A transimpedance amplifier (IV converter) for low frequency and an FDA for high frequency are provided at one end of the CD transfer electrode, and the source of the reset MOSFET and the input gate of the high frequency FDA are connected to the floating diffusion region. , The high frequency component for each pixel from the floating diffusion region is detected by the high frequency FDA, the low frequency component is converted into a voltage by the IV converter, and then the low frequency component and the high frequency component are crossover circuit. A video signal generation circuit for generating a video signal by combining is disclosed. The configuration of the IV converter and the charge amplifier for FDA is shown in FIG.

[0012]

However, in the solid-state image pickup device in which the circuit 210 for low noise and the circuit 220 for high speed are provided at both ends of the CCD transfer electrode 101, the case where the signal charge is transferred to the right side is different. When transferring to the left, it is necessary to switch the clock pulse applied to the transfer electrodes 101, 107 and the like, and since the obtained image becomes a mirror object, it is necessary to restore the image in terms of hardware or software. is there. For this reason, extra processing time and circuits are required when processing images in hardware or software, such as switching clock pulses.
The design of the entire device was complicated.

Further, in the video signal generator disclosed in Japanese Patent Laid-Open No. 62-056551, the I signal is used for low frequency reading.
It uses a low-frequency readout circuit that uses a -V converter.
Although low-frequency read-out is possible, the influence of such thermal noise of the IV converter cannot be ignored, and low-noise read-out with reduced noise at the pixel detection limit was impossible.

The present invention has been made in view of the above problems, and it is possible to realize low-noise reading by slow scanning, and high-scan reading can be performed without sacrificing the low-noise characteristic. The purpose is to provide a device.

In order to achieve the above-mentioned object, the solid-state image pickup device according to the present invention is generated in the light receiving section by applying a drive voltage to the transfer electrode group formed in the light receiving section and causing light to enter the light receiving section. A solid-state imaging device including an imaging unit that transfers the generated charge to a floating diffusion unit provided at one end of a transfer electrode group, wherein a source is connected to the floating diffusion unit of the imaging unit and a reset gate is charged. And a first reset FET in which a charge is applied from the reset drain to the floating diffusion portion to accumulate the electric charge in the floating diffusion portion and a gate is connected to the floating diffusion portion of the imaging unit. A first floating diffusion amplifier configured to generate a signal voltage corresponding to the amount of charges transferred to the floating diffusion portion, and a source connected to the first reset FET. And a second reset FET for causing charges to flow from the reset drain to the floating diffusion portion via the first reset FET by applying a voltage for resetting charges to the reset gate to accumulate the charges in the floating diffusion portion. And a high speed processing first FET having a gate connected to the source of the second reset FET, and a high speed processing
The source and drain of the first FET of
And a second floating diffusion amplifier configured to generate a signal voltage corresponding to the charge amount of the charges transferred to the floating diffusion portion, and a second reset FET, Applying a voltage equal to or higher than the threshold voltage to the gate of the first reset FET
A low-noise signal voltage is read from the first floating diffusion amplifier by applying a reset pulse voltage synchronized with the drive voltage to the gate of the first floating diffusion amplifier,
By applying a voltage equal to or higher than the threshold voltage to the gate of the reset FET and applying a reset pulse voltage synchronized with the driving voltage to the gate of the second reset FET, a high-speed signal voltage is read from the second floating diffusion amplifier. It is characterized by

[0016]

According to the present invention, first, the signal charge generated by the optical image applied to the light receiving portion is transferred to the floating diffusion portion by applying a drive voltage to the transfer electrode. Next, when a low-noise optical image is captured by slow scan, the first reset FET is set to HIGH level. At the time of this slow scan, the second reset FET is HIGH.
It is set as a level and does not prevent electric charge from being accumulated in the floating diffusion portion when the first reset FET is set to the HIGH level. Then, the first floating diffusion amplifier converts the signal charge transferred to the floating diffusion portion into an output signal voltage. After amplifying the signal charges by the first floating diffusion amplifier, the first reset FET is set to HIGH level again, and this operation is repeated in synchronization with the transfer of the signal charges.

When a high-speed optical image is picked up by high scanning, the first reset FET is set to HIGH level. At the time of this high scan, the first reset FET is at the HIGH level, and the second reset F
It does not prevent electric charges from being accumulated in the floating diffusion portion when ET is set to the HIGH level. Then, the first floating diffusion amplifier converts the signal charge transferred to the floating diffusion portion into an output signal voltage. After amplifying the signal charge by the second floating diffusion amplifier, the second reset FET is set to HIGH level again,
Hereinafter, this operation is repeated in synchronization with the transfer of signal charges.

When a slow scan image is taken, the low noise signal voltage read from the first floating diffusion amplifier is applied to the first filter and the second filter.
It is possible to obtain an output signal voltage with even lower noise by passing it with the filter of.

[0019]

DESCRIPTION OF THE PREFERRED EMBODIMENTS A solid-state image pickup device according to the present invention will be described below with reference to the accompanying drawings. The same elements will be denoted by the same reference symbols, without redundant description.

FIG. 1 is a circuit diagram showing a configuration of an output section of a solid-state image pickup device (CCD) according to an embodiment of the present invention. The solid-state imaging device according to the present invention transfers the charges generated in the light receiving region to the floating diffusion section by the transfer electrodes, and converts the transferred charges into a voltage by the floating diffusion amplifier (FDA).

The floating diffusion portion FD is represented by a diode D1 and a capacitor Cfd1 connected to the cathode of the diode D1. The cathode of the diode D1 and the capacitor C
A gate of a first low noise MOSFET (field effect transistor) L1 for low noise reading is connected to a node 1 with fd1 and a bias voltage OD1 is applied between the output drain and source of the first low noise MOSFET L1 to form a source follower of one stage. It constitutes the circuit.

When the signal charge transferred by the transfer electrode in the slow scan and injected into the floating diffusion portion FD via the output gate OG1 is read out, the floating diffusion amplifier constituted by the one-stage source follower circuit is read out. (FDA) is used to convert the signal charge into an output signal voltage. The first low-noise MO
The source of the SFET (L1) is grounded to the ground via the load resistance R.

The node 1 has a first reset MOSFET.
The source of (RG1) is connected, and the drain thereof is connected to the gate of the first high-speed processing MOSFET (H1). The source and drain of the first high-speed processing MOSFET (H1) are the second high-speed processing MOSFET.
(H2) is connected to the gate and drain of the first and second high-speed processing MOSFETs (H1,
Bias OD2 is applied to the drain of 2)
It constitutes a source follower circuit of stages.

When the signal charge transferred by the transfer electrode in the high scan and injected into the floating diffusion portion FD through the output gate OG1 is read, a floating diffusion amplifier (FDA) composed of the two-stage source follower circuit is used. ) Is used to convert the signal charge into an output signal voltage. The first and second high-speed processing MOs
The source of the SFET (H1, H2) is a first load resistance MOSFET whose gate and source are short-circuited and grounded.
(R1) and second load resistance MOSFET (R2)
Respectively connected to the drains of.

The first reset MOSFET (RG
1) drain and the first high-speed processing MOSFET (H
The second reset MOSFET is provided at the node 2 with the gate of 1).
The source of (RG2) is connected. Second reset M
A bias is applied to the drain of the OSFET (RG2) via the terminal RD.

When the output section of such a solid-state image pickup device is constructed, the output section is the first reset MOSFET.
(RG1) and second reset MOSFET (RG2)
By applying the clock pulse shown in the time charts of FIGS. 2 and 3, the signal charges transferred under the transfer electrodes are read out. The read mechanism of the output signal voltage during the high scan and the slow scan will be described below with reference to the timing charts of FIGS. 2 and 3.

When reading a signal by high scan, first, the voltage applied to the first reset MOSFET (RG1) is set to the HIGH level (FIG. 2 (a)). Between time t ₁ ~t _2, the second reset MOSFET
By applying a clock pulse to the gate of (RG2) (FIG. 2 (c)), a bias is applied to the capacitor Cfd1 via the terminal RD and the charges are reset. Then, for the charge transfer, a DC bias is applied to the output gate (OG1) and the final gate (L
This is LOW because the clock is input to G).
This is performed in synchronization with reaching the level (FIG. 2 (b)). In addition, the output signal voltages V ₀ 1 and V _O 2 have t _{1 to} t ₂
The noise due to reset appears between (Fig. 2 (d),
(E)).

Then, at times t _{3 to} t ₄ , signal charges flow into the floating diffusion portion FD (FIG. 2 (b)), and at the same time, output signal voltages V _O 1 and V _O 2 appear (FIG. 2 (d),
(E)). After this, until the time t ₄ ~t _7, time t ₁ ~
The same operation is performed up to t ₄ .

As described above, at the time of high scan, the signal charges transferred under the floating diffusion portion FD are composed of the floating diffusion portion FD and the first and second MOSFETs (H1, 2) for high-speed processing at high speed. The signal is input to the signal reading floating diffusion (FDA2) circuit and converted into a signal voltage. At this time, the second high-speed processing MOSFET (H
In 2), since the mutual conductance g _m is very high, high-speed signal read operation is possible.

When reading a signal by slow scan, first, the voltage applied to the second reset MOSFET (RG2) is set to the HIGH level (FIG. 3).
(A)). By applying a clock pulse to the gate of the second resetting MOSFET (RG2) between times t _{1 and} t ₂ (FIG. 3C), the capacitor Cfd
A bias is applied to 1 through the terminal RD to accumulate charges. At this time, the final gate (LG) of the transfer gate is at the HIGH level from time t _{1 to} t ₃ , and no charge is injected into the floating diffusion portion FD. At this time, noise due to resetting appears in the output signal voltage V _O 1 between t ₁ and t ₂ (FIG. 3D).

When the final gate (LG) becomes LOW level from time t _{3 to} t ₄ , signal charges flow into the floating diffusion portion FD (FIG. 3B), and at the same time, the output signal voltage V _O 1 appears (Fig. 3 (d)). Then, until a time t ₄ ~t ₇ operates similarly to to time t ₁ ~t _4.

As described above, the signal charge transferred under the floating diffusion portion FD during the slow scan is the floating diffusion for reading the low noise signal which is composed of the floating diffusion portion FD and the first MOSFET (L1) for low noise. (F
It is input to the DA1) circuit and converted into a signal voltage.

Next, FIG. 4 shows the overall structure of a solid-state image pickup device (CCD) using the output section as described above. Note that the signal charge transfer method of this embodiment is described as a frame transfer (FT) method, but this is a full frame transfer (FFT) method or an interline (IL) method.
Various transfer methods such as a transfer method and a frame interline (FIT) transfer method can be applied.

The light receiving portion of the CCD image pickup device is composed of a photosensitive portion SE1 and a storage portion AC1, both of which are arranged in the vertical direction by the number of horizontal pixels transferred by the CCD, and the CCDs are separated by a channel stop. Has been done. Photosensitive part S
When E1 is irradiated with a light image, signal charges corresponding to the lightness and darkness of the light image are accumulated at each place where light is irradiated on the photosensitive section SE1 for a fixed time of one field or one frame. Then, this signal charge is transferred to the control circuit C.
By applying the clock pulse generated from O1 to the transfer electrode (not shown), the pattern of the signal charges accumulated in the photosensitive section SE1 is transferred to the accumulating section AC1 within the vertical blanking time.

The charge pattern input to the accumulator AC1 is such that the signal charge is added to the horizontal register RE1 every horizontal scanning time.
Transfer to. The signal charge transferred to the horizontal register RE1 is transferred to the output unit at a faster scan than the scan for transferring the signal charge from the storage unit AC1 to the horizontal register RE1. This output section has the configuration shown in FIG. 1, and the signal charges are converted into the output signal voltage V ₀ 1 or V ₀ 2 and output.

The output signal voltage V ₀ 1 extracted for low noise by the slow scan is input to the low noise amplifier A1. At this time, the high-frequency component of the signal charge is removed by the low-pass filter provided in the amplifier A1. Thereafter, this signal is correlated double sampling CDS (corrella).
The low frequency component and KTC noise (reset noise) are removed by being input to the ted double sampling circuit B1. Since such a series of signal processing functions as a bandpass filter, unnecessary low frequency components and high frequency components other than the signal frequency can be removed. The low-noise signal thus obtained is 12-16
It is input to the high-precision AD converter C1 of bits and converted from an analog signal to a digital signal.

Then, this digital signal is accumulated in the frame memory M1, and the light image input to the light receiving portion is accurately stored.

The output signal voltage V ₀ 2 extracted for high speed imaging by high scanning is input to the amplifier A2 for high speed processing. Then, similar to the signal processing in the case of the slow scan, the low frequency component and the reset noise of this signal are removed by the CDS circuit (B2), and the high speed A of 8 to 10 bits
After the analog signal is converted into a digital signal by the D converter C2, it is stored in the frame memory (M1) as required. The control circuit CO1 controls the timing of the entire circuit.

According to this embodiment of the present invention, the signal diffusion transferred to the floating diffusion portion FD is read by the floating diffusion (FDA1) for reading a low noise signal.
The circuit and the floating diffusion (FDA2) for high-speed signal reading are independently converted into signal voltages, so that the signal charges can be read at high speed without sacrificing low noise characteristics. Further, when the output signal voltage output from the output unit is imaged by slow scan, unnecessary signal components are removed by the low noise amplifier A1 and the CDS circuit (B1) to obtain a higher quality image. be able to. Further, when the output signal voltage is imaged by high scanning, the output signal voltage can be amplified at a high speed and an unnecessary signal component can be removed by the high speed processing amplifier A2 and the CDS circuit (B2).

[0040]

As described above, according to the present invention, when high-speed imaging is performed by high scan, the first reset F
The second reset F with ET kept at HIGH level
When the signal charge is amplified by the second floating diffusion amplifier while applying the voltage for resetting the charge to ET, and the low noise imaging is performed by the slow scan, the second reset FET is kept at the HIGH level. , The signal charges can be amplified by the first floating diffusion amplifier while applying the voltage for resetting the charges to the first reset FET. At this time, the first floating diffusion amplifier can output a low noise output signal voltage, and the second floating diffusion amplifier can output an output signal voltage at high speed. In addition, the low noise characteristic in the case of performing image capture by slow scan is never sacrificed. As a result, C using this solid-state imaging device
When capturing a weak optical image such as an astronomical observation with a CD camera or the like, it is possible to first focus the CCD camera in a short time by high scan, and then capture a high-quality image by slow scan. In this way, it is possible to shorten the imaging time which could not be reached by the conventional one or a plurality of CCD cameras.

[Brief description of drawings]

FIG. 1 is a circuit diagram of an output unit of a solid-state imaging device according to an embodiment of the present invention.

2 is a timing chart of the output unit of the solid-state imaging device shown in FIG.

FIG. 3 is a timing chart of the output section of the solid-state imaging device shown in FIG.

FIG. 4 is a circuit diagram of a solid-state imaging device according to an embodiment of the present invention.

FIG. 5 is a diagram illustrating a circuit configuration of a conventional solid-state imaging device output unit.

FIG. 6 is a diagram illustrating a circuit configuration of a conventional solid-state imaging device output unit.

FIG. 7 is a diagram illustrating a transimpedance amplifier and a charge amplifier.

[Explanation of symbols]

FD ... Floating diffusion section, D1 ... Diode, Cfd1 ... Capacitor, L1 ... Low noise MOSFET, OD1 ... Bias voltage, RG1 ... First reset MOSFET, RG2
... second reset MOSFET, H1 ... first high-speed processing MOSFET, H2 ... second high-speed processing MOSFET
T, OD2 ... Bias, R1 ... First load resistance MOS
FET, R2 ... Second load resistance MOSFET, RD ...
Terminal, OG1 ... Output gate, LG ... Final gate, SE1 ... Photosensitive part, AC1 ... Storage part, RE1 ... Horizontal register, V ₀ 1, V ₀ 2 ... Output signal voltage, A1, A2 ...
Amplifier, B1, B2 ... CDS circuit, C1, C2 ... AD converter, CO1 ... Control circuit, FDA1, FDA2
… Floating diffusion amplifier.

Claims (2)

(57) [Claims] 1. A drive voltage is applied to a transfer electrode group formed in a light receiving portion, and charges generated in the light receiving portion when light is incident on the light receiving portion are provided at one end of the transfer electrode group. A solid-state imaging device having an imaging unit for transferring to a floating diffusion unit, wherein a source is connected to the floating diffusion unit of the imaging unit, and a voltage for charge resetting is applied to a reset gate to reset the drain from the reset drain. A first reset FET that causes a charge to flow into the floating diffusion unit to accumulate the charge in the floating diffusion unit, and a first reset FET having a gate connected to the floating diffusion unit of the imaging unit.
A first floating diffusion amplifier configured to generate a signal voltage corresponding to the amount of charges transferred to the floating diffusion section, a source connected to the first reset FET, and a charge applied to the reset gate. A second reset FET that causes a charge to flow from the reset drain to the floating diffusion portion via the first reset FET when the reset voltage is applied, and accumulates the charge in the floating diffusion portion; A first FET for high-speed processing , the gate of which is connected to the source of the second reset FET, and the first F for high-speed processing
ET source and drain have gate and drain
A second floating diffusion amplifier configured to include a connected second FET for high-speed processing, which generates a signal voltage corresponding to the amount of charges transferred to the floating diffusion portion, and the second reset FET By applying a voltage equal to or higher than a threshold voltage to the gate of the first reset FET and applying a reset pulse voltage synchronized with the drive voltage to the gate of the first reset FET, a low-noise signal voltage is output from the first floating diffusion amplifier. Read, by applying a voltage equal to or higher than a threshold voltage to the gate of the first reset FET, and applying a reset pulse voltage synchronized with the drive voltage to the gate of the second reset FET, the second floating diffusion. Solid-state imaging device characterized by reading high-speed signal voltage from amplifier 2. A first filter for removing a high frequency component of a low noise signal voltage read from the first floating diffusion amplifier, and a second filter for removing a low frequency component of the low noise signal voltage. The solid-state imaging device according to claim 1, further comprising a filter.