KR20020053550A - Method of manufacturing a semiconductor device - Google Patents

Abstract

PURPOSE: A method for manufacturing a semiconductor device is provided to prevent the reduction of a ferroelectrics characteristic of a dielectric film by preventing the hydrogen from flowing into the dielectric film of a capacitor. CONSTITUTION: The first contact hole exposing a fixed part of a semiconductor substrate(1) is formed by etching the first insulation film(2). The first contact plug(14) is formed in order to bury the first contact hole and the capacitor(16) is formed on an upper part of the first contact plug. A barrier layer(18) is formed on the surface including the capacitor. After forming the second insulation film on the barrier layer, the second contact hole is formed by etching the second insulation film in order to expose the capacitor. The second contact plug(20) is formed in order to bury the second contact hole and a metal wiring(21) is formed on the second contact plug.

Description

Method of manufacturing a semiconductor device

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a semiconductor device. In particular, an interlayer insulating film is formed by forming a barrier layer of La ₂ O ₃ on a capacitor before an interlayer insulating film such as ILD and IMD for insulating the upper metal wiring is formed. The present invention relates to a method of manufacturing a semiconductor device capable of preventing hydrogen injected during a subsequent process to be introduced into a capacitor, thereby preventing the ferroelectric characteristics of the capacitor from deteriorating and preventing the dielectric film from deteriorating.

As the integration of DRAMs increases, higher dielectric constants and smaller leakage current characteristics are required, and therefore, the capacitor structure needs to be changed to a MIM structure with a small leakage current.

SiO ₂ / Si ₃ N ₄ / SiO ₂ laminated structure is widely used as a capacitor dielectric film of a conventional MIM structure. However, in recent years, a capacitor having a high dielectric constant and a low leakage current and a simplified capacitor manufacturing process have been shifting from a stacked structure to a single layer structure. In line with this trend, BST, Ta ₂ O _5, or BLT (Bi _4-x , La _x ) Ti ₃ O ₁₂ ) is used as a capacitor dielectric film of a DRAM device having an integration density of 1 Gbit or more. Capacitors using BST, Ta ₂ O _5, and BST are commonly used in structures of Ru / Ta ₂ O ₅ / Ru, Ru / BST / Ru, Pt / BST / Pt, and Pt / BLT / Pt.

An interlayer insulating film such as inter-level dielectric (ILD) and inter-metal dielectric (IMD) is formed on the capacitor of the above structure to insulate the upper metal wiring. However, hydrogen injected during a predetermined deposition process for forming ILD and IMD flows into the dielectric film of the capacitor to break oxygen bonds in the dielectric film, thereby degrading ferroelectric properties.

In particular, when the BLT is used as the dielectric film of the capacitor, hydrogen injected during the predetermined deposition process for forming the ILD and the IMD is introduced into the BLT of the capacitor to maintain the electrical properties of the perovskite layer. Degradation of oxygen bonds (Oxygen) reduces ferroelectric properties, and accumulates in the unit cell, the interface between the unit cells and grain boundaries, thereby inhibiting the movement of the unit cell in the alignment direction or greatly deteriorating the dielectric film.

Accordingly, the present invention prevents hydrogen injected during a predetermined deposition process for forming an interlayer insulating film such as ILD and IMD to insulate the metal wiring on the capacitor, thereby preventing the ferroelectric property of the dielectric film from being introduced into the dielectric film of the capacitor. It is to provide a method of manufacturing a semiconductor device for preventing the degradation.

It is still another object of the present invention to provide a subsequent layer for forming an interlayer insulating film by forming a barrier layer of La ₂ O ₃ on top of a capacitor before an interlayer insulating film such as ILD and IMD for insulating the upper metal wiring is formed. The present invention provides a method of manufacturing a semiconductor device capable of preventing hydrogen injected during a process from being introduced into a capacitor, thereby preventing the ferroelectric property of the capacitor from deteriorating and preventing the dielectric film from deteriorating.

1 (a) to 1 (d) are cross-sectional views of a semiconductor device sequentially shown to explain a method of manufacturing a semiconductor device according to an embodiment of the present invention.

<Explanation of symbols for the main parts of the drawings>

1 semiconductor substrate 2 field oxide film

3: gate insulating film 4: conductive layer

5: insulation layer 6: gate electrode

7 spacer 8 first interlayer insulating layer

9 bit line 10 second interlayer insulating layer

11: polycrystalline silicon 12: ohmic contact layer

13: diffusion barrier 14: first contact plug

15 lower electrode 16 dielectric film

17: upper electrode 18: barrier layer

19: third interlayer insulating layer 20: second contact plug

21: first metal wiring 22: fourth interlayer insulating layer

23: second metal wiring

The present invention includes forming a first contact hole for exposing a predetermined region of the semiconductor substrate by etching a predetermined region of the first insulating layer after forming a first insulating layer on the semiconductor substrate having a predetermined structure; Forming a first contact plug to fill the first contact hole; Forming a capacitor on the first contact plug; Forming a barrier layer over the entire structure including the capacitor; Forming a second contact hole so as to expose the capacitor by etching a predetermined portion of the second insulating film after forming a second insulating film over the barrier layer; Forming a second contact plug to fill the second contact hole; And forming a metal wiring on the second contact plug.

Hereinafter, with reference to the accompanying drawings will be described in detail the present invention.

1 (a) to 1 (d) are cross-sectional views sequentially illustrating a method of manufacturing a capacitor of a semiconductor device according to an embodiment of the present invention.

Referring to Fig. 1A, first, a field oxide film 2 for determining an active region and a field region is formed in a semiconductor substrate 1 having a predetermined structure. The gate electrode 6 is formed on the entire structure including the field oxide film 2.

The gate electrode 6 is formed by sequentially depositing the gate insulating film 3, the conductive layer 4, and the insulating layer 5, and then patterning the gate insulating film 3. Subsequently, a spacer 7 may be formed on both sides of the gate electrode 6 to protect itself during a subsequent etching process, and a predetermined insulating layer (not shown) may be formed on the spacer 7.

After the first interlayer insulating layer 8 is deposited on the entire structure including the spacers 7, the first interlayer insulating layer 8 is patterned to form a first contact hole to expose a predetermined portion of the semiconductor substrate 1.

Thereafter, after the metal material or the precious metal material is deposited on the entire structure, the bit line 9 is formed to fill the first contact hole formed between the gate electrodes 6 by patterning.

Thereafter, after the second interlayer insulating layer 10 is deposited on the entire structure including the bit line 9, the second contact hole is exposed to expose a predetermined portion of the semiconductor substrate 1 via the first contact hole. Patterned to form. Thereafter, the first contact plug 14 is formed to fill the second contact hole.

The first contact plug 14 is formed in a laminated structure in which the polycrystalline silicon 11, the ohmic contact layer 12, and the diffusion barrier layer 13 are sequentially formed.

The polysilicon 11 is formed on a predetermined portion in the second contact hole after polycrystalline silicon is deposited on the entire structure including the gate electrode 35.

In the ohmic contact layer 12, a Ti film or a Co film is formed on the entire structure including the polycrystalline silicon 11. The semiconductor substrate 1 having the Ti film or the Co film is thermally treated to react with the polycrystalline silicon 12 on the polycrystalline silicon 11 inside the second contact hole to form a titanium silicide film or a cobalt silicide film.

In the diffusion barrier 13, a nitride film such as a TiN film, a TiSiN film, a TiAlN film, a TaSiN film, and a TaAlN film is formed by a PVD method or a CVD method.

Referring to FIG. 1B, after the lower electrode 15, the dielectric film 16, and the upper electrode 17 are sequentially deposited on the entire structure including the first contact plug 14, patterning is performed. Thus, a capacitor is formed.

The lower electrode 15 is formed of precious metals such as Ir, IrOx, Ru, RuOx, PtW, WN, and TiN, such as metal-organic chemical vapor deposition (MOCVD), physical vapor deposition (PVD), spin-on, and plasma enhanced chemical vapor (PECVD). It is formed by any one of the deposition).

The dielectric film 16 is a spin-on method using BLT ((Bi _x La _y ) Ti ₃ O ₁₂ ) having a Bi and La composition ratio of 3.25 to 3.35 atoms and 0.80 to 0.90 atoms, using a liquid source. After being deposited with MOD or LSMCD, it is cured by two baking processes and the organic matter is removed by rapid heat treatment, and formed by perovskite BLT nucleation and growth.

Here, the rapid heat treatment process is performed in a mixed gas atmosphere in which a temperature range of 500 to 700 ° C., an atmospheric pressure, and O ₂ , N ₂ O or O ₂ and N ₂ O are mixed at a predetermined ratio.

The upper electrode 17 is a metal-organic chemical vapor deposition (MOCVD), physical vapor deposition (PVD), spin-on, and plasma enhanced chemical vapor (PECVD) of precious metals such as Ir, IrOx, Ru, RuOx, PtW, WN, and TiN. It is formed by any one of the deposition).

Referring to FIG. 1 (c), the temperature range of 300 to 700 ° C. and O ₂ , N ₂ O, H ₂ O, H ₂ O _2, or O ₂ and N are on the entire structure including the upper electrode 17. A barrier layer 18 of La ₂ O ₃ is formed to a thickness of 50 to 500 kPa by CVD (chemical vapor deposition) or ALD (atomic layer deposition) in a mixed gas atmosphere in which ₂ O is mixed at a predetermined ratio.

Thereafter, the barrier layer 18 is rapidly thermally crystallized in a temperature range of 500 to 800 ° C. and N ₂ gas.

Referring to FIG. 1 (d), a phospho silicate glass (PSG), a boro-phospho silicate glass (PSG), a spin on glass (SOG), an undoposed silicate glass (USG), and the like, are disposed on an entire structure including the barrier layer 18. After the oxide of is deposited, the third interlayer insulating layer 19 is formed by patterning the third contact hole so that the upper electrode 17 of the capacitor is exposed.

Thereafter, a second contact plug 20 is formed to fill the third contact hole. The second contact plug 20 is formed in a stacked structure in which TiN, Ti, and Al are sequentially formed.

Thereafter, a first metal wiring 21 having a stacked structure in which TiN, Ti, and Al are sequentially formed on the entire structure including the second contact plug 20 is formed.

Thereafter, the fourth interlayer insulating layer 22 of the IMD is formed on the entire structure including the first metal wiring 21 and the second metal wiring 23 is formed thereon.

As described above, in the semiconductor device of the present invention, a barrier layer of La ₂ O ₃ is formed on the capacitor before the interlayer insulating films such as ILD and IMD for insulating the upper metal wiring are formed.

As described above, the present invention forms a barrier layer of La ₂ O ₃ on the capacitor before the interlayer insulating film such as ILD and IMD for insulating the upper metal wiring is formed, thereby forming the interlayer insulating film. By preventing the injected hydrogen from flowing into the capacitor, it is possible to prevent the ferroelectric characteristics of the capacitor from deteriorating and to prevent the dielectric film from deteriorating.

Claims (10)

Forming a first contact hole exposing a predetermined region of the semiconductor substrate by etching a predetermined region of the first insulating layer after forming a first insulating layer on the semiconductor substrate having a predetermined structure; Forming a first contact plug to fill the first contact hole; Forming a capacitor on the first contact plug; Forming a barrier layer over the entire structure including the capacitor; Forming a second contact hole so as to expose the capacitor by etching a predetermined portion of the second insulating film after forming a second insulating film over the barrier layer; Forming a second contact plug to fill the second contact hole; Forming a metal wiring on the second contact plug. The method of claim 1, The capacitor is a method of manufacturing a semiconductor device, characterized in that the lower electrode, the dielectric film and the upper electrode are sequentially deposited, then patterned. The method of claim 2, The lower electrode is a method of manufacturing a semiconductor device, characterized in that the noble metal material such as Ir, IrOx, Ru, RuOx, PtW, WN and TiN is formed by any one of MOCVD, PVD, spin-on and PECVD. The method of claim 2, The dielectric film is a spin-on method using a liquid source of BLT ((Bi _x La _y ) Ti ₃ O ₁₂ ) having a Bi and La composition ratio of 3.25 to 3.35 atom% and 0.80 to 0.90 atom%, MOD or Fabrication of a semiconductor device characterized in that it is formed by the formation and growth of perovskite BLT nuclei at the same time, after being deposited with LSMCD, is cured by two baking processes, and a predetermined organic material is removed by a rapid heat treatment process. Way. The method of claim 4, wherein The rapid heat treatment process is a semiconductor device, characterized in that the temperature range of 500 ~ 700 ℃, the pressure of the atmospheric pressure, O ₂ , N ₂ O or a mixed gas atmosphere mixed O ₂ and N ₂ O in a predetermined ratio Method of preparation. The method of claim 1, The upper electrode is a capacitor manufacturing method of a semiconductor device, characterized in that the noble metal materials such as Ir, IrOx, Ru, RuOx, PtW, WN and TiN is formed by any one of MOCVD, PVD, spin-on and PECVD. The method of claim 1, The barrier layer is CVD in a mixed gas atmosphere in which La ₂ O ₃ is in a temperature range of 300 to 700 ° C. and O ₂ , N ₂ O, H ₂ O, H ₂ O ₂ or O ₂ and N ₂ O are mixed at a predetermined ratio. Or ALD is formed to a thickness of 50 to 500 kHz. The capacitor manufacturing method of a semiconductor device characterized by the above-mentioned. The method of claim 1, The barrier layer is a method of manufacturing a semiconductor device characterized in that it further comprises the step of crystallizing by rapid heat treatment in a temperature range of 500 ~ 800 ℃ N ₂ gas. The method of claim 1, And the second insulating film is formed to expose the capacitor after oxides such as PSG, BPSG, SOG, and USG are deposited. The method of claim 1, And forming a second metal interconnection (IMD) and a second metal interconnection on the entire structure including the first metal interconnection.