KR20020051287A - Method for making inter-dielectric layer in semiconductor device - Google Patents
Method for making inter-dielectric layer in semiconductor device Download PDFInfo
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- KR20020051287A KR20020051287A KR1020000080888A KR20000080888A KR20020051287A KR 20020051287 A KR20020051287 A KR 20020051287A KR 1020000080888 A KR1020000080888 A KR 1020000080888A KR 20000080888 A KR20000080888 A KR 20000080888A KR 20020051287 A KR20020051287 A KR 20020051287A
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
- H01L21/76837—Filling up the space between adjacent conductive structures; Gap-filling properties of dielectrics
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02107—Forming insulating materials on a substrate
- H01L21/02109—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates
- H01L21/02112—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer
- H01L21/02123—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon
- H01L21/02126—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon the material containing Si, O, and at least one of H, N, C, F, or other non-metal elements, e.g. SiOC, SiOC:H or SiONC
- H01L21/02129—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon the material containing Si, O, and at least one of H, N, C, F, or other non-metal elements, e.g. SiOC, SiOC:H or SiONC the material being boron or phosphorus doped silicon oxides, e.g. BPSG, BSG or PSG
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02107—Forming insulating materials on a substrate
- H01L21/02225—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer
- H01L21/0226—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process
- H01L21/02263—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process deposition from the gas or vapour phase
- H01L21/02271—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process deposition from the gas or vapour phase deposition by decomposition or reaction of gaseous or vapour phase compounds, i.e. chemical vapour deposition
- H01L21/02274—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process deposition from the gas or vapour phase deposition by decomposition or reaction of gaseous or vapour phase compounds, i.e. chemical vapour deposition in the presence of a plasma [PECVD]
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
- H01L21/76819—Smoothing of the dielectric
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3105—After-treatment
- H01L21/31051—Planarisation of the insulating layers
- H01L21/31053—Planarisation of the insulating layers involving a dielectric removal step
Abstract
Description
본 발명은 반도체소자의 제조 방법에 관한 것으로서, 특히 배선간 절연막과 소자의 보호막으로 이용되는 층간절연막의 형성 방법에 관한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a semiconductor device, and more particularly, to a method for forming an interlayer insulating film and an interlayer insulating film used as a protective film for an element.
일반적으로 반도체 소자 제조 공정에서 폴리실리콘과 상부 금속배선 사이의 층간절연막, 즉 PMD(Pre Metal Dielectric 또는 Polysilicon-Metal Dielectric)으로 BPSG(Boro Phospho Silicate Glass)가 사용되고 있다. 특히, SACVD(Sub-Atmospheric Chemical Vapor Deposition), APCVD(Atmospheric Pressure CVD) 증착 장치를 이용하여 O3-TEOS(Tetra Ethyl Ortho Silicate)계 케미컬 소스로 우수한 갭필특성 및 평탄화 특성을 가지도록 하여 서브미크론(Sub-micron) 반도체소자의 제조 공정에 적용되고 있다.In general, BPSG (Boro Phospho Silicate Glass) is used as an interlayer insulating layer between a polysilicon and an upper metal wiring, that is, a PMD (Pre Metal Dielectric or Polysilicon-Metal Dielectric). In particular, sub-Atmospheric Chemical Vapor Deposition (SACVD) and Atmospheric Pressure CVD (APCVD) deposition apparatuses have excellent gap fill and planarization characteristics as O 3 -TEOS (Tetra Ethyl Ortho Silicate) based chemical sources. Sub-micron) has been applied to the manufacturing process of semiconductor devices.
도 1은 종래기술에 따른 층간절연막의 형성 방법을 개략적으로 도시한 도면이다.1 is a view schematically showing a method of forming an interlayer insulating film according to the prior art.
도 1에 도시된 바와 같이, 반도체기판(11)상에 게이트산화막(12), 폴리실리콘으로 이루어진 게이트전극(13)을 순차적으로 형성한 다음, 게이트산화막(12)과 게이트전극(13)의 양측벽에 스페이서(15)를 형성한다. 여기서, 스페이서(14) 형성전에 저농도 불순물 이온주입으로 LDD(Lightly Doped Drain) 영역(14)을 형성한다. 계속해서, LDD 영역(14)에 접하는 소스/드레인 영역(16)을 형성하고, 전면에 금속을 증착 및 고온 열처리로 게이트전극(13)의 상면, 소스/드레인 영역(16)의 표면에 실리사이드막(17)을 형성한다.As shown in FIG. 1, the gate oxide film 12 and the gate electrode 13 made of polysilicon are sequentially formed on the semiconductor substrate 11, and then both sides of the gate oxide film 12 and the gate electrode 13 are formed. The spacer 15 is formed in the wall. Here, the LDD (Lightly Doped Drain) region 14 is formed by implanting low concentration impurity ions before forming the spacer 14. Subsequently, a source / drain region 16 in contact with the LDD region 14 is formed, a metal is deposited on the entire surface, and a silicide film is formed on the upper surface of the gate electrode 13 and the surface of the source / drain region 16 by high temperature heat treatment. (17) is formed.
전면에 층간절연막으로서 제 1 PMD(18), 제 2 PMD(19), 제 3 PMD(20)을 순차적으로 형성한다.The first PMD 18, the second PMD 19, and the third PMD 20 are sequentially formed on the entire surface as an interlayer insulating film.
이러한 층간절연막의 증착은 먼저, 제 1 PMD(18)로서 PECVD(Plasma Enhanced Chemical Vapor Deposition)계 USG(Undoped Silicon Glass)를 500Å∼1000Å의 두께로 증착하며, 제 1 PMD(18)는 후속 상부 BPSG의 보론/인의 확산방지막으로 작용한다.The deposition of such an interlayer insulating film firstly deposits a Plasma Enhanced Chemical Vapor Deposition (PECVD) -based undoped silicon glass (USG) as a first PMD 18 to a thickness of 500 mW to 1000 mW, and the first PMD 18 is followed by a subsequent upper BPSG. It acts as a diffusion barrier for boron / phosphorus.
다음으로, 제 2 PMD(19)로서 SACVD 또는 APCVD 방법을 이용한 O3-TEOS계 BPSG를 3000Å∼5000Å의 두께로 증착한다.Next, an O 3 -TEOS-based BPSG using the SACVD or APCVD method is deposited as the second PMD 19 to a thickness of 3000 kPa to 5000 kPa.
계속해서, 700℃∼900℃에서 열처리하여 제 2 PMD(19)인 BPSG을 평탄화하고 BPSG를 치밀화시킨다.Subsequently, heat treatment is performed at 700 ° C to 900 ° C to flatten the BPSG which is the second PMD 19 and to densify the BPSG.
마지막으로, 제 3 PMD(20)로서 광역 평탄화를 위한 희생산화막을 5000Å∼10000Å의 두께로 증착한다.Finally, as the third PMD 20, a sacrificial oxide film for wide area planarization is deposited to a thickness of 5000 kPa to 10,000 kPa.
상술한 PMD의 증착이 완료된 후, 화학적기계적연마(Chemical Mechanical Polishing; CMP) 공정을 실시하여 넓은 영역에 걸쳐 평탄화를 진행하고, 제 3 PMD(20), 제 2 PMD(19), 제 1 PMD(18)을 순차적으로 식각하여 소스/드레인 영역()이 노출되는 콘택홀을 형성한다.After the deposition of the above-described PMD is completed, a chemical mechanical polishing (CMP) process is performed to planarize over a wide area, and the third PMD 20, the second PMD 19, and the first PMD ( 18) is sequentially etched to form a contact hole through which the source / drain region is exposed.
그러나, 0.25㎛ 기술(Deep sub micron)로의 소자 개발이 이루어짐에 따라 BPSG의 PMD 적용에 많은 문제점이 유발되고 있다.However, as the device development to the 0.25 μm technology (Deep sub micron) is made, many problems are caused to the PMD application of BPSG.
먼저, BPSG의 평탄화를 위해 약 700℃ 이상의 고온 열처리 공정이 필요하나 하부 공정에 실리사이드(Silicide) 공정이 적용됨에 따라 고온 열처리에 의해 실리사이드막이 응집되는 등 실리사이드 특성 열화라는 큰 문제점을 유발하게 된다.First, a high temperature heat treatment process of about 700 ° C. or more is required to planarize the BPSG, but as the silicide process is applied to the lower process, the silicide film is agglomerated by high temperature heat treatment.
또한, O3-TEOS계 BPSG의 근본적인 취약점인 큰 흡습성으로 인해 보론(B)과 인(P)의 농도 제어가 불안정하고 후속 공정 지연시 수분 흡수로 인해 결정 결함이 발생하여 소자의 특성에 치명적 문제를 유발시키기도 한다.In addition, due to the large hygroscopicity, which is a fundamental weakness of O 3 -TEOS-based BPSG, concentration control of boron (B) and phosphorus (P) is unstable, and crystal defects occur due to moisture absorption during subsequent process delays, which is a critical problem in device characteristics. It may cause.
한편, 최상층 금속배선 형성후 소자보호막(Passivation)으로서 PE-USG/PE-질화막 또는 PE-PSG/PE-질화막의 이층 구조를 적용한다. 그러나, 소자의 고집적화에 따른 금속배선 피치(Pitch)의 감소로 갭필이 열악하고 큰 유전상수를 갖는 문제점이 있다.On the other hand, after forming the uppermost metal wiring, a two-layer structure of PE-USG / PE-nitride film or PE-PSG / PE-nitride film is used as passivation. However, there is a problem in that the gap fill is poor and a large dielectric constant is reduced due to the reduction of the metal wiring pitch due to the high integration of the device.
본 발명은 상기 종래기술의 문제점을 해결하기 위해 안출한 것으로서, 우수한 갭필 특성과 저유전상수를 가지며, 수분 흡수로 인한 결정 결함을 방지하는데 적합한 층간절연막의 형성 방법을 제공하는데 그 목적이 있다.The present invention has been made to solve the problems of the prior art, and has an object of providing a method of forming an interlayer insulating film having excellent gap fill characteristics and low dielectric constant and suitable for preventing crystal defects due to water absorption.
도 1은 종래기술에 따른 층간절연막의 형성 방법을 개략적으로 도시한 도면,1 is a view schematically showing a method of forming an interlayer insulating film according to the prior art;
도 2a 내지 도 2b는 본 발명의 제 1 실시예에 따른 층간절연막의 형성 방법을 도시한 도면,2A to 2B illustrate a method of forming an interlayer insulating film according to a first embodiment of the present invention;
도 3은 본 발명의 제 2 실시예에 따른 층간절연막의 형성 방법을 도시한 도면.3 is a view showing a method of forming an interlayer insulating film according to a second embodiment of the present invention.
*도면의 주요 부분에 대한 부호의 설명* Explanation of symbols for the main parts of the drawings
31 : 반도체기판 32 : 게이트산화막31 semiconductor substrate 32 gate oxide film
33 : 게이트전극 34 : LDD 영역33: gate electrode 34: LDD region
35 : 스페이서 36 : 소스/드레인 영역35: spacer 36: source / drain area
37 : 실리사이드막 38 : PECVE-USG37: silicide film 38: PECVE-USG
39 : F-PSG 40 : USG39: F-PSG 40: USG
상기의 목적을 달성하기 위한 본 발명의 층간절연막의 형성 방법은 반도체기판상에 다수의 도전층패턴을 형성하는 단계, 상기 도전층패턴상에 플라즈마화학기상증착법으로 제 1 절연막을 형성하는 단계, 상기 제 1 절연막상에 플라즈마화학기상증착법으로 플루오린과 인이 함유된 제 2 절연막을 형성하는 단계, 및 상기 제 2 절연막상에 광역 평탄화를 위한 제 3 절연막을 형성하는 단계를 포함하여 이루어짐을 특징으로 한다.The method of forming an interlayer insulating film of the present invention for achieving the above object comprises the steps of forming a plurality of conductive layer patterns on a semiconductor substrate, forming a first insulating film on the conductive layer pattern by plasma chemical vapor deposition; Forming a second insulating film containing fluorine and phosphorus on the first insulating film by plasma chemical vapor deposition, and forming a third insulating film for wide area planarization on the second insulating film. do.
본 발명의 층간절연막의 형성 방법은 반도체기판상에 다수의 금속배선을 형성하는 단계, 상기 금속배선상부에 소자보호막으로서 플루오린과 인이 함유된 제 1 절연막을 형성하는 단계, 및 상기 제 1 절연막상에 소자보호막으로서 제 2 절연막을 형성하는 단계를 포함하여 이루어짐을 특징으로 한다.The method of forming an interlayer insulating film of the present invention comprises the steps of forming a plurality of metal wirings on a semiconductor substrate, forming a first insulating film containing fluorine and phosphorus as an element protection film on the metal wirings, and the first insulation And forming a second insulating film as an element protective film on the film.
이하, 본 발명이 속하는 기술분야에서 통상의 지식을 가진 자가 본 발명의 기술적 사상을 용이하게 실시할 수 있을 정도로 상세히 설명하기 위하여, 본 발명의 가장 바람직한 실시예를 첨부 도면을 참조하여 설명하기로 한다.Hereinafter, the preferred embodiments of the present invention will be described in detail with reference to the accompanying drawings so that those skilled in the art may easily implement the technical idea of the present invention. .
도 2a 내지 도 2b는 본 발명의 제 1 실시예에 따른 층간절연막의 형성 방법을 도시한 도면이다.2A to 2B illustrate a method of forming an interlayer insulating film according to a first embodiment of the present invention.
도 2a에 도시된 바와 같이, 실리사이드막(37) 형성전에 반도체기판(31)상에 게이트산화막(32), 게이트전극(33)을 형성하고, 게이트전극(33)의 양측벽에 스페이서 (35)를 형성하며, 반도체기판(31)에 LDD영역(34)과 소스/드레인 영역(36)을 형성한다. 실리사이드막을 포함한 다수의 게이트전극(33)이 형성된 반도체기판(31)상에 제 1 PMD로서 PECVD-USG(38)를 500Å∼1000Å의 두께로 증착한다. PECVD-USG(38)는 후속 상부 F-PSG(Fluoro-Phospho Silicate Glass)의 플루오린/인의 확산방지막으로 작용한다.As shown in FIG. 2A, the gate oxide film 32 and the gate electrode 33 are formed on the semiconductor substrate 31 before the silicide film 37 is formed, and the spacers 35 are formed on both sidewalls of the gate electrode 33. The LDD region 34 and the source / drain region 36 are formed in the semiconductor substrate 31. On the semiconductor substrate 31 on which the plurality of gate electrodes 33 including the silicide film are formed, PECVD-USG 38 is deposited as a first PMD to a thickness of 500 to 1000 mW. PECVD-USG 38 serves as a diffusion barrier of fluorine / phosphorus in subsequent top Fluoro-Phospho Silicate Glass (F-PSG).
다음으로, 제 2 PMD로서 PECVD방법을 이용한 F-PSG(39)를 증착한다. 이러한 F-PSG(39) 증착은, PECVD 장치에서 플루오린 소스로서 CF계 가스, 예컨대 CF4,C2F6, NF3를 이용하고, 인 소스로서 TMP(Ttri Methyl Phosphate), TMOP(Tri Methyl Ortho Phospate)를 이용하며, 이러한 플루오린 소스와 인소스와 함께 TEOS 소스를 이용하여 SiOF-P2O5화합물을 형성한다.Next, the F-PSG 39 using the PECVD method is deposited as the second PMD. Such F-PSG 39 deposition uses CF-based gases such as CF 4 , C 2 F 6 , NF 3 as a fluorine source in a PECVD apparatus, and TMP (Ttri Methyl Phosphate) and TMOP (Tri Methyl) as phosphorus sources. Ortho Phospate), together with these fluorine and phosphorus sources to form SiOF-P 2 O 5 compounds using TEOS sources.
이 때, 플루오린(F)과 인(P)의 성분비는 플루오린 4wt%∼7wt%, 인 3wt%∼5wt%를 가질 수 있도록 증착시 가스비를 조절하여 진행한다.At this time, the component ratio of fluorine (F) and phosphorus (P) proceeds by adjusting the gas ratio during deposition so as to have fluorine 4wt% to 7wt%, phosphorus 3wt% to 5wt%.
상술한 바와 같은 F-PSG(39)에서 플루오린은 산화막 식각 특성을 가져 증착시 증착/식각/증착의 반복이 이루어지도록 하므로써 우수한 갭필특성을 가지도록 한다. 이를 통해 미세한 게이트전극간, 자세히는 폴리실리콘간 간극을 보이드없이 매울수 있다. 또한, 플루오린은 전기음성도가 가장 큰 물질로 전자 분극(Electronic polarization)을 감소시키며, Si-F 결합이 Si-O 결합보다 강한 결합력을 가지므로 이온 분극(Ionic polarization)이 작아져 SiO2박막에 비해 저유전상수를 갖는다.In the F-PSG 39 as described above, the fluorine has an oxide film etching characteristic, so that the deposition / etching / deposition may be repeated during deposition to have excellent gap fill characteristics. As a result, the gap between the fine gate electrodes and more specifically the polysilicon can be filled without voids. In addition, fluorine is the largest electron-negative material, reducing electronic polarization, and since Si-F bonds have stronger bonding force than Si-O bonds, ionic polarization is reduced, resulting in a SiO 2 thin film. It has a low dielectric constant compared to
실제로, 플루오린 4wt%∼7wt% 성분으로 통상 BPSG의 유전상수(4∼4.5)의 약 20% 이상인 3.5∼3.8까지 감소시킨다.In practice, the fluorine 4wt% -7wt% component is reduced to 3.5-3.8, which is usually about 20% or more of the dielectric constant (4-4.5) of BPSG.
한편, F-PSG(39)에서 인(P)은 후속 공정 진행시 오염될 수 있는 K+, Na+같은 각종 모빌이온(Mobile ion)들을 모으는 작용을 가져 하부 소자의 열화를 방지한다.Meanwhile, phosphorus (P) in the F-PSG 39 has a function of collecting various mobile ions such as K + and Na + that may be contaminated in a subsequent process to prevent deterioration of the lower device.
통상, 제 2 PMD 형성후 고온 열처리를 진행하였으나, 본 발명의 실시예에서는 플라즈마를 이용하여 PMD를 증착하므로 수분에 대한 안정성이 뛰어나며 이미 갭필이 충분히 이루어져 추가적인 고온 열처리 공정이 불필요하다.In general, although the high temperature heat treatment is performed after the formation of the second PMD, in the embodiment of the present invention, since the PMD is deposited by using plasma, the stability of the moisture is excellent and the gap fill is sufficient, so that an additional high temperature heat treatment process is unnecessary.
도 2b에 도시된 바와 같이, 제 3 PMD로서 광역 평탄화를 위한 희생산화막인 USG막(40)을 5000Å∼10000Å의 두께로 형성한다.As shown in FIG. 2B, a USG film 40, which is a sacrificial oxide film for wide area planarization, is formed as a third PMD to a thickness of 5000 kPa to 10,000 kPa.
상술한 PMD의 증착이 완료된 후, 화학적기계적연마(Chemical Mechanical Polishing; CMP) 공정을 실시하여 넓은 영역에 걸쳐 평탄화를 진행하고, USG(40), F-PSG(39), PECVD-USG(38)을 순차적으로 식각하여 콘택홀을 형성한다.After the deposition of the above-mentioned PMD is completed, chemical mechanical polishing (CMP) process is performed to planarize over a wide area, and USG 40, F-PSG 39, PECVD-USG 38 Sequentially etch to form contact holes.
도 3은 본 발명의 다른 실시예에 따른 층간절연막의 형성 방법을 도시한 도면으로서, 소자보호막의 형성 방법을 도시하고 있다.3 is a diagram illustrating a method of forming an interlayer insulating film according to another exemplary embodiment of the present invention, and illustrates a method of forming an element protective film.
도 3에 도시된 바와 같이, 반도체기판 또는 하부 소자의 제조 공정이 완료된 층간절연막(41)상에 소정 간격을 두고 다수의 최상층 금속배선(42)을 형성한다.As shown in FIG. 3, a plurality of uppermost metal wirings 42 are formed at predetermined intervals on the interlayer insulating film 41 on which the semiconductor substrate or lower device manufacturing process is completed.
계속해서, 금속배선(42)을 포함한 전면에 제 1 소자보호막으로서 F-PSG(43)를 형성하고, F-PSG(43)상에 제 2 소자보호막으로서 PE-질화막(44)을 3000Å∼5000Å의 두께로 형성한다.Subsequently, an F-PSG 43 is formed on the entire surface including the metal wiring 42 as the first element protection film, and the PE-nitride film 44 is formed as a second element protection film on the F-PSG 43 as 3000 Å to 5000 Å. It is formed to the thickness of.
이 때, F-PSG(43) 형성시, 금속배선(42) 두께의 100%∼120%로 증착하여 금속배선 사이의 간극을 매우며 금속배선의 층간 정전용량을 최소화한다.At this time, when forming the F-PSG (43), it is deposited by 100% to 120% of the thickness of the metal wiring 42 to close the gap between the metal wiring and minimize the interlayer capacitance of the metal wiring.
후속 공정으로 패드(Pad) 오픈 공정을 실시한다.The pad opening process is performed as a subsequent process.
본 발명의 기술 사상은 상기 바람직한 실시예에 따라 구체적으로 기술되었으나, 상기한 실시예는 그 설명을 위한 것이며 그 제한을 위한 것이 아님을 주의하여야 한다. 또한, 본 발명의 기술 분야의 통상의 전문가라면 본 발명의 기술 사상의 범위 내에서 다양한 실시예가 가능함을 이해할 수 있을 것이다.Although the technical idea of the present invention has been described in detail according to the above preferred embodiment, it should be noted that the above-described embodiment is for the purpose of description and not of limitation. In addition, those skilled in the art will understand that various embodiments are possible within the scope of the technical idea of the present invention.
상술한 바와 같은 본 발명의 층간절연막 형성 방법은 열적 스트레스로 인한 실리사이드막의 특성 열화를 방지하고, 미세한 게이트전극간 또는 배선간 간극을 보이드없이 매울수 있는 우수한 갭필특성 및 저유전상수를 구현할 수 있는 효과가 있다.The method of forming the interlayer insulating film of the present invention as described above prevents the deterioration of characteristics of the silicide film due to thermal stress, and has an effect of realizing excellent gap fill characteristics and low dielectric constants to fill gaps between minute gate electrodes or wirings without voids. have.
또한 플라즈마를 이용하므로써 수분 흡습을 방지할 수 있고, 갭필이 충분히 이루어져 추가적인 고온 열처리 공정을 생략할 수 있는 효과가 있다.In addition, by using the plasma it is possible to prevent the moisture absorption, the gap fill is sufficiently made there is an effect that can omit the additional high temperature heat treatment process.
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| US7226875B2 (en) * | 2004-11-30 | 2007-06-05 | Taiwan Semiconductor Manufacturing Co., Ltd. | Method for enhancing FSG film stability |
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