KR100223288B1 - Method of fabrication isolation film of semiconductor device - Google Patents
Method of fabrication isolation film of semiconductor device Download PDFInfo
- Publication number
- KR100223288B1 KR100223288B1 KR1019960022783A KR19960022783A KR100223288B1 KR 100223288 B1 KR100223288 B1 KR 100223288B1 KR 1019960022783 A KR1019960022783 A KR 1019960022783A KR 19960022783 A KR19960022783 A KR 19960022783A KR 100223288 B1 KR100223288 B1 KR 100223288B1
- Authority
- KR
- South Korea
- Prior art keywords
- film
- bpsg
- bpsg film
- semiconductor device
- forming
- Prior art date
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
- H01L21/76819—Smoothing of the dielectric
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02107—Forming insulating materials on a substrate
- H01L21/02225—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer
- H01L21/0226—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process
- H01L21/02263—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process deposition from the gas or vapour phase
- H01L21/02271—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process deposition from the gas or vapour phase deposition by decomposition or reaction of gaseous or vapour phase compounds, i.e. chemical vapour deposition
- H01L21/02274—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process deposition from the gas or vapour phase deposition by decomposition or reaction of gaseous or vapour phase compounds, i.e. chemical vapour deposition in the presence of a plasma [PECVD]
Abstract
본 발명은 반도체 소자의 층간 절연막 형성 방법에 관한 것으로, BPSG막에 함유된 도펀트의 배출에 의한 결함의 발생을 방지하기 위하여 BPSG막을 도포한 후 상기 BPSG막상에 보호막을 형성한다. 그리고 플로우 공정을 실시하여 상기 BPSG막의 표면을 평탄화시킨 후 상기 보호막을 제거하고 상기 BPSG막상에 산화막을 형성한다. 따라서 후속 열처리 공정시 상기 BPSG막에 함유된 도펀트의 배출에 의한 결합의 발생이 방지되어 소자의 절연 특성이 향상되며, 불량의 발생이 방지되어 소자의 수율이 향상될 수 있는 반도체 소자의 층간 절연막 형성 방법에 관한 것이다.The present invention relates to a method for forming an interlayer insulating film of a semiconductor device, in which a BPSG film is coated and a protective film is formed on the BPSG film in order to prevent defects caused by the discharge of a dopant contained in the BPSG film. After the surface of the BPSG film is planarized by a flow process, the protective film is removed and an oxide film is formed on the BPSG film. Accordingly, it is possible to prevent the occurrence of bonding due to the discharge of the dopant contained in the BPSG film during the subsequent heat treatment process, thereby improving the insulation characteristics of the device, preventing the occurrence of defects, and improving the yield of the device. ≪ / RTI >
Description
제 1a 및 제 1b 도는 종래 반도체 소자의 층간 절연막 형성 방법을 설명하기 위한 소자의 단면도.FIGS. 1A and 1B are cross-sectional views of a device for explaining a conventional method for forming an interlayer insulating film of a semiconductor device.
제 2a 내지 제 2d 도는 본 발명에 따른 반도체 소자의 층간 절연막 형성 방법을 설명하기 위한 소자의 단면도.Figs. 2 (a) to 2 (d) are cross-sectional views of a device for explaining a method of forming an interlayer insulating film of a semiconductor device according to the present invention.
* 도면의 주요부분에 대한 부호의 설명DESCRIPTION OF THE REFERENCE NUMERALS
1 및 11 : 실리콘 기판 2 및 12 : 접합 영역1 and 11: silicon substrate 2 and 12: junction region
3 및 13 : 게이트 산화막 4 및 14 : 폴리실리콘층3 and 13: gate oxide films 4 and 14: polysilicon layer
5 및 15 : 게이트 전극 6 및 16 : 산화막 스페이서5 and 15: gate electrodes 6 and 16: oxide spacer
7 및 17 : 제 1 산화막 8 및 18 : BPSG7 and 17: First oxide films 8 and 18: BPSG
9 및 20 : 제 2 산화막 19 : 보호막9 and 20: second oxide film 19: protective film
본 발명은 반도체 소자의 층간 절연막 형성 방법에 관한 것으로, 특히 BPSG(Borophospho Silicate Glass)막에 함유된 도펀트(Dopant)의 배출에 의한 결합(Defect)의 발생을 방지할 수 있도록 한 반도체 소자의 층간 절연막 형성 방법에 관한 것이다.The present invention relates to a method of forming an interlayer insulating film of a semiconductor device, and more particularly, to a method of forming an interlayer insulating film of a semiconductor device capable of preventing the occurrence of defects due to the discharge of a dopant contained in a BPSG (Borophospho Silicate Glass) Forming method.
일반적으로 반도체 소자의 제조 공정에서 도전층간의 전기적 절연 및 평탄화를 위하여 층간 절연막을 형성한다.Generally, an interlayer insulating film is formed for electrical insulation and planarization between conductive layers in a semiconductor device manufacturing process.
종래에는 제 1a 도에 도시된 바와 같이 실리콘 기판(1)상에 게이트 산화막(3) 및 폴리실리콘층(4)을 순차적으로 형성하고 패터닝하여 게이트전극(5)을 형성한 후 상기 게이트 전극(5) 양측벽에 산화막 스페이서(6)를 형성한다. 그리고 불순물 이온을 주입 공정으로 상기 게이트 전극(5) 양측부의 상기 실리콘 기판(1)에 접합 영역(2)을 형성하여 트랜지스터의 형성을 완료한 후 표면의 평탄화 및 도전층간의 절연을 위하여 상기 실리콘 기판(1)상에 층간 절연막을 형성하는데, 상기 층간 절연막은 다음과 같은 방법에 의해 형성된다.1A, a gate oxide film 3 and a polysilicon layer 4 are sequentially formed and patterned on a silicon substrate 1 to form a gate electrode 5, and then the gate electrode 5 ) Oxide spacers 6 are formed on both side walls. Then, a junction region 2 is formed in the silicon substrate 1 on both sides of the gate electrode 5 by the impurity ion implantation process to complete the formation of the transistor. Then, for planarization of the surface and insulation between the conductive layers, An interlayer insulating film is formed on the substrate 1, and the interlayer insulating film is formed by the following method.
먼저, 상기와 같이 소자 제조 공정을 거친 상기 실리콘 기판(1)상에 제 1 산화막(7)을 형성한다. 그리고 상기 제 1 산화막(7)상에 BPSG막(8)을 도포하고 플로우(Flow)시켜 표면을 평탄화시킨 후 상기 BPSG막(8)상에 제 2 산화막(9)을 형성한다. 그런데 상기와 같이 형성된 층간 절연막은 후속 열처리 공정시 결함의 발생으로 인해 막의 질이 저하되는데, 이는 상기 BPSG(8)내에 함유된 도펀트가 열에 의해 외부로 배출되고, 이에 의해 제 1B 도에 도시된 바와 같이 상기 BPSG막(8)과 제 2 산화막(9)의 계면에 결함(A 부분)이 발생되기 때문이다. 그러므로 상기 결함(A 부분)에 의해 도전층간의 절연이 저하되어 소자의 신뢰성이 저하되고, 불량이 발생되어 소자의 수율이 저하된다.First, the first oxide film 7 is formed on the silicon substrate 1 having undergone the device manufacturing process as described above. Then, a BPSG film 8 is applied on the first oxide film 7 and is flowed to planarize the surface, and then a second oxide film 9 is formed on the BPSG film 8. However, in the interlayer insulating film formed as described above, the quality of the film is lowered due to occurrence of defects in a subsequent heat treatment process, because the dopant contained in the BPSG 8 is discharged to the outside by heat, (A portion) is generated at the interface between the BPSG film 8 and the second oxide film 9 as shown in FIG. Therefore, the insulation between the conductive layers is deteriorated by the above-mentioned defects (A portion), the reliability of the device is lowered, and defects are generated, and the yield of the device is lowered.
따라서 본 발명은 BPSG막을 도포한 후 상기 BPSG막상에 보호막을 형성한다. 그리고 플로우 공정을 실시하여 상기 BPSG막의 표면을 평탄화시킨 후 상기 보호막을 제거하므로써 상기한 단점을 해소할 수 있는 반도체 소자의 층간 절연막 형성 방법을 제공하는 데 그 목적이 있다.Therefore, the present invention forms a protective film on the BPSG film after applying the BPSG film. It is another object of the present invention to provide a method of forming an interlayer insulating film of a semiconductor device, which can solve the above-mentioned disadvantages by performing a flow process, planarizing the surface of the BPSG film, and removing the protective film.
상기한 목적을 달성하기 위한 본 발명은 소자 제조 공정을 거친 실리콘 기판상에 제 1 산화막을 형성한 후 상기 제 1 산화막상에 BPSG막을 도포하는 단계와, 상기 단계로부터 상기 BPSG막상에 보호막을 형성한 후 플로우 공정을 실시하여 상기 BPSG막을 평탄화시키는 단계와, 상기 단계로부터 상기 보호막을 제거한 후 상기 BPSG막상에 제 2 산화막을 형성하는 단계로 이루어지는 것을 특징으로 한다.According to another aspect of the present invention, there is provided a method of manufacturing a semiconductor device, comprising: forming a first oxide layer on a silicon substrate after a device fabrication process; applying a BPSG layer on the first oxide layer; forming a protective layer on the BPSG layer Performing a post-flow process to planarize the BPSG film; and removing the protective film from the BPSG film and forming a second oxide film on the BPSG film.
이하, 첨부된 도면을 참조하여 본 발명을 상세히 설명하기로 한다.Hereinafter, the present invention will be described in detail with reference to the accompanying drawings.
제 2a 내지 제 2d 도는 본 발명에 따른 반도체 소자의 층간 절연막 형성 방법을 설명하기 위한 소자의 단면도로서,Figs. 2a to 2d are cross-sectional views of a device for explaining a method of forming an interlayer insulating film of a semiconductor device according to the present invention,
제 2a 도는 실리콘 기판(11)상에 게이트 산화막(13) 및 폴리실리콘층(14)을 순차적으로 형성하고 패터닝하여 게이트 전극(15)을 형성한 후 상기 게이트 전극(15) 양측벽에 산화막 스페이서(16)를 형성한다. 그리고 불순물 이온을 주입 공정으로 상기 게이트 전극(15) 양측부의 상기 실리콘 기판(11)에 접합 영역(12)을 형성하여 트랜지스터의 형성을 완료한 상태의 단면도이다.2A and 2B, a gate oxide film 13 and a polysilicon layer 14 are sequentially formed on a silicon substrate 11 and patterned to form a gate electrode 15. Then, oxide spacers (not shown) are formed on both sidewalls of the gate electrode 15 16). And a junction region 12 is formed in the silicon substrate 11 on both sides of the gate electrode 15 by an impurity ion implantation process to form a transistor.
제 2b 도는 상기와 같이 소자 제조 공정을 거친 상기 실리콘 기판(11)상에 제 1 산화막(17)을 형성한 후 상기 제 1 산화막(17)상에 BPSG막(18)을 도포한 상태의 단면도이다.2b is a cross-sectional view of the BPSG film 18 formed on the first oxide film 17 after the first oxide film 17 is formed on the silicon substrate 11 through the device manufacturing process as described above .
제 2c 도는 상기 BPSG막(18)상에 보호막(19)을 250 내지 350Å의 두께로 형성한 후 플로우 공정을 실시하여 상기 BPSG막(18)을 평탄화시킨 상태의 단면도로서, 상기 보호막(19)은 불순물 이온이 도핑되지 않은 산화막으로 형성한다.FIG. 2c is a cross-sectional view of the BPSG film 18 formed on the BPSG film 18 with a thickness of 250 to 350 Å and then subjected to a flow process to planarize the BPSG film 18, The impurity ions are formed by an undoped oxide film.
제 2d 도는 블랜켄(Blanket) 식각 방법으로 상기 보호막(19)을 제거한 후 상기 BPSG막(18)상에 제 2 산화막(20)을 형성하여 층간 절연막의 형성을 완료한 상태의 단면도로서, 상기 플로우 공정시 상기 BPSG막(18)으로부터 배출되는 도펀트에 의해 결함이 발생되더라도 상기 플로우 공정후 상기 보호막(19)을 제거하기 때문에 상기 BPSG막(18)의 표면 상태가 양호하게 유지되며, 상기 제 2 산화막(20)에 의해 후속 열처리 공정시 상기 BPSG막(18)에 함유된 도펀트의 배출이 방지된다. 이때 상기 제 2 산화막(20)은 150 내지 250Å의 두게로 형성되며, 플라즈마 화학 기상 증착(Plasma Enhanced CVD; PECVD) 방법으로 저온에서 TEOS를 소오스 가스로 이용하여 짧은 시간동안 형성하기 때문에 후속 열처리 공정시 상기 BPSG막(18)의 표면을 보호하는 역할을 한다.2d is a cross-sectional view of a state in which the protective film 19 is removed by a Blanket etching method and then a second oxide film 20 is formed on the BPSG film 18 to form an interlayer insulating film, Even if a defect is generated by the dopant discharged from the BPSG layer 18 during the process, since the protective layer 19 is removed after the flow process, the surface state of the BPSG layer 18 is maintained satisfactorily, (20) prevents the dopant contained in the BPSG film (18) from being discharged during the subsequent heat treatment process. Since the second oxide film 20 is formed in a thickness of 150 to 250 angstroms and is formed by plasma enhanced chemical vapor deposition (PECVD) using TEOS as a source gas at a low temperature for a short time, And serves to protect the surface of the BPSG film 18.
상술한 바와 같이 본 발명에 의하면 BPSG막을 도포한 후 상기 BPSG막상에 보호막을 형성한다. 그리고 플로우 공정을 실시하여 상기 BPSG막의 표면을 평탄화시킨 후 상기 보호막을 제거하고 상기 BPSG막상에 산화막을 형성한다. 따라서 후속 열처리 공정시 상기 보호막에 의해 상기 BPSG막에 함유된 도펀트의 배출에 의한 결함의 발생이 방지되어 소자의 절연 특성이 향상되며, 불량의 발생이 방지되어 소자의 수율이 향상될 수 있는 탁월한 효과가 있다.As described above, according to the present invention, after the BPSG film is coated, a protective film is formed on the BPSG film. After the surface of the BPSG film is planarized by a flow process, the protective film is removed and an oxide film is formed on the BPSG film. Therefore, it is possible to prevent the generation of defects due to the discharge of the dopant contained in the BPSG film by the protective film during the subsequent heat treatment step, to improve the insulating property of the device, to prevent the occurrence of defects and to improve the yield of the device .
Claims (4)
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| KR1019960022783A KR100223288B1 (en) | 1996-06-21 | 1996-06-21 | Method of fabrication isolation film of semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| KR1019960022783A KR100223288B1 (en) | 1996-06-21 | 1996-06-21 | Method of fabrication isolation film of semiconductor device |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| KR980005806A KR980005806A (en) | 1998-03-30 |
| KR100223288B1 true KR100223288B1 (en) | 1999-10-15 |
Family
ID=19462792
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| KR1019960022783A KR100223288B1 (en) | 1996-06-21 | 1996-06-21 | Method of fabrication isolation film of semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| KR (1) | KR100223288B1 (en) |
Families Citing this family (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR100872981B1 (en) * | 2007-07-19 | 2008-12-08 | 주식회사 동부하이텍 | Method of fabricating semiconductor |
-
1996
- 1996-06-21 KR KR1019960022783A patent/KR100223288B1/en not_active IP Right Cessation
Also Published As
| Publication number | Publication date |
|---|---|
| KR980005806A (en) | 1998-03-30 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| US7094672B2 (en) | Method for forming self-aligned contact in semiconductor device | |
| US6440817B2 (en) | Methods of forming integrated circuitry | |
| US5652176A (en) | Method for providing trench isolation and borderless contact | |
| KR100338778B1 (en) | Method for fabricating MOS transistor using selective silicide process | |
| US6573168B2 (en) | Methods for forming conductive contact body for integrated circuits using dummy dielectric layer | |
| US20050106888A1 (en) | Method of in-situ damage removal - post O2 dry process | |
| US6468904B1 (en) | RPO process for selective CoSix formation | |
| JP2001358214A (en) | Semiconductor device and its manufacturing method | |
| KR960002073B1 (en) | Fabricating method of semiconductor device | |
| JP2007516598A (en) | PECVD silicon-rich silicon oxide layer to reduce UV charging | |
| US6686286B2 (en) | Method for forming a borderless contact of a semiconductor device | |
| JP2000223573A (en) | Integrated circuit element having flat inter-level dielectric layer | |
| KR100252039B1 (en) | Method for forming a self-aligned contact hole | |
| US7825030B2 (en) | Method of forming a spacer | |
| KR100223288B1 (en) | Method of fabrication isolation film of semiconductor device | |
| US6294449B1 (en) | Self-aligned contact for closely spaced transistors | |
| KR100301530B1 (en) | Mehtod for forming inter layer insulting film in the semiconductor device | |
| KR20090057730A (en) | Method for forming inter layer dielectrics of semiconductor device | |
| JPH0917869A (en) | Preparation of insulation film between metal wirings of semiconductor element | |
| KR100688023B1 (en) | Method of fabricating semiconductor device | |
| US6806208B2 (en) | Semiconductor device structured to prevent oxide damage during HDP CVD | |
| JP3543504B2 (en) | Method for manufacturing semiconductor device | |
| JPH09260366A (en) | Manufacture of semiconductor device | |
| KR100899567B1 (en) | Method for fabricating semiconductor device with gate-electrode including tungsten | |
| KR100313785B1 (en) | Method for forming interlayer dielectric of semiconductor device |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| A201 | Request for examination | ||
| E902 | Notification of reason for refusal | ||
| E701 | Decision to grant or registration of patent right | ||
| GRNT | Written decision to grant | ||
| FPAY | Annual fee payment |
Payment date: 20070622 Year of fee payment: 9 |
|
| LAPS | Lapse due to unpaid annual fee |