KR20020050467A - Pad of semiconductor device and method for fabricating the same - Google Patents
Pad of semiconductor device and method for fabricating the same Download PDFInfo
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- KR20020050467A KR20020050467A KR1020000079618A KR20000079618A KR20020050467A KR 20020050467 A KR20020050467 A KR 20020050467A KR 1020000079618 A KR1020000079618 A KR 1020000079618A KR 20000079618 A KR20000079618 A KR 20000079618A KR 20020050467 A KR20020050467 A KR 20020050467A
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- metal pad
- pad
- interlayer insulating
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- upper portion
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- 238000000034 method Methods 0.000 title claims abstract description 21
- 239000004065 semiconductor Substances 0.000 title abstract description 23
- 239000002184 metal Substances 0.000 claims abstract description 103
- 239000011229 interlayer Substances 0.000 claims abstract description 37
- 239000010410 layer Substances 0.000 claims abstract description 21
- 238000002161 passivation Methods 0.000 claims abstract description 12
- 239000011521 glass Substances 0.000 claims description 4
- 239000005368 silicate glass Substances 0.000 claims description 2
- 238000005530 etching Methods 0.000 claims 1
- 230000015572 biosynthetic process Effects 0.000 abstract 1
- BOTDANWDWHJENH-UHFFFAOYSA-N Tetraethyl orthosilicate Chemical compound CCO[Si](OCC)(OCC)OCC BOTDANWDWHJENH-UHFFFAOYSA-N 0.000 description 4
- 238000011156 evaluation Methods 0.000 description 3
- 150000004767 nitrides Chemical class 0.000 description 3
- QZPSXPBJTPJTSZ-UHFFFAOYSA-N aqua regia Chemical compound Cl.O[N+]([O-])=O QZPSXPBJTPJTSZ-UHFFFAOYSA-N 0.000 description 2
- 230000007547 defect Effects 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 238000007517 polishing process Methods 0.000 description 1
- 239000000126 substance Substances 0.000 description 1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/02—Bonding areas ; Manufacturing methods related thereto
- H01L24/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L24/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
- H01L21/60—Attaching or detaching leads or other conductive members, to be used for carrying current to or from the device in operation
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/02—Bonding areas ; Manufacturing methods related thereto
- H01L24/03—Manufacturing methods
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
- H01L2224/05001—Internal layers
- H01L2224/05075—Plural internal layers
- H01L2224/0508—Plural internal layers being stacked
- H01L2224/05085—Plural internal layers being stacked with additional elements, e.g. vias arrays, interposed between the stacked layers
- H01L2224/05089—Disposition of the additional element
- H01L2224/05093—Disposition of the additional element of a plurality of vias
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
- H01L2224/0554—External layer
- H01L2224/0555—Shape
- H01L2224/05556—Shape in side view
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- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Manufacturing & Machinery (AREA)
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- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
- Wire Bonding (AREA)
Abstract
Description
본 발명은 반도체 소자에 대한 것으로, 특히 패드 공정 진행 후 신뢰성 평가(볼 쉬어 테스트(Ball Shear Test))시에 페일(fail) 발생을 제거하기에 알맞은반도체소자의 패드 및 그 형성방법에 관한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device, and more particularly, to a pad of a semiconductor device suitable for eliminating a failure during a reliability evaluation (Ball Shear Test) after a pad process and a method of forming the same.
금속 패드의 층간절연막으로 다른 산화막에 비해서 저유전율을 갖는 SOG를 사용한다.As the interlayer insulating film of the metal pad, SOG having a lower dielectric constant than other oxide films is used.
그러나 이 SOG는 다른 산화막에 비해 막의 내구력(strength)이 약하여 패드 공정 진행후 신뢰성 평가중에 패드 불량 문제를 야기시킨다.However, this SOG has a weaker strength than other oxide films, causing a problem of pad failure during reliability evaluation after the pad process.
또한 이문제를 해결하기 위해서 SOG(Spin On Glass)의 내구력을 강화시키면 SOG의 내구력이 강화되는 것과는 상대적으로 유전율이 증가하는 문제가 발생된다.In addition, in order to solve this problem, increasing the durability of SOG (Spin On Glass) causes a problem of increasing the dielectric constant relative to increasing the durability of SOG.
이에 증간절연막으로 SOG를 사용하면서 상기의 신뢰성 평가시 불량을 야기하지 않는 패드 형성방법이 연구되고 있다.Accordingly, a method of forming a pad that does not cause a defect in the reliability evaluation while using SOG as an interlayer insulating film has been studied.
첨부 도면을 참조하여 종래 반도체소자의 패드 및 그 형성방법에 대하여 설명하면 다음과 같다.Referring to the accompanying drawings, a pad of a conventional semiconductor device and a method of forming the same will be described below.
도 1은 종래 기술에 따른 반도체소자의 패드를 나타낸 구조 단면도이고, 도 2a 내지 도 2e는 종래 기술에 따른 반도체소자의 패드 형성방법을 나타낸 공정단면도이다.1 is a cross-sectional view illustrating a pad of a semiconductor device according to the prior art, and FIGS. 2A to 2E are cross-sectional views illustrating a method of forming a pad of the semiconductor device according to the prior art.
종래 반도체소자의 패드는 도 1에 도시한 바와 같이 일정폭을 갖는 제 1 금속 패드(1)이 있고, 제 1 금속패드(1)의 가장자리 상부가 드러나도록 비아홀을 갖는 층간절연막(2)이 있고, 비아홀 및 제 1 금속패드(1) 상측의 층간절연막(2)상에 제 2 금속패드(4a)가 형성되어 있고, 제 2 금속패드(4a)가 상부가 드러나도록 페시베이션막(5)이 형성되어 있다.As shown in FIG. 1, a pad of a semiconductor device includes a first metal pad 1 having a predetermined width, and an interlayer insulating film 2 having a via hole so that an upper edge of the first metal pad 1 is exposed. , The second metal pad 4a is formed on the via hole and the interlayer insulating film 2 on the upper side of the first metal pad 1, and the passivation film 5 is disposed so that the second metal pad 4a is exposed. Formed.
그리고 상기와 같은 구성을 갖는 종래 반도체소자의 패드 형성방법은 도 2a에 도시한 바와 같이 일정폭을 갖도록 제 1 금속층을 식각하여 제 1 금속 패드(1)를 형성하고, 제 1 금속 패드(1)를 포함하도록 층간절연막(2)을 증착한다.In the method of forming a pad of a conventional semiconductor device having the above configuration, as shown in FIG. 2A, the first metal layer is etched to form a first metal pad 1 to have a predetermined width, and the first metal pad 1 is formed. The interlayer insulating film 2 is deposited to include.
이후에 제 1 금속 패드(1)의 양 가장자리 상부에 비아홀을 갖도록 층간절연막(2)을 식각한다.Thereafter, the interlayer insulating film 2 is etched to have via holes on both edges of the first metal pad 1.
그리고 도 2b에 도시한 바와 같이 비아홀을 포함한 층간절연막(2)상에 제 2 금속층(4)을 증착한다.As shown in FIG. 2B, the second metal layer 4 is deposited on the interlayer insulating film 2 including the via holes.
그리고 도 2c에 도시한 바와 같이 제 2 금속층(4)을 식각해서 비아홀과 제 1 금속 패드(1) 상측의 층간절연막(2)상에 제 2 금속패드(4a)를 형성한다.As shown in FIG. 2C, the second metal layer 4 is etched to form the second metal pad 4a on the via hole and the interlayer insulating film 2 above the first metal pad 1.
이후에 도 2d에 도시한 바와 같이 제 2 금속패드(4a)를 포함한 층간절연막(2) 전면에 TEOS나 질화막으로 구성된 페시베이션막(5)을 증착한다.Thereafter, as illustrated in FIG. 2D, a passivation film 5 composed of TEOS or a nitride film is deposited on the entire surface of the interlayer insulating film 2 including the second metal pad 4a.
그리고 도 2e에 도시한 바와 같이 제 2 금속패드(4a)의 상부가 드러나도록 페시베이션막(5)을 식각한다.As shown in FIG. 2E, the passivation film 5 is etched so that the upper portion of the second metal pad 4a is exposed.
상기와 같은 종래 반도체소자의 패드 및 그 형성방법은 다음과 같은 문제가 있다.The pad and the method of forming the conventional semiconductor device as described above has the following problems.
첫째, 차후에 와이어 본딩 작업을 할 때 볼(Ball)에 패드 하층의 층간절연막 일부가 붙어서 떨어지는 문제와, 차후에 볼 쉬어 테스트에서 30gf 이상에서 볼에 패드 하층의 층간절연막의 일부가 붙어서 떨어지는 문제가 발생할 수 있다.First, when the wire bonding operation is performed later, a part of the interlayer insulating layer under the pad may adhere to the ball and fall off, and a part of the interlayer insulating layer under the pad may adhere to the ball at more than 30 gf in the ball shear test. have.
둘째, 차후에 볼 쉬어 테스트 이전 시료를 왕수에 식각할 때 패드 하층이 손상되는 문제가 발생할 수 있다.Secondly, the lower layer of the pad may be damaged when the sample is later etched into the aqua regia before the ball rest test.
본 발명은 상기와 같은 문제를 해결하기 위하여 안출한 것으로 특히, 금속 패드 공정 후에 발생하는 볼 쉬어 테스트 페일(Ball Shear Test Fail)을 제거하기에 알맞은 반도체소자의 패드 및 그 형성방법을 제공하는데 그 목적이 있다.The present invention has been made to solve the above problems, and in particular, to provide a pad and a method of forming a semiconductor device suitable for removing the Ball Shear Test Fail generated after the metal pad process. There is this.
도 1은 종래 기술에 따른 반도체소자의 패드를 나타낸 구조 단면도1 is a structural cross-sectional view showing a pad of a semiconductor device according to the prior art
도 2a 내지 도 2e는 종래 기술에 따른 반도체소자의 패드 형성방법을 나타낸 공정단면도2A through 2E are cross-sectional views illustrating a method of forming a pad of a semiconductor device according to the related art.
도 3은 본 발명 실시예에 따른 반도체소자의 패드를 나타낸 구조 단면도3 is a cross-sectional view illustrating a pad of a semiconductor device in accordance with an embodiment of the present invention.
도 4a 내지 도 4f는 본 발명 실시예에 따른 반도체소자의 패드 형성방법을 나타낸 공정단면도4A through 4F are cross-sectional views illustrating a method of forming a pad of a semiconductor device in accordance with an embodiment of the present invention.
도면의 주요 부분에 대한 부호의 설명Explanation of symbols for the main parts of the drawings
41 : 제 1 금속 패드 42 : 층간절연막41: first metal pad 42: interlayer insulating film
43 : 제 2 금속층 43a : 제 2 금속 패드43: second metal layer 43a: second metal pad
44 : 페시베이션막44: passivation film
상기와 같은 목적을 달성하기 위한 본 발명 반도체소자의 패드는 일정폭을 갖고 형성된 제 1 금속패드, 상기 제 1 금속패드의 전체 상부와 직접 연결되도록 그 상부에 형성된 제 2 금속패드, 상기 제 1, 제 2 금속패드와 일정 간격 격리되어 형성된 층간절연막, 상기 제 2 금속패드의 상부가 드러나도록 상기 전면에 형성된 페시베이션막을 포함함을 특징으로 한다.The pad of the semiconductor device of the present invention for achieving the above object is a first metal pad having a predetermined width, a second metal pad formed on the upper portion of the first metal pad to be directly connected to the entire upper portion of the first metal pad, And an interlayer insulating film formed to be separated from the second metal pad by a predetermined distance, and a passivation film formed on the front surface of the second metal pad to expose the upper portion of the second metal pad.
상기와 같은 구성을 갖는 본 발명 반도체소자의 패드 형성방법은 일정폭을 갖도록 제 1 금속패드를 형성하는 공정, 상기 제 1 금속패드의 상부가 드러나도록 층간절연막을 형성하는 공정, 상기 제 1 금속패드 상부와 직접 연결되도록 제 2 금속패드를 형성하는 공정, 상기 제 2 금속패드의 상부가 드러나도록 상기 전면에 페시베이션막을 형성하는 공정을 포함함을 특징으로 한다.The method of forming a pad of a semiconductor device according to the present invention having the above structure includes the steps of forming a first metal pad to have a predetermined width, a step of forming an interlayer insulating film to expose an upper portion of the first metal pad, and the first metal pad. And forming a passivation film on the front surface of the second metal pad so that the upper portion of the second metal pad is exposed.
첨부 도면을 참조하여 본 발명 반도체소자의 패드 및 그 형성방법에 대하여 설명하면 다음과 같다.A pad and a method of forming the semiconductor device of the present invention will be described with reference to the accompanying drawings.
도 3은 본 발명 실시예에 따른 반도체소자의 패드를 나타낸 구조 단면도이고, 도 4a 내지 도 2f는 본 발명 실시예에 따른 반도체소자의 패드 형성방법을 나타낸 공정단면도 이다.3 is a cross-sectional view illustrating a pad of a semiconductor device according to an exemplary embodiment of the present invention, and FIGS. 4A to 2F are cross-sectional views illustrating a method of forming a pad of a semiconductor device according to an exemplary embodiment of the present invention.
본 발명 실시예에 따른 반도체소자의 패드는 도 3에 도시한 바와 같이 일정폭으로 패턴된 제 1 금속 패드(41)가 있고, 제 1 금속 패드(41)이 드러나며 그 양측면에서 일정폭만큼 떨어진 영역에 층간절연막(42)이 형성되어 있고, 제 1 금속 패드(41)를 감싸도록 제 2 금속 패드(43a)가 형성되어 있다.In the pad of the semiconductor device according to the embodiment of the present invention, as shown in FIG. 3, the first metal pad 41 is patterned with a predetermined width, and the first metal pad 41 is exposed and is separated by a predetermined width from both sides thereof. An interlayer insulating film 42 is formed on the second metal pad 43a so as to surround the first metal pad 41.
이때 제 2 금속 패드(43a)는 비아홀을 통하지 않고 상기에서와 같이 제 1 금속 패드(41)와 직접 연결되어 있다.In this case, the second metal pad 43a is directly connected to the first metal pad 41 as described above without passing through the via hole.
그리고 제 2 금속 패드(43a)의 상부가 드러나도록 제 2 금속 패드(43a)와 층간절연막(42)의 사이 및 층간절연막(42) 상에 TEOS나 질화막으로 구성된 페시베이션막(44)이 형성되어 있다.A passivation film 44 composed of TEOS or a nitride film is formed between the second metal pad 43a and the interlayer insulating film 42 and on the interlayer insulating film 42 so that the upper portion of the second metal pad 43a is exposed. have.
상기의 구성을 갖는 본 발명 반도체소자의 패드 형성방법은 도 4a에 도시한 바와 같이 일정폭을 갖도록 제 1 금속층을 식각해서 제 1 금속 패드(41)를 형성한다.In the method for forming a pad of the semiconductor device of the present invention having the above configuration, the first metal layer is etched to form a first metal pad 41 to have a predetermined width as shown in FIG. 4A.
그리고 제 1 금속 패드(41)를 감싸도록 SOG(Spin On Glass)로 구성된 층간절연막(42)을 형성한다.An interlayer insulating layer 42 made of SOG (Spin On Glass) is formed to surround the first metal pad 41.
그리고 도 4b에 도시한 바와 같이 제 1 금속 패드(41) 상부가 드러나며 층간절연막(42)이 제 1 금속 패드(41)의 측면과 일정간격 떨어지도록 층간절연막(42)을 식각한다.4B, the interlayer insulating layer 42 is etched so that the upper portion of the first metal pad 41 is exposed and the interlayer insulating layer 42 is spaced apart from the side surface of the first metal pad 41 by a predetermined distance.
이후에 도 4c에 도시한 바와 같이 제 1 금속 패드(41)와 층간절연막(42)을 포함한 전면에 제 2 금속층(43)을 증착한다.Thereafter, as illustrated in FIG. 4C, a second metal layer 43 is deposited on the entire surface including the first metal pad 41 and the interlayer insulating layer 42.
그리고 도 4d에 도시한 바와 같이 층간절연막(42)과 일정 간격 격리되고 제 1 금속 패드(41)의 둘레에만 남도록 제 2 금속층(43)을 식각해서 제 2 금속패드(43a)를 형성한다.As shown in FIG. 4D, the second metal layer 43 is etched so as to be separated from the interlayer insulating film 42 at a predetermined interval and remain only around the first metal pad 41 to form the second metal pad 43a.
이때 제 2 금속 패드(43a)는 제 1 금속 패드(41)와 비아홀을 통하지 않고 직접 연결된다.In this case, the second metal pad 43a is directly connected to the first metal pad 41 without passing through the via hole.
그리고 도 4e에 도시한 바와 같이 상기 제 2 금속 패드(43a)와 층간절연막(42)을 포함한 전면에 TEOS(Tetra Ethyl Ortho Silicate)나 질화막으로 구성된 페시베이션막(44)을 증착한다.As shown in FIG. 4E, a passivation film 44 composed of TEOS (Tetra Ethyl Ortho Silicate) or a nitride film is deposited on the entire surface including the second metal pad 43a and the interlayer insulating film 42.
이후에 도 4f에 도시한 바와 같이 제 2 금속 패드(43a)의 상부가 드러나도록 페시베이션막(44)을 식각한다.Afterwards, the passivation film 44 is etched to expose the upper portion of the second metal pad 43a as shown in FIG. 4F.
상기에서와 같이 제 1 금속 패드(41)가 형성되는 지역을 완전히 오픈해서 제 2 금속 패드(43a)와 제 1 금속 패드(41)가 접촉하는 면을 최대화하여서 차후에 와이어 본딩시 페일이 발생하는 것을 줄인다.As described above, the area in which the first metal pad 41 is formed is completely opened to maximize the surface where the second metal pad 43a and the first metal pad 41 come into contact with each other. Reduce
상기에서 층간절연막(42)으로 SOG 대신 HDP-USG(High Density Plasma-Undoped Silicate Glass)를 증착한 후 화학적 기계적 연마공정을 진행하여서 제 1 금속패드(41)의 상부만 드러나게 하고, 차후에 제 1 금속패드(41)의 상부에서만 접촉되도록 제 2 금속패드(43a)를 형성할 수도 있다.In the above, the HDP-USG (High Density Plasma-Undoped Silicate Glass) is deposited on the interlayer dielectric layer 42 instead of the SOG, and the chemical mechanical polishing process is performed to expose only the upper portion of the first metal pad 41. The second metal pad 43a may be formed so as to contact only the upper portion of the pad 41.
그리고 제 1 금속 패드(41)를 헤치형(Hatch type)으로 형성할 수도 있다.In addition, the first metal pad 41 may be formed in a hatch type.
상기와 같은 본 발명 반도체소자의 패드 및 그 형성방법은 다음과 같은 효과가 있다.The pad and the method of forming the semiconductor device of the present invention as described above has the following effects.
첫째, 제 1 금속 패드 주변의 층간절연막을 식각하여서 제 2 금속 패드가 제1 금속 패드를 직접 감싸도록 하므로써, 와이어 본딩 작업시 기계적 충돌을 받는 SOG(Spin On Glass)로 구성된 층간절연막을 금속패드 주변에서 완전히 제거하므로써 금속패드의 필링(Peeling) 문제를 해결할 수 있다.First, the interlayer insulating film around the first metal pad is etched so that the second metal pad directly surrounds the first metal pad, so that the interlayer insulating film composed of SOG (Spin On Glass) subjected to mechanical collision during wire bonding is applied. This can be eliminated by peeling the metal pad completely.
둘째, 제 1 금속 패드 주변의 층간절연막을 식각하여서 제 2 금속 패드가 제 1 금속 패드를 직접 감싸도록 하여서 제 2 금속 패드 하부에 층간절연막이 존재하지 않게 하므로써, 차후에 와이어 본딩 작업을 할 때 볼(Ball)에 금속 패드 하층의 층간절연막 일부가 붙어서 떨어지는 문제와, 차후에 볼 쉬어 테스트에서 30gf 이상에서 볼에 금속 패드 하층의 층간절연막의 일부가 붙어서 떨어지는 문제의 발생을 미연에 방지할 수 있다.Secondly, the interlayer insulating film around the first metal pad is etched so that the second metal pad directly surrounds the first metal pad so that the interlayer insulating film does not exist under the second metal pad, thereby making it possible to see the ball when the wire bonding operation is performed later. It is possible to prevent the occurrence of a problem that a part of the interlayer insulating film of the metal pad lower layer sticks and falls, and a problem of a part of the interlayer insulating film of the metal pad lower layer sticking to the ball later than 30 gf in a ball shear test.
셋째, 제 2 금속 패드가 제 1 금속 패드를 직접 감싸도록 하여서 제 2 금속 패드 하부에 층간절연막이 존재하지 않으므로, 차후에 볼 쉬어 테스트 이전 시료를 왕수에 식각할 때 금속패드 하층이 손상되는 문제의 발생을 미연에 방지할 수 있다.Third, since the interlayer insulating film does not exist under the second metal pad so that the second metal pad directly surrounds the first metal pad, there is a problem that the lower layer of the metal pad is damaged when the sample is etched into the aqua regia after the ball rest test. Can be prevented in advance.
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| KR100543867B1 (en) * | 2003-01-30 | 2006-01-20 | 동부아남반도체 주식회사 | Wide memory pattern for finding defect easily at memory or embeded memory device |
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| KR100543867B1 (en) * | 2003-01-30 | 2006-01-20 | 동부아남반도체 주식회사 | Wide memory pattern for finding defect easily at memory or embeded memory device |
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