KR20020046776A - structure for mounting chip scale package on PCB - Google Patents
structure for mounting chip scale package on PCB Download PDFInfo
- Publication number
- KR20020046776A KR20020046776A KR1020000077107A KR20000077107A KR20020046776A KR 20020046776 A KR20020046776 A KR 20020046776A KR 1020000077107 A KR1020000077107 A KR 1020000077107A KR 20000077107 A KR20000077107 A KR 20000077107A KR 20020046776 A KR20020046776 A KR 20020046776A
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- South Korea
- Prior art keywords
- chip
- circuit
- circuit board
- scale package
- chip scale
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Classifications
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- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K1/00—Printed circuits
- H05K1/18—Printed circuits structurally associated with non-printed electric components
- H05K1/181—Printed circuits structurally associated with non-printed electric components associated with surface mounted components
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
- H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
- H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
- H01L23/3114—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed the device being a chip scale package, e.g. CSP
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- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/30—Assembling printed circuits with electric components, e.g. with resistor
- H05K3/32—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits
- H05K3/34—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits by soldering
- H05K3/3457—Solder materials or compositions; Methods of application thereof
- H05K3/3478—Applying solder preforms; Transferring prefabricated solder patterns
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/50—Tape automated bonding [TAB] connectors, i.e. film carriers; Manufacturing methods related thereto
Abstract
Description
본 발명은 칩스케일 패키지의 회로기판에의 실장구조 에 관한 것으로서, 더욱 상세하게는 칩스케일 패키지의 단자 구조 및 회로기판의 단자 구조 개선을 통해 실장이 용이하게 이루어질 수 있도록 함과 더불어 실장 신뢰성을 높일 수 있도록 한 것이다.The present invention relates to a mounting structure of a chip scale package on a circuit board. More specifically, the mounting structure can be easily achieved by improving the terminal structure of the chip scale package and the terminal structure of the circuit board, and also increase the mounting reliability. I would have to.
일반적으로, 마이크로 비·지·에이(μ-BGA) 패키지는 도 1에 나타낸 바와 같이, 서키트 필름(4)과, 상기 서키트 필름(4)에 부착되는 칩(1)과, 칩(1)과 서키트 필름(4)사이에 개재되어 칩(1)이 서키트 필름(4)에 부착되도록 하는 접착테이프(3)와, 상기 칩(1)의 외부접속단자인 본딩패드(2)와 서키트 필름(4)의 회로패턴을 전기적으로 연결하는 리드(5)와, 상기 칩(1)의 측면 및 리드(5)를 감싸는 봉지제(7)와, 상기 서키트 필름(4)의 칩 부착면 반대쪽의 솔더볼랜드에 부착되는 솔더볼(8)을 포함하여 구성된다.In general, as shown in FIG. 1, a micro B-GA package includes a circuit film 4, a chip 1 attached to the circuit film 4, and a chip 1. An adhesive tape 3 interposed between the circuit film 4 to attach the chip 1 to the circuit film 4, a bonding pad 2, which is an external connection terminal of the chip 1, and the circuit film 4. Leads 5 electrically connecting circuit patterns of the < RTI ID = 0.0 >), < / RTI > an encapsulant 7 surrounding the side and the lead 5 of the chip 1, and solder bores on the opposite side of the chip attaching surface of the circuit film 4; It is configured to include a solder ball (8) attached to.
한편, 이와 같이 구성된 마이크로 비·지·에이 패키지의 제조 과정은 다음과 같다.In addition, the manufacturing process of the micro BG package comprised in this way is as follows.
먼저, 칩(1)에 접착테이프(3)를 붙이고, 상기 접착테이프(3) 위로 서키트 필름(4)을 올린 뒤, 리드 본드 툴(도시는 생략함)을 이용하여 칩(1)의 본딩패드(2)와 서키트 필름(4)의 회로패턴이 전기적으로 연결되도록 리드 본딩을 실시한다.First, the adhesive tape 3 is attached to the chip 1, the circuit film 4 is placed on the adhesive tape 3, and then a bonding pad of the chip 1 is formed using a lead bond tool (not shown). Lead bonding is performed so that the circuit pattern of (2) and the circuit film 4 is electrically connected.
그 다음, 봉지제(7)로 리드(5) 및 칩(1) 측면을 봉지제(7)로 봉지하여 칩(1)의 회로형성면이 보호되도록 한다.Then, the lead 5 and the side of the chip 1 with the sealing agent 7 is sealed with the sealing agent 7 so that the circuit formation surface of the chip 1 is protected.
그 후, 상기 서키트 필름(4)의 칩 부착면 반대쪽에 위치하는 솔더볼랜드에 솔더볼(8)을 부착한다.Thereafter, the solder ball 8 is attached to the solder ball land located on the opposite side of the chip attaching surface of the circuit film 4.
한편, 이와 같은 종래의 마이크로 비·지·에이 패키지는, 서키트 필름(4)에 솔더볼(8)을 고정시키기 위해서는 솔더볼 부착 위치에 플럭스를 묻히고 개개의 솔더볼을 서키트 필름(4)에 얹은 후 열을 가하여 솔더볼을 녹이게 되는 방법을 이용하였다.On the other hand, in order to fix the solder ball 8 to the circuit film 4, such a conventional micro B / A package has a flux applied to the solder ball attachment position, and the individual solder balls are placed on the circuit film 4, and then heat is applied. The method was used to melt the solder ball.
그리고, 칩스케일 패키지를 회로기판(9)에 실장시키기 위해서는 별도의 스크린 프린팅 공정에 의해 솔더페이스트를 회로기판(9) 상에 도포하여야만 하였다.In addition, in order to mount the chip scale package on the circuit board 9, the solder paste had to be applied on the circuit board 9 by a separate screen printing process.
따라서, 종래에는 솔더볼(8)을 서키트 필름(4)상에 얹기 위한 고정밀도의 얼라인 장치가 필요하게 되고, 솔더볼(8)이 얹힌 후에는 리플로우 공정이 수반되어야 하며, 완성된 칩사이즈 패키지를 회로기판(9)에 실장시 추가적으로 회로기판에 솔더페이스트를 도포하는 공정이 수반되어야 하는 등, 제조 과정이 복잡하여 공정이 까다로울 뿐만 아니라 본딩 신뢰성 및 생산성이 저하되는 문제점이 있었다.Therefore, in the related art, a high precision aligning device for mounting the solder ball 8 on the circuit film 4 is required, and after the solder ball 8 is placed, a reflow process is required, and the completed chip size package When the mounting on the circuit board (9) must be accompanied by a process of additionally applying a solder paste on the circuit board, the manufacturing process is complicated, the process is difficult, and there is a problem that the bonding reliability and productivity is lowered.
또한, 종래에는 완성된 칩스케일 패키지를 회로기판(4)에 실장할 때 접속단자가 돌출되어 있을 경우, 얼라인이 제대로 이루어지지 않아 솔더조인트의 접합 신뢰성이 저하될 가능성이 높은 등 많은 문제점이 있었다.In addition, in the related art, when the completed chip scale package is mounted on the circuit board 4, when the connection terminal protrudes, there are many problems such that the alignment is not properly performed and the soldering reliability of the solder joint is high. .
본 발명은 상기한 제반 문제점을 해결하기 위한 것으로서, 칩스케일 패키지의 단자 구조 및 회로기판의 단자 구조를 개선하므로써, 칩스케일 패키지를 회로기판에 실장시 실장작업이 용이하게 이루어질 수 있도록 함과 더불어 실장 신뢰성이 향상되도록 한 칩스케일 패키지의 회로기판에의 실장구조 를 제공하는데 그 목적이 있다.The present invention is to solve the above-mentioned problems, by improving the terminal structure of the chip scale package and the terminal structure of the circuit board, to facilitate the mounting work when mounting the chip scale package on the circuit board as well as mounting The purpose is to provide a mounting structure on a circuit board of a chip scale package to improve the reliability.
도 1은 칩스케일 패키지의 일예를 나타낸 것으로서, 마이크로 비·지·에이 패키지 구조를 나타낸 종단면도1 illustrates an example of a chip scale package, and a longitudinal cross-sectional view illustrating a micro B / A package structure.
도 2는 본 발명에 따른 마이크로 비·지·에이 패키지의 단자 및 회로기판 구조를 나타낸 종단면도로서, 실장전의 상태도Figure 2 is a longitudinal sectional view showing the terminal and the circuit board structure of the micro B / A package according to the present invention, a state diagram before mounting
도 3은 도 2의 실장이 완료된 후의 상태도3 is a state diagram after the mounting of FIG. 2 is completed.
* 도면의 주요부분에 대한 부호의 설명 *Explanation of symbols on the main parts of the drawings
1:칩 2:본딩패드1: chip 2: bonding pad
3:접착테이프 4:서키트 필름3: Adhesive tape 4: Circuit film
5:리드 6:솔더페이스트5: Lead 6: Solder Paste
7:봉지제 8:솔더볼7: encapsulation 8: solder ball
9:회로기판 10:단자홈9: Circuit board 10: Terminal groove
11:접속단자11: Connection terminal
상기한 목적을 달성하기 위해, 본 발명은 서키트 필름과, 상기 서키트 필름에 부착되는 칩과, 상기 칩의 외부접속단자인 본딩패드와 서키트 필름의 회로패턴을 전기적으로 연결하는 리드를 포함하여서 된 칩스케일 패키지와 상기 칩스케일 패키지 실장을 위한 회로기판에 있어서; 상기 서키트 필름의 칩 부착면 반대쪽에 위치한 솔더볼랜드 상에 서키트 필름 외측으로 돌출되도록 소정 두께의 솔더페이스트가 형성되고, 상기 칩스케일 패키지의 솔더볼랜드 위치에 대응하여 회로기판 표면에는 단자홈이 형성되며, 각 단자홈 내에는 상기 칩스케일 패키지의 솔더페이스트와의 결합을 위한 접속단자가 형성됨을 특징으로 하는 칩스케일 패키지의 회로기판에의 실장구조 가 제공된다.In order to achieve the above object, the present invention includes a circuit including a circuit film, a chip attached to the circuit board, and a lead for electrically connecting the circuit pad of the circuit board and the bonding pad which is an external connection terminal of the chip A circuit board for mounting a scale package and the chip scale package; A solder paste having a predetermined thickness is formed on the solder borland opposite the chip attaching surface of the circuit film to protrude out of the circuit film, and terminal grooves are formed on the surface of the circuit board corresponding to the solder borland position of the chip scale package. Each terminal groove is provided with a mounting structure on a circuit board of the chip scale package, characterized in that a connection terminal for coupling with the solder paste of the chip scale package is formed.
이하, 본 발명의 일실시예를 첨부도면 도 2 및 도 3을 참조하여 상세히 설명하면 다음과 같다.Hereinafter, an embodiment of the present invention will be described in detail with reference to FIGS. 2 and 3.
도 2는 본 발명에 따른 마이크로 비·지·에이 패키지의 단자 및 회로기판 구조를 나타낸 종단면도로서, 실장전의 상태도이고, 도 3은 도 2의 실장이 완료된 후의 상태도이다.2 is a longitudinal cross-sectional view showing the terminal and circuit board structure of the micro BG package according to the present invention, which is a state diagram before mounting, and FIG. 3 is a state diagram after the mounting of FIG. 2 is completed.
본 발명은 서키트 필름(4)과, 상기 서키트 필름(4)에 부착되는 칩(1)과, 상기 칩(1)의 외부접속단자인 본딩패드(2)와 서키트 필름(4)의 회로패턴을 전기적으로 연결하는 리드(5)를 포함하여서 된 칩스케일 패키지와 상기 칩스케일 패키지 실장을 위한 회로기판(9)에 있어서; 상기 서키트 필름(1)의 칩 부착면 반대쪽에 위치한 솔더볼랜드 상에 서키트 필름(1) 외측으로 돌출되도록 소정 두께의 솔더페이스트(6)가 형성되고, 상기 칩스케일 패키지의 솔더볼랜드 위치에 대응하여 회로기판(9) 표면에는 단자홈(10)이 형성되며, 상기 각 단자홈(10) 내에는 상기 칩스케일 패키지의 솔더페이스트(6)와의 결합을 위한 접속단자(11)가 형성된 것이다.According to the present invention, circuit patterns of the circuit film 4, the chip 1 attached to the circuit film 4, the bonding pads 2 and the circuit film 4, which are external connection terminals of the chip 1, are formed. A chip scale package including a lead (5) for electrically connecting and a circuit board (9) for mounting the chip scale package; A solder paste 6 having a predetermined thickness is formed on a solder ball land opposite to the chip attaching surface of the circuit film 1 so as to protrude out of the circuit film 1, and the circuit corresponds to the solder ball land position of the chip scale package. A terminal groove 10 is formed on the surface of the substrate 9, and a connection terminal 11 for coupling with the solder paste 6 of the chip scale package is formed in each terminal groove 10.
이 때, 상기 서키트 필름(4)의 솔더볼랜드 상에 서키트 필름(4) 외측으로 돌출되는 두께를 갖도록 형성되는 솔더페이스트(6)의 도포 두께(t)는, 회로기판(9) 상의 단자홈(10) 깊이(d)의 1.5배 이상이 되도록 한다.At this time, the coating thickness t of the solder paste 6 formed to have a thickness protruding to the outside of the circuit film 4 on the solder ball land of the circuit film 4 is a terminal groove (on the circuit board 9). 10) It should be at least 1.5 times the depth (d).
또한, 상기 서키트 필름(4)의 솔더볼랜드 상에 형성되는 솔더페이스트(6)와 회로기판(9)의 접속단자(11)는 실장시 열풍에 의해 용융 접합된다.In addition, the solder paste 6 formed on the solder ball land of the circuit film 4 and the connection terminal 11 of the circuit board 9 are melt-bonded by hot air during mounting.
이와 같이 구성된 본 발명의 작용을 패키지 제조 과정 및 실장 과정을 통해 설명하면 다음과 같다.Referring to the operation of the present invention configured as described through the package manufacturing process and mounting process as follows.
칩스케일 패키지 제조시에는, 먼저 칩(1)에 접착테이프(3)를 붙이고, 상기 접착테이프(3) 위로 서키트 필름(4)을 올린 뒤, 리드 본드 툴(도시는 생략함)을 이용하여 칩(1)의 본딩패드(2)와 서키트 필름(4)의 회로패턴이 전기적으로 연결되도록 리드 본딩을 실시한다.In manufacturing the chip scale package, first, the adhesive tape 3 is attached to the chip 1, the circuit film 4 is placed on the adhesive tape 3, and then the chip is bonded using a lead bond tool (not shown). Lead bonding is performed so that the bonding pad 2 of (1) and the circuit pattern of the circuit film 4 are electrically connected.
그 다음, 봉지제(7)로 리드(5) 및 칩(1) 측면을 봉지제(7)로 봉지하여 칩(1)의 회로형성면이 보호되도록 한다.Then, the lead 5 and the side of the chip 1 with the sealing agent 7 is sealed with the sealing agent 7 so that the circuit formation surface of the chip 1 is protected.
여기까지의 과정은 종래의 마이크로 비·지·에이 패키지 제조과정과 동일하며, 그 다음이 달라진다.The procedure up to this point is the same as that of the conventional micro B, G, and A package manufacturing process, and the following steps are different.
즉, 봉지후 패키지의 솔더볼랜드 상에는 솔더볼 대신 솔더페이스트(6)가 스크린 프린팅 방식에 의해 도포되어 패키지 제조가 완료된다.That is, after sealing, the solder paste 6 is applied to the solder ball land of the package by screen printing instead of the solder ball, thereby completing the manufacture of the package.
한편, 칩스케일 패키지의 제조 과정과는 별도로 회로기판(9)이 제작되는데, 상기 회로기판(9) 상에는 상기 칩스케일 패키지의 솔더페이스트(6)가 삽입되는 단자홈(10)이 형성되어 있고, 그 단자홈(10) 내에는 접속단자(11)가 위치하게 된다.Meanwhile, a circuit board 9 is manufactured separately from a manufacturing process of a chip scale package. A terminal groove 10 into which the solder paste 6 of the chip scale package is inserted is formed on the circuit board 9. The connecting terminal 11 is located in the terminal groove 10.
이 때, 상기 솔더페이스트(6)의 두께는 접속단자(11)와의 확실한 접속을 위해 단자홈(10) 깊이의 1.5배 이상이어야 함은 물론이다.At this time, the thickness of the solder paste 6 should be 1.5 times or more of the depth of the terminal groove 10 in order to ensure the connection with the connection terminal (11).
한편, 상기와 같이 제조된 칩스케일 패키지는, 칩스케일 패키지의 서키트 필름 저면에 형성된 솔더페이스트(6)가 회로기판(9)의 단자홈(10)내에 위치한 상태에서 열풍을 가해 함에 따라, 솔더페이스트(6)가 녹으면서 상기 단자홈(10) 내의 접속단자(11)에 접합되어 도 3에 도시된 바와 같은 형태로 실장이 이루어지게 된다.Meanwhile, in the chip scale package manufactured as described above, as the solder paste 6 formed on the bottom surface of the circuit film of the chip scale package is subjected to hot air while being placed in the terminal groove 10 of the circuit board 9, the solder paste is applied. 6 is melted and bonded to the connection terminal 11 in the terminal groove 10 so as to be mounted as shown in FIG. 3.
이상에서와 같이, 본 발명은 칩스케일 패키지의 단자 구조 및 회로기판의 단자 구조를 개선하여, 실장시의 작업성 및 솔더조인트에서의 접합 신뢰성이 향상되도록 한 것이다.As described above, the present invention improves the terminal structure of the chip scale package and the terminal structure of the circuit board, thereby improving the workability at the time of mounting and the bonding reliability in the solder joint.
즉, 본 발명은 회로기판의 단자홈으로 인해 칩스케일 패키지와 회로기판과의 얼라인이 용이하게 이루어지며, 솔더볼 부착공정 및 회로기판에의 솔더페이스트 도포과정이 없어, 칩스케일 패키지를 회로기판에 실장시 작업성이 향상되며, 이와 더불어 패키지의 실장 신뢰성이 향상된다.That is, the present invention facilitates alignment between the chip scale package and the circuit board due to the terminal groove of the circuit board, and there is no solder ball attaching process and no solder paste coating process on the circuit board, thereby providing the chip scale package to the circuit board. The workability is improved during mounting, and the package reliability of the package is also improved.
Claims (3)
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| KR1020000077107A KR20020046776A (en) | 2000-12-15 | 2000-12-15 | structure for mounting chip scale package on PCB |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| KR1020000077107A KR20020046776A (en) | 2000-12-15 | 2000-12-15 | structure for mounting chip scale package on PCB |
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| Publication Number | Publication Date |
|---|---|
| KR20020046776A true KR20020046776A (en) | 2002-06-21 |
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Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| KR1020000077107A KR20020046776A (en) | 2000-12-15 | 2000-12-15 | structure for mounting chip scale package on PCB |
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| Country | Link |
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| KR (1) | KR20020046776A (en) |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US7586182B2 (en) | 2004-11-26 | 2009-09-08 | Samsung Electronics Co., Ltd. | Packaged semiconductor die and manufacturing method thereof |
| CN109257872A (en) * | 2018-10-23 | 2019-01-22 | 广东晶科电子股份有限公司 | A kind of Mini LED module and preparation method thereof |
-
2000
- 2000-12-15 KR KR1020000077107A patent/KR20020046776A/en not_active Application Discontinuation
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US7586182B2 (en) | 2004-11-26 | 2009-09-08 | Samsung Electronics Co., Ltd. | Packaged semiconductor die and manufacturing method thereof |
| CN109257872A (en) * | 2018-10-23 | 2019-01-22 | 广东晶科电子股份有限公司 | A kind of Mini LED module and preparation method thereof |
| CN109257872B (en) * | 2018-10-23 | 2024-03-26 | 广东晶科电子股份有限公司 | Mini LED module and manufacturing method thereof |
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