KR20020046682A - method for forming contact metal line semiconductor device - Google Patents
method for forming contact metal line semiconductor device Download PDFInfo
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- KR20020046682A KR20020046682A KR1020000076990A KR20000076990A KR20020046682A KR 20020046682 A KR20020046682 A KR 20020046682A KR 1020000076990 A KR1020000076990 A KR 1020000076990A KR 20000076990 A KR20000076990 A KR 20000076990A KR 20020046682 A KR20020046682 A KR 20020046682A
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- 239000004065 semiconductor Substances 0.000 title claims abstract description 49
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- 239000005380 borophosphosilicate glass Substances 0.000 claims description 2
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- 229910052814 silicon oxide Inorganic materials 0.000 claims description 2
- 239000011800 void material Substances 0.000 abstract description 9
- 239000005368 silicate glass Substances 0.000 abstract description 2
- 238000009413 insulation Methods 0.000 abstract 5
- 238000005530 etching Methods 0.000 description 8
- 239000010410 layer Substances 0.000 description 8
- 150000002500 ions Chemical class 0.000 description 4
- 238000000151 deposition Methods 0.000 description 3
- 230000010354 integration Effects 0.000 description 3
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 3
- 229920005591 polysilicon Polymers 0.000 description 3
- 238000007796 conventional method Methods 0.000 description 2
- 230000000694 effects Effects 0.000 description 2
- 238000011160 research Methods 0.000 description 2
- ATJFFYVFTNAWJD-UHFFFAOYSA-N Tin Chemical compound [Sn] ATJFFYVFTNAWJD-UHFFFAOYSA-N 0.000 description 1
- 230000015572 biosynthetic process Effects 0.000 description 1
- 230000015556 catabolic process Effects 0.000 description 1
- 239000004020 conductor Substances 0.000 description 1
- 230000007423 decrease Effects 0.000 description 1
- 238000006731 degradation reaction Methods 0.000 description 1
- 238000011161 development Methods 0.000 description 1
- 230000018109 developmental process Effects 0.000 description 1
- 239000011521 glass Substances 0.000 description 1
- 239000011229 interlayer Substances 0.000 description 1
- 238000004519 manufacturing process Methods 0.000 description 1
- 230000008054 signal transmission Effects 0.000 description 1
- 125000006850 spacer group Chemical group 0.000 description 1
- 239000000126 substance Substances 0.000 description 1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76897—Formation of self-aligned vias or contact plugs, i.e. involving a lithographically uncritical step
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3105—After-treatment
- H01L21/311—Etching the insulating layers by chemical or physical means
- H01L21/31105—Etching inorganic layers
- H01L21/31111—Etching inorganic layers by chemical means
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
- H01L21/76802—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
- H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
- H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
- H01L21/8232—Field-effect technology
- H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
- H01L21/823475—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type interconnection or wiring or contact manufacturing related aspects
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- Insulated Gate Type Field-Effect Transistor (AREA)
Abstract
Description
본 발명은 반도체 소자의 제조방법에 관한 것으로, 특히 셀프 얼라인 콘택(self align contact)을 형성하는데 적당한 반도체 소자의 콘택 배선 형성방법에 관한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a semiconductor device, and more particularly, to a method for forming contact wiring of a semiconductor device suitable for forming a self align contact.
반도체 집적회로에 있어서 좋은 회로동작 성능과 높은 집적도를 얻기 위하여 집적회로를 구성하는 MOS FET의 크기를 줄이기 위한 노력의 결과로 반도체 집적회로의 기술이 마이크론 이하로 스케일다운(Scale Down)되었다.As a result of efforts to reduce the size of the MOS FET constituting the integrated circuit in order to obtain good circuit operation performance and high integration in the semiconductor integrated circuit, the technology of the semiconductor integrated circuit has been scaled down to less than micron.
따라서 MOS FET에 있어서는 게이트 라인의 폭이 좁게(Narrow) 되었으며, CMOS FET에 있어서는 집적화가 거듭되면서 단일 소자의 크기가 줄어듦에 따른 MOS FET의 특성 중 숏 채널 효과(short channel effect)에 의한 핫 캐리어(hot carrier)의 문제를 해결하기 위해 LDD(Lightly Doped Drain) 구조를 MOS FET에 적용하여 그와 같은 문제를 개선하고, 집적도 증가에 따른 배선저항의 증가로 발생하는 신호전달속도 저하의 문제를 해결하기 위하여 폴리 사이드를 이용한 게이트 구조를 채용하는 등으로 다각적으로 연구 및 개발되고 있다.Therefore, in the MOS FET, the gate line width is narrowed, and in the CMOS FET, the hot carrier due to the short channel effect is one of the characteristics of the MOS FET as the size of a single device decreases as integration is repeated. In order to solve the problem of hot carrier, the LDD (Lightly Doped Drain) structure is applied to the MOS FET to solve such problems, and to solve the problem of signal transmission speed degradation caused by the increase in wiring resistance due to the increase in integration. For this purpose, various researches and developments have been made by employing a gate structure using polysides.
이밖에도, 게이트 전극의 양측면 반도체 기판에 소오스/드레인으로 사용할 불순물 영역을 형성한 이후 진행되는 배선공정은 상기 게이트 전극을 포함한 기판 전면에 평탄화 공정을 포함하는 ILD(Inter Layer Dielectric)공정 후에 소오스/드레인 영역의 상측에 형성된 ILD층을 선택적으로 제거하여 콘택홀을 형성한 다음 진행되는데, 이와 같은 콘택 배선 공정 또한 반도체 소자의 미세화로 인해 그 종횡비(aspect ratio)가 증가하여 비트 라인이나 메모리 콘택부의 마진 확보에 어려움이 있어 이를 해결하기 위한 연구가 활발히 진행되고 있다.In addition, after the impurity regions to be used as the source / drain regions are formed on both side semiconductor substrates of the gate electrode, the wiring process is performed after the ILD (Inter Layer Dielectric) process including a planarization process on the entire surface of the substrate including the gate electrode. A contact hole is formed by selectively removing the ILD layer formed on the upper side of the gate, and the contact wiring process also increases the aspect ratio due to the miniaturization of the semiconductor device, thereby securing the margin of the bit line or the memory contact portion. There is a difficulty, and research to solve this problem is being actively conducted.
한편, 반도체 소자의 콘택 배선 형성 공정 중 게이트 전도체와의 오버랩 마진(overlap margin)을 증대시키기 위해 SOSCON(Sidewall Oxide Spacer CONtact hole) 공정을 진행하고 있다.Meanwhile, a SOSCON (Sidewall Oxide Spacer CONtact hole) process is being performed to increase an overlap margin with a gate conductor during the process of forming a contact wiring of a semiconductor device.
이하, 첨부된 도면을 참고하여 종래의 반도체 소자의 콘택 배선 형성방법을 설명하면 다음과 같다.Hereinafter, a method for forming contact wires of a conventional semiconductor device will be described with reference to the accompanying drawings.
도 1a 내지 도 1d는 종래의 반도체 소자의 콘택 배선 형성방법을 나타낸 공정단면도이다.1A to 1D are cross-sectional views illustrating a conventional method for forming contact wirings in a semiconductor device.
도 1a에 도시한 바와 같이, 필드 영역과 활성 영역으로 정의된 반도체 기판(11)의 필드 영역에 필드 산화막(12)을 형성하고, 전면에 산화막과 폴리 실리콘을 증착한 후 게이트 형성 마스크로 패터닝하여 게이트 산화막(13)과 게이트 전극(14)을 적층하여 형성한다.As shown in FIG. 1A, a field oxide film 12 is formed in a field region of a semiconductor substrate 11 defined as a field region and an active region, an oxide layer and polysilicon are deposited on the entire surface, and then patterned by a gate forming mask. The gate oxide film 13 and the gate electrode 14 are laminated to form.
이어, 상기 게이트 전극(14)을 마스크로 이용하여 상기 반도체 기판(11)에 저농도 n형 소오스/드레인 이온을 주입하여 LDD(Lightly Doped Drain) 영역(15)을 형성한다.Subsequently, a lightly doped drain (LDD) region 15 is formed by implanting low concentration n-type source / drain ions into the semiconductor substrate 11 using the gate electrode 14 as a mask.
그리고 상기 게이트 전극(14)을 포함한 반도체 기판(11)의 전면에 절연막을 형성한 후 이방성 식각하여 상기 게이트 전극(14)의 양측면에 측벽 절연막(16)을 형성한다.An insulating film is formed on the entire surface of the semiconductor substrate 11 including the gate electrode 14, and then anisotropically etched to form sidewall insulating films 16 on both sides of the gate electrode 14.
이어, 상기 측벽 절연막(16)과 게이트 전극(14)을 마스크로 이용하여 반도체 기판(11)에 고농도 n형 소오스/드레인 이온을 주입하여 상기 LDD 영역(15)과 연결되는 소오스/드레인 불순물 영역(17)을 형성한다.Subsequently, a high concentration of n-type source / drain ions are implanted into the semiconductor substrate 11 using the sidewall insulating layer 16 and the gate electrode 14 as masks, so that source / drain impurity regions connected to the LDD region 15 ( 17).
도 1b에 도시한 바와 같이, 상기 게이트 전극(14)을 포함한 반도체 기판(11)의 전면에 제 1 절연막(18)을 형성하고, 포토 및 식각공정을 통해 상기 게이트 전극(14) 사이의 소오스/드레인 불순물 영역(17)이 노출되도록 콘택홀(19)을 형성한다.As shown in FIG. 1B, a first insulating film 18 is formed on the entire surface of the semiconductor substrate 11 including the gate electrode 14, and a source / gate between the gate electrodes 14 is formed through photo and etching processes. The contact hole 19 is formed to expose the drain impurity region 17.
도 1c에 도시한 바와 같이, 상기 콘택홀(19)을 포함한 반도체 기판(11)의 전면에 제 2 절연막을 형성한 후, 전면에 에치백 공정을 실시하여 상기 콘택홀(19)의 양측면에 제 2 절연막 측벽(20)을 형성한다.As shown in FIG. 1C, after the second insulating film is formed on the entire surface of the semiconductor substrate 11 including the contact hole 19, an etch back process is performed on the entire surface of the semiconductor substrate 11. 2 insulating film sidewall 20 is formed.
도 1d에 도시한 바와 같이, 상기 콘택홀(19)을 포함한 반도체 기판(11)의 전면에 플러그(plug)용 제 1 금속막을 증착한 후, 에치백 또는 CMP 공정을 통해 상기 콘택홀(19)의 내부에 금속 플러그(21)를 형성한다.As illustrated in FIG. 1D, after depositing a first metal film for plug on the front surface of the semiconductor substrate 11 including the contact hole 19, the contact hole 19 may be subjected to an etch back or CMP process. The metal plug 21 is formed in the interior thereof.
이어, 상기 금속 플러그(21)를 포함한 반도체 기판(11)의 전면에 금속 배선용 제 2 금속막을 증착한 후, 포토 및 식각공정을 통해 제 2 금속막을 선택적으로 제거하여 금속 플러그(21) 및 그에 인접한 제 1 절연막(18)상에 금속 배선(22)을 형성한다.Subsequently, after depositing the second metal film for metal wiring on the front surface of the semiconductor substrate 11 including the metal plug 21, the second metal film is selectively removed through a photo and etching process to thereby remove the metal plug 21 and adjacent thereto. The metal wiring 22 is formed on the first insulating film 18.
그러나 상기와 같은 종래의 반도체 소자의 콘택 배선 형성방법에 있어서 다음과 같은 문제점이 있었다.However, the above-described conventional method for forming a contact wiring of a semiconductor device has the following problems.
즉, 콘택홀을 형성한 후에 콘택홀의 양측면에 절연막 측벽을 형성할 때 2번 식각 공정으로 오버 에치(over etch)가 발생하여 기판의 손상(damage)(접합 깊이 감소)으로 인한 과다한 누설 전류를 유발한다.That is, when forming the insulating film sidewalls on both sides of the contact hole after forming the contact hole, an over-etch occurs by the etching process 2, causing excessive leakage current due to damage of the substrate (reduction of the bonding depth). do.
본 발명은 상기와 같은 종래의 문제점을 해결하기 위해 안출한 것으로 콘택홀 형성시 오버 에치에 의한 기판의 손상(damage)을 방지하여 누설 전류의 유발을 줄이도록 한 반도체 소자의 콘택 배선 형성방법을 제공하는데 그 목적이 있다.SUMMARY OF THE INVENTION The present invention has been made to solve the above-mentioned problems and provides a method for forming contact wirings in a semiconductor device to reduce the occurrence of leakage current by preventing damage to the substrate due to over-etching when forming contact holes. Its purpose is to.
도 1a 내지 도 1d는 종래의 반도체 소자의 콘택 배선 형성방법을 나타낸 공정단면도1A to 1D are cross-sectional views illustrating a method of forming contact wirings in a conventional semiconductor device.
도 2a 내지 도 2e는 본 발명에 의한 반도체 소자의 콘택 배선 형성방법을 나타낸 공정단면도2A through 2E are cross-sectional views illustrating a method of forming contact wirings in a semiconductor device according to the present invention.
도면의 주요 부분에 대한 부호의 설명Explanation of symbols for the main parts of the drawings
31 : 반도체 기판 32 : 필드 산화막31 semiconductor substrate 32 field oxide film
33 : 게이트 절연막 34 : 게이트 전극33 gate insulating film 34 gate electrode
35 : LDD 영역 36 : 측벽 절연막35 LDD region 36 sidewall insulating film
37 : 소오스/드레인 불순물 영역 38 : USG막37 source / drain impurity region 38 USG film
39 : 보이드 40 : 제 1 절연막39: void 40: first insulating film
41 : 제 2 절연막 42 : 콘택홀41 second insulating film 42 contact hole
43 : 금속 플러그 44 : 금속 배선43: metal plug 44: metal wiring
상기와 같은 목적을 달성하기 위한 본 발명에 의한 반도체 소자의 콘택 배선 형성방법은 반도체 기판상에 게이트 절연막을 개재하여 게이트 전극을 형성하는 단계와, 상기 게이트 전극 양측면에 측벽 절연막을 형성하는 단계와, 상기 게이트 전극 양측의 반도체 기판 표면내에 소오스/드레인 불순물 영역을 형성하는 단계와, 상기 게이트 전극을 포함한 반도체 기판의 전면에 보이드 발생이 용이한 USG막을 형성하는 단계와, 상기 보이드의 개구부가 오픈되도록 상기 USG막을 선택적으로 폴리싱하는 단계와, 상기 보이드를 포함한 반도체 기판의 전면에 제 1, 제 2 절연막을 차례로 형성하는 단계와, 상기 보이드가 형성된 소오스/드레인 불순물 영역이 노출되도록 상기 제 2, 제 1 절연막을 선택적으로 제거하여 콘택홀을 형성하는 단계와, 상기 콘택홀의 내부에 금속 플러그를 형성하는 단계와, 상기 금속 플러그 및 그에 인접한 제 2 절연막상에 금속 배선을 형성하는 단계를 포함하여 형성함을 특징으로 한다.The contact wiring forming method of the semiconductor device according to the present invention for achieving the above object comprises the steps of forming a gate electrode on the semiconductor substrate via a gate insulating film, forming a sidewall insulating film on both sides of the gate electrode; Forming a source / drain impurity region on a surface of the semiconductor substrate at both sides of the gate electrode, forming a USG film that easily generates voids on the entire surface of the semiconductor substrate including the gate electrode, and opening the opening of the void Selectively polishing a USG film, sequentially forming first and second insulating films on the entire surface of the semiconductor substrate including the voids, and exposing the second and first insulating films to expose source / drain impurity regions in which the voids are formed. Selectively removing the contact hole to form a contact hole; Forming a metal plug in, including the step of forming the metal wiring on the metal plug and the second insulating layer adjacent thereto, characterized in that formation.
이하, 첨부된 도면을 참고하여 본 발명에 의한 반도체 소자의 콘택 배선 형성방법을 상세히 설명하면 다음과 같다.Hereinafter, a method for forming contact wirings of a semiconductor device according to the present invention will be described in detail with reference to the accompanying drawings.
도 2a 내지 도 2e는 본 발명에 의한 반도체 소자의 콘택 배선 형성방법을 나타낸 공정단면도이다.2A through 2E are cross-sectional views illustrating a method of forming contact wirings in a semiconductor device according to the present invention.
도 2a에 도시한 바와 같이, 필드 영역과 활성 영역으로 정의된 반도체 기판(31)의 필드 영역에 필드 산화막(32)을 형성하고, 전면에 산화막과 폴리 실리콘을 증착한 후 게이트 형성 마스크로 패터닝하여 게이트 산화막(33)과 게이트 전극(34)을 적층하여 형성한다.As shown in FIG. 2A, a field oxide film 32 is formed in a field region of a semiconductor substrate 31 defined as a field region and an active region, an oxide layer and polysilicon are deposited on the entire surface, and then patterned by a gate forming mask. The gate oxide film 33 and the gate electrode 34 are laminated.
이어, 상기 게이트 전극(34)을 마스크로 이용하여 상기 반도체 기판(31)에 저농도 n형 소오스/드레인 이온을 주입하여 LDD(Lightly Doped Drain) 영역(35)을 형성한다.Subsequently, a lightly doped drain (LDD) region 35 is formed by implanting low concentration n-type source / drain ions into the semiconductor substrate 31 using the gate electrode 34 as a mask.
그리고 상기 게이트 전극(34)을 포함한 반도체 기판(31)의 전면에 절연막을 형성한 후 이방성 식각하여 상기 게이트 전극(34)의 양측면에 측벽 절연막(36)을 형성한다.An insulating film is formed on the entire surface of the semiconductor substrate 31 including the gate electrode 34, and then anisotropically etched to form sidewall insulating films 36 on both sides of the gate electrode 34.
이어, 상기 측벽 절연막(36)과 게이트 전극(34)을 마스크로 이용하여 반도체 기판(31)에 고농도 n형 소오스/드레인 이온을 주입하여 상기 LDD 영역(35)과 연결되는 소오스/드레인 불순물 영역(37)을 형성한다.Subsequently, a high concentration of n-type source / drain ions are implanted into the semiconductor substrate 31 using the sidewall insulating layer 36 and the gate electrode 34 as a mask to form a source / drain impurity region connected to the LDD region 35. 37).
도 2b에 도시한 바와 같이, 상기 게이트 전극(34)을 포함한 반도체 기판(31)의 전면에 보이드(void) 발생이 용이한 USG(Undoped Silicate Glass)막(38)을 증착한다.As shown in FIG. 2B, an undoped silicate glass (USG) film 38 which easily generates voids is deposited on the entire surface of the semiconductor substrate 31 including the gate electrode 34.
여기서 상기 USG막(38)을 증착할 때 상기 게이트 전극(34) 사이에는 단차에 의해 보이드(39)가 발생한다.Here, when the USG film 38 is deposited, a void 39 is generated between the gate electrodes 34 due to a step.
한편, 상기 USG막(38)은 3000 ~ 10000Å 두께로 형성한다.On the other hand, the USG film 38 is formed to a thickness of 3000 ~ 10000Å.
도 2c에 도시한 바와 같이, 상기 보이드(39)의 개구부가 오픈(open)되도록상기 USG막(38)의 전면에 CMP(Chemical Mechanical Polishing) 공정을 이용하여 상기 USG막(38)을 선택적으로 폴리싱한다.As shown in FIG. 2C, the USG film 38 is selectively polished by using a chemical mechanical polishing (CMP) process on the entire surface of the USG film 38 so that the opening of the void 39 is open. do.
도 2d에 도시한 바와 같이, 상기 개구부가 오픈된 보이드(39)를 포함한 반도체 기판(31)의 전면에 에치스톱(etch stop)용 제 1 절연막(40)과 유동성이 용이한 제 2 절연막(41)을 차례로 형성한다.As shown in FIG. 2D, the first insulating film 40 for etch stop and the second insulating film 41 for easy fluidity are formed on the entire surface of the semiconductor substrate 31 including the voids 39 having the openings opened. ) In turn.
여기서 상기 제 1 절연막(40)은 SiON, SiN, PE-질화막, Al2O3등의 비전도성 재료를 500 ~ 3000Å 두께로 형성하고, 상기 제 2 절연막(41)은 HDP(High Density Plasma) 산화막, SOG(Spin On Glass), BPSG 등의 절연막을 3000 ~ 10000Å 두께로 형성한다.Here, the first insulating film 40 is formed of a non-conductive material such as SiON, SiN, PE-nitride film, Al 2 O 3 to a thickness of 500 ~ 3000Å, the second insulating film 41 is HDP (High Density Plasma) oxide film , Insulating film such as SOG (Spin On Glass), BPSG, etc. to form a thickness of 3000 ~ 10000Å.
이어, 포토 및 식각 공정을 통해 상기 보이드(39)가 형성된 소오스/드레인 불순물 영역(37)의 표면이 노출되도록 상기 제 2 절연막(41) 및 제 1 절연막(40)을 선택적으로 제거하여 콘택홀(42)을 형성한다.Subsequently, the second insulating layer 41 and the first insulating layer 40 may be selectively removed to expose the surface of the source / drain impurity region 37 in which the void 39 is formed through photo and etching processes. 42).
도 2e에 도시한 바와 같이, 상기 콘택홀(42)을 포함한 반도체 기판(31)의 전면에 플러그(plug)용 제 1 금속막을 증착한 후, 에치백 또는 CMP 공정을 통해 상기 콘택홀(42)의 내부에 금속 플러그(43)를 형성한다.As shown in FIG. 2E, a first metal film for plug is deposited on the entire surface of the semiconductor substrate 31 including the contact hole 42, and then the contact hole 42 is formed through an etch back or a CMP process. The metal plug 43 is formed inside.
이어, 상기 금속 플러그(43)를 포함한 반도체 기판(31)의 전면에 금속 배선용 제 2 금속막을 증착한 후, 포토 및 식각공정을 통해 제 2 금속막을 선택적으로 제거하여 금속 플러그(43) 및 그에 인접한 제 2 절연막(41)상에 금속 배선(44)을 형성한다.Subsequently, after depositing the second metal film for metal wiring on the front surface of the semiconductor substrate 31 including the metal plug 43, the second metal film is selectively removed through a photo and etching process to thereby remove the metal plug 43 and the adjacent metal plug 43. Metal wires 44 are formed on the second insulating film 41.
여기서 상기 금속 배선(44)은 W, 폴리 실리콘, TiN 등을 사용할 수 있다.Here, the metal wire 44 may use W, polysilicon, TiN, or the like.
이상에서 설명한 바와 같이 본 발명에 의한 반도체 소자의 콘택 배선 형성방법은 다음과 같은 효과가 있다.As described above, the method for forming a contact wiring of a semiconductor device according to the present invention has the following effects.
즉, 한 번의 식각공정을 통해 콘택홀을 형성함으로서 과도한 오버 에치에 의한 기판의 손상을 방지할 수 있으므로 누설 전류의 발생을 방지하여 소자의 전기적 특성을 개선할 수 있다.That is, by forming the contact hole through one etching process, damage to the substrate due to excessive over-etching can be prevented, thereby preventing the occurrence of leakage current, thereby improving the electrical characteristics of the device.
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