KR100223809B1 - Method of manufacturing transistor of semiconductor device - Google Patents

Abstract

The present invention relates to a method of manufacturing a transistor of a semiconductor device, and more particularly, to a method of manufacturing a transistor of a semiconductor device suitable for improving operating characteristics and manufacturing processes. As described above, the method of manufacturing a transistor of the semiconductor device according to the present invention includes forming an isolation layer using trenches having a predetermined interval on a semiconductor substrate defined by a memory cell unit and a logic unit, and a conductive layer for a first gate insulating layer and a first gate electrode on the entire surface of the semiconductor substrate. And forming a first cap insulating layer, selectively removing the first cap insulating layer, the conductive layer for the first gate electrode, and the first gate insulating layer to form first gate electrodes in the memory cell portion, and forming a first gate electrode in the logic portion. Leaving a conductive layer pattern for a gate electrode, forming a first impurity region in the semiconductor substrate below both sides of the first gate electrodes, forming an interlayer insulating film on the entire surface of the substrate including the first gate electrodes; Selectively removing the interlayer insulating layer between the first gate electrodes of the memory cell unit. Forming a contact hole, forming a capacitor first electrode on the interlayer insulating film adjacent to the node contact hole and the node contact hole, forming a dielectric film on an entire surface of the substrate including the capacitor first electrode, and in the logic unit Removing the formed dielectric film, the interlayer insulating film, the first cap insulating film, and the conductive layer pattern for the first gate electrode, and forming the second gate insulating film, the conductive layer for the second gate electrode, and the second cap insulating film in the logic part. And selectively removing the second cap insulation layer, the conductive layer for the second gate electrode, and the second gate insulation layer to form a second gate electrode on the logic unit, and a capacitor second electrode on the dielectric layer of the memory cell unit. And forming a second impurity region in the semiconductor substrate under the side of the second gate electrode.

Description

Method of manufacturing transistor of semiconductor device

The present invention relates to a method of manufacturing a transistor of a semiconductor device, and more particularly, to a method of manufacturing a transistor of a semiconductor device suitable for improving operating characteristics and manufacturing processes.

In accordance with the trend of integration of semiconductor devices, the area of contact between the wirings and the area of electrical wirings such as gate electrodes or conducting lines of semiconductor devices is reduced, and the junction depth X _j , which is a diffusion layer, is not formed thinly to reduce lateral diffusion. You must.

As a result, the wiring resistance increases and the sheet resistance and the contact resistance of the diffusion layer increase, thereby delaying the transmission time of the electrical signal.

In addition, the signal transmission speed of the entire circuit is reduced by the inductive coupling between the chip and the chip.

Accordingly, in order to prevent the time delay phenomenon described above, a technique of integrating circuits having different functions into one chip has emerged.

This implements a logic circuit having high speed and a memory cell unit having high integration in one chip, and typically includes at least one of a ROM, a flash memory, a ferroelectric memory DRAM, and the like.

Furthermore, in addition to these functions, it has been developed into a system-on-a-chip that includes RF circuits for transmitting and receiving, current amplification for improving the high speed of input and output, and analog circuits for switches, and especially for low voltage portable personal communication devices. It is expected to play a leading role in the commercialization of high speed and multifunction.

The most active research is the embedded DRAM which can minimize the power, increase the speed and improve the function by integrating the high speed logic circuit and the highly integrated DRAM circuit in one chip.

Specifically, there are two processes to realize the technology of the embedded DRAM as described above.

One is to use the high speed of the logic circuit unit mainly on the DRAM process, and the other is a method of integrating the DRAM mainly on the logic process.

The system-on-a-chip process developed as the next step of the above-described process aims to reduce as much as possible the sacrifice of high integration of the DRAM and high speed of logic.

Specifically, the DRAM unit uses a DRAM cell having a 0.25 µm rule to realize high integration of a general-purpose DRAM level. The logic section uses a logic LSI transistor having a 0.25 µm rule. However, since the high temperature heat treatment is required to form the memory cell, the length of the gate electrode needs to be somewhat longer, and the performance will be 80 to 90% of the same design rule.

The improved system-on-a-chip process is an ideal method that does not sacrifice the high-density of the DRAM and the high-speed logic. At first, the one-chip process is developed for the 0.18㎛ rule. We develop each process of logic.

The problem with this development sequence is that there is a possibility that the process steps will increase when developing to DRAM process. For example, two types of gate insulating films will be formed. Such a problem is changed by applying a voltage to a memory cell. It can be solved by realizing it.

Under the one-chip DRAM and logic LSI, new flow technology and device technology are required which are completely different from each other so as not to sacrifice performance and price. Such a technology firstly determines the thickness of the gate oxide layer of the DRAM part. As such, a technology that does not deteriorate in performance, and secondly, a technology for lowering the heat treatment temperature, or a device technology and device technology that does not degrade the transistor performance even after a high temperature heat treatment is required. High density plasma technology and device technology are needed to solve the aspect ratio problem caused by the step difference problem.

In general, when the stack cell is used, all three techniques are required, and when the trench structure is used, only the problem of the gate oxide layer remains. However, most LSI makers use stack capacitor cells in their one-chip process, so all three problems must be addressed.

Hereinafter, a transistor manufacturing method of a conventional semiconductor device will be described with reference to the accompanying drawings.

1A to 1H are cross-sectional views of a transistor manufacturing process of a conventional semiconductor device. In this case, the transistor of the conventional semiconductor device as shown in FIGS. 1A to 1H is a cross-sectional view of a transistor manufacturing process of a semiconductor device having a gate oxide film having the same thickness as a memory cell part and a logic part of a transistor manufacturing method for forming an embedded DRAM device. Since the transistor forming process of the memory cell portion is performed at the same time, only the transistor manufacturing process for the logic portion is shown.

First, as shown in FIG. 1A, the field oxide film 2 is formed on the semiconductor substrate 1 at a predetermined interval using a normal process. Subsequently, a gate oxide film 3 is formed on the semiconductor substrate 1 except for the field oxide film 2.

As shown in FIG. 1B, a polysilicon layer 4 is formed on the entire surface of the substrate including the gate oxide film 3.

As shown in FIG. 1C, a cap oxide film 5 is formed on the polysilicon layer 4.

As shown in FIG. 1D, the cap oxide film 5, the polysilicon layer 4 and the gate oxide film 3 are selectively patterned (photolithography process + etching process) to form a gate electrode 4a having a predetermined interval. .

As shown in FIG. 1E, a low concentration impurity region is formed by injecting low concentration impurity ions into the semiconductor substrate 1 under both sides of the gate electrode 4a by an ion implantation process using the gate electrode 4a as a mask. Drain) region 6 is formed.

As shown in FIG. 1F, an oxide film is formed on the entire surface of the substrate including the gate electrode 4a and then etched back to form sidewall spacers 7 on the side surfaces of the cap insulating film 5 and the gate electrode 4a. Subsequently, an ion implantation process using the gate electrode 4a and the sidewall spacers 7 as a mask forms a highly-concentrated impurity region 8 as a source / drain region in the semiconductor substrate 1 under both sidewalls of the sidewall spacers 7. do.

As shown in FIG. 1G, after forming the interlayer oxide film 9 on the entire surface of the substrate, a contact hole 10 is formed by selectively removing the interlayer oxide film 9 above the high concentration impurity region 8. An aluminum layer 11 is formed on the entire surface of the interlayer oxide film 9 including the holes 10.

The conventional method of manufacturing a transistor of a semiconductor device has the following problems.

First, when the high temperature heat treatment for the formation of the capacitor and the high temperature heat treatment such as the reflow of the interlayer oxide layer after the transistor forming process for the logic unit is completed, the impurity profile that determines the characteristics of the transistor is diffused during the high temperature heat treatment. Since the junction depth of the source / drain region having a high impurity concentration is deepened, the punchthrough may occur. In addition, the high-temperature heat treatment shortens the effective channel length of the low concentration impurity region, and lowers the surface concentration in the channel region, thereby lowering the threshold voltage.

Second, when forming the gate electrode of the transistor, the design rule adopts silicide starting from 0.35 μm. When the silicide is heat-treated at 750 ° C. for 10 minutes or more, aggregation occurs and the resistance of the gate electrode is increased.

The present invention has been made to solve the problems of the conventional method of manufacturing a transistor of a semiconductor device as described above to improve the operation characteristics by using a process of forming an isolation layer using a trench, and a method of forming a transistor later in the logic unit To provide a method for manufacturing a transistor of a semiconductor device with improved manufacturing process,

1A to 1G are cross-sectional views of a transistor manufacturing process of a conventional semiconductor device.

2A to 2K are cross-sectional views of a transistor manufacturing process of the semiconductor device according to the first embodiment of the present invention.

3A to 3J are cross-sectional views of a transistor manufacturing process of a semiconductor device according to a second exemplary embodiment of the present invention.

4A to 4J are cross-sectional views of a transistor manufacturing process of a semiconductor device according to a third exemplary embodiment of the present invention.

Explanation of symbols for main parts of the drawings

21 semiconductor substrate 22 first insulating film

23: trench 24: separator

25: first gate insulating film 26a: first gate electrode

26b: conductive layer pattern for gate electrode 27: first cap insulating film

28; First Impurity Region 29: First Sidewall Spacer

30 second insulating film 31 node contact hole

32 capacitor first electrode 33 dielectric film

34: second gate insulating film 35a: second gate electrode

35b: Capacitor second electrode 36: Second cap insulating film

37: second sidewall spacer 38: second impurity region

39: third insulating film 40: contact hole

41: conductive layer pattern

According to the present invention, a method of manufacturing a transistor of a semiconductor device includes forming an isolation layer using trenches having a predetermined interval on a semiconductor substrate defined by a memory cell unit and a logic unit, and a conductive layer for a first gate insulating layer and a first gate electrode on the entire surface of the semiconductor substrate. And forming a first cap insulating layer, selectively removing the first cap insulating layer, the conductive layer for the first gate electrode, and the first gate insulating layer to form first gate electrodes in the memory cell portion, and forming a first gate electrode in the logic portion. Leaving a conductive layer pattern for a gate electrode, forming a first impurity region in the semiconductor substrate below both sides of the first gate electrodes, forming an interlayer insulating film on the entire surface of the substrate including the first gate electrodes; Selectively removing the interlayer insulating layer between the first gate electrodes of the memory cell unit Forming a tack hole; forming a capacitor first electrode on the node contact hole and an interlayer insulating film adjacent to the node contact hole; forming a dielectric film on the entire surface of the substrate including the capacitor first electrode; Removing a dielectric film, an interlayer insulating film, a first cap insulating film, and a conductive layer pattern for a first gate electrode, forming a second gate insulating film, a conductive layer for a second gate electrode, and a second cap insulating film in the logic portion; Selectively removing the second cap insulation layer, the conductive layer for the second gate electrode, and the second gate insulation layer to form a second gate electrode in the logic unit, and to form a capacitor second electrode on the dielectric layer of the memory cell unit. And forming a second impurity region in the semiconductor substrate under the side of the second gate electrode.

Such a transistor manufacturing method of the semiconductor device of the present invention will be described with reference to the accompanying drawings.

2A to 2K are cross-sectional views of a transistor manufacturing process of the semiconductor device according to the first embodiment of the present invention.

First, as shown in FIG. 2A, the first insulating film 22 is formed to a thickness of 1000 to 10000 상 에 on the semiconductor substrate 21 defined by the memory cell portion A and the logic portion B. FIG.

As shown in FIG. 2B, after defining the isolation region, the first insulating layer 22 is selectively patterned (photolithography process + etching process) to expose the upper surface of the semiconductor substrate 21 in the isolation region. Subsequently, a trench 23 having a predetermined interval is formed by etching the semiconductor substrate 21 by a predetermined depth by an etching process using the patterned first insulating layer 22 as a mask.

As shown in FIG. 2C, an isolation layer 24 is formed in the trench 23 to define an isolation region and an active region. In other words, by forming an isolation film using a trench, a shallow trench isolation (STI) is formed using a conventional method. At this time, the first insulating film 22 on the semiconductor substrate 21 is also removed.

As shown in FIG. 2D, the first gate insulating layer 25, the first gate electrode conductive layer 26, and the first cap insulating layer 27 are sequentially formed on the entire surface of the semiconductor substrate 21 including the isolation layer 24. do. In this case, the first gate insulating film 25 is formed by removing the first insulating film 22 and then heat treating the entire surface of the substrate, or using a dielectric film such as a silicon oxide film or the like to have a thickness of 500 kW or less. The first gate electrode conductive layer 26 is formed of polysilicon or sputtered a metal material having a relatively high melting point and low resistivity (resistance) such as tungsten (W), tantalum (Ta), or copper (Cu). It is formed to a thickness of 1000 ~ 5000Å by using a CVD method or the like.

As shown in FIG. 2E, the memory cell portion may be selectively patterned (photolithography process + etching process) of the first cap insulation layer 27, the first gate electrode conductive layer 26, and the first gate insulation layer 25. In (A), the first gate electrode 26a having a predetermined interval is formed, and in the logic portion B, the conductive layer pattern 26b for the gate electrode is formed to mask the active region. At this time, the reason why the conductive layer pattern 26b for the gate electrode is left is advantageous in the planarization process. Subsequently, an impurity ion implantation process using the first gate electrode 26a and the conductive layer pattern 26b for the gate electrode as a mask is performed on both side semiconductor substrates 21 of the first gate electrode 26a of the memory cell portion A. ), A first impurity region 28 to be used as a source / drain is formed.

As shown in FIG. 2F, a first sidewall spacer 29 is formed on the side surfaces of the first cap insulating film 27 and the first gate electrode 26a by using an insulating film. Next, a second insulating film 30 is formed on the entire surface of the substrate including the first gate electrode 26a. Subsequently, the node contact hole 31 is formed by selectively removing the second insulating layer 30 on one side of the first gate electrode 26a formed in the memory cell unit A. Referring to FIG. Next, after the capacitor first electrode 32 is formed on the entire surface of the second insulating layer 30 including the node contact hole 31, the second insulating layer 30 adjacent to the node contact hole 31 and the node contact hole 31 is formed. The capacitor first electrode 32 is patterned so that only the phase remains. In this case, the capacitor first electrode 32 may be formed of a doped polysilicon layer, or may be formed of a silicide laminated film such as WSi ₂ and a polysilicon layer, or a barrier metal layer such as Ti / TiN and a tungsten or aluminum layer. It is formed by applying a laminated film with a metal layer, and may be utilized as a bit line or a metal wiring in the memory cell portion in addition to the capacitor first electrode 32 as described above.

As shown in FIG. 2G, the dielectric film 33 is formed on the entire surface of the second insulating film 30 including the capacitor first electrode 32. At this time, the dielectric film 33 is formed to a thickness of 50 ~ 1000Å using an insulating film containing nitride (nitride).

As shown in FIG. 2H, after the photoresist film PR is applied to the entire surface of the dielectric film 33, the photoresist film PR is patterned such that only the dielectric film 33 above the logic part B is exposed through an exposure and development process. Next, the dielectric layer 33, the second insulating layer 30, the first cap insulating layer 27, and the conductive layer for the gate electrode of the logic unit B are etched using the patterned photoresist film PR as a mask. The pattern 26b is removed. That is, the etching process is performed to expose the upper surface of the semiconductor substrate 21 to the logic unit B.

As shown in FIG. 2I, after the photoresist film PR is removed, a second gate insulating film 34 is formed on the entire surface of the semiconductor substrate 21 and the isolation film 24 of the logic unit B. Next, the second gate electrode conductive layer 35 and the second cap insulation layer 36 are formed on the dielectric layer 33 of the memory cell unit A and the second gate insulating layer 34 of the logic unit B. ) In turn. In this case, the second gate insulating film 34 may be formed by heat-treating the semiconductor substrate 21 in an oxidizing atmosphere, or by depositing an insulating film such as a silicon oxide film with a thickness of 500 GPa or less, and the first portion of the memory cell portion A. Since the gate insulating layer 25 is formed in a separate process, the gate insulating layer 25 may have a different thickness. The second gate electrode conductive layer 35 may be formed of a polysilicon layer, or may be formed of a metal material having a high melting point and low specific resistance such as tungsten, tantalum (Ta), copper (Cu), or the like by using a sputtering method or a CVD method. It is formed by the thickness of about 1000 ~ 5000Å.

As shown in FIG. 2J, the logic unit may be selectively patterned (photolithography process + etching process) of the second cap insulation layer 36, the conductive layer 35 for the second gate electrode, and the second gate insulation layer 34. A second gate electrode 35a having a predetermined interval is formed in (B), and in the memory cell portion A, the capacitor second electrode 35b is formed on the surface of the dielectric film 33 adjacent to the capacitor first electrode 32. ). Subsequently, a second sidewall spacer 37 is formed in a conventional process using an insulating film on the side surfaces of the patterned second cap insulating layer 36 and the second gate electrode 35a and the side surface of the capacitor second electrode 35b. Form. Subsequently, impurity ions are implanted into the semiconductor substrate 21 under the side of the second gate electrode 35a by ion implantation to form a second impurity region 38 to be used as a source / drain. In this case, the second impurity region 38 is formed of an impurity region having an LDD structure. The second gate electrode 35a is formed above the isolation layer 24 and is formed to expose the upper side of the semiconductor substrate 21 to be used as an active region.

As shown in FIG. 2K, a third insulating film 39 is formed on the entire surface of the substrate including the capacitor second electrode 35b and the second gate electrode 35a. Subsequently, the second and second impurity regions 28 and 38 of side surfaces of the memory cell unit A and the logic unit B are exposed to the first and second gate electrodes 26a and 35a. And selectively removing the third insulating films 30 and 39 to form the contact holes 40, and then connecting the semiconductor substrate 21 to the contact holes 40 and the entire surface of the third insulating films 39. After forming the conductive layer pattern 41 is selectively patterned to form the conductive layer pattern 41. The conductive layer pattern 41 may be formed of a doped polysilicon layer, or may be formed of a silicide laminated film such as polysilicon and tungsten silicide (WSi ₂ ), or a Bayer metal layer such as Ti / TiN and a metal layer such as tungsten or aluminum. It is formed as a lamination film of and used as a bit line, a metal wiring, or a capacitor first electrode.

3A to 3J are cross-sectional views of a transistor manufacturing process of the semiconductor device according to the second embodiment of the present invention.

First, as shown in FIG. 3A, a first insulating film 22 is formed on the semiconductor substrate 21 defined by the memory cell portion A and the logic portion B to have a thickness of 1000 to 10000 GPa.

As shown in FIG. 3B, the first insulating film 22 is selectively patterned (photolithography process + etching process) to expose the upper surface of the semiconductor substrate 21 in the isolation region. Subsequently, a trench 23 having a predetermined interval is formed by etching the semiconductor substrate 21 by a predetermined depth by an etching process using the patterned first insulating layer 22 as a mask.

As shown in FIG. 3C, an isolation layer 24 is formed in the trench 23 to define an isolation region and an active region. In other words, by forming an isolation film using a trench, a shallow trench isolation (STI) is formed using a conventional method. At this time, the first insulating film 22 on the semiconductor substrate 21 is also removed.

As shown in FIG. 3D, the first gate insulating layer 25, the first gate electrode conductive layer 26, and the first cap insulating layer 27 are sequentially formed on the entire surface of the semiconductor substrate 21 including the isolation layer 24. do. At this time, the first gate insulating film 25 is formed by removing the first insulating film 22 and then heat treating the entire surface of the substrate, or below 500 kW using a dielectric film such as a silicon oxide film. The first gate electrode conductive layer 26 is formed of polysilicon or sputtered a metal material having a relatively high melting point and low resistivity (resistance) such as tungsten (W), tantalum (Ta), or copper (Cu). It is formed to a thickness of 1000 ~ 5000Å by using a CVD method or the like.

As shown in FIG. 3E, the memory cell portion may be selectively patterned (photolithography process + etching process) of the first cap insulation layer 27, the first gate electrode conductive layer 26, and the first gate insulation layer 25. In (A), the first gate electrode 26a having a predetermined interval is formed, and in the logic unit B, the conductive layer pattern 26b for the gate electrode is formed to mask the active region. At this time, the reason why the conductive layer pattern 26b for the gate electrode is left is advantageous in the planarization process. Subsequently, an impurity ion implantation process using the first gate electrode 26a and the conductive layer pattern 26b for the gate electrode as a mask is performed on both side semiconductor substrates 21 of the first gate electrode 26a of the memory cell portion A. ), A first impurity region 28 to be used as a source / drain is formed.

As shown in FIG. 3F, a first sidewall spacer 29 is formed on the side surfaces of the first cap insulating film 27 and the first gate electrode 26a by using an insulating film. Next, a second insulating film 30 is formed on the entire surface of the substrate including the first gate electrode 26a. Subsequently, the second insulating layer 30 on the side of the first gate electrode 26a of the memory cell unit A is selectively removed to form a node contact hole 31. Next, after the capacitor first electrode 32 is formed on the second insulating layer 30 including the node contact hole 31, the second insulating layer 30 adjacent to the node contact hole 31 and the node contact hole 31 is formed. The capacitor first electrode 32 is patterned so that only the phase remains. In this case, the capacitor first electrode 32 may be formed of a doped polysilicon layer, or may be formed of a silicide laminated film such as WSi ₂ and a polysilicon layer, or a barrier metal layer such as Ti / TiN and a tungsten or aluminum layer. It is formed as a laminated film with a metal layer, and can be used as a bit line or a metal wiring in the memory cell portion in addition to the capacitor first electrode 32 as described above.

As shown in FIG. 3G, after the photosensitive film PR is coated on the entire surface of the second insulating film 30 including the capacitor first electrode 32, the second insulating film of the logic part B may be exposed and developed. The photoresist film PR is patterned to expose the upper surface, and then the dielectric film 33 and the second insulating film 30 of the logic part B are subjected to an etching process using the patterned photoresist film PR as a mask. The first cap insulating film 27 and the conductive layer pattern 26b for the gate electrode are removed.

As shown in FIG. 3H, the photosensitive film PR is removed. Subsequently, a dielectric film 33 is formed on the entire surface of the substrate including the capacitor first electrode 32. Next, the second gate electrode conductive layer 35 and the second cap insulation layer 36 are sequentially formed on the entire surface of the dielectric layer 33. In this case, the dielectric film 33 is formed to have a thickness of 50 to 1000 하여 using an insulating film containing nitride, and the dielectric film of the memory cell part A is used as the gate insulating film of the logic part B. The second gate electrode conductive layer 35 may be formed of a polysilicon layer, or may be formed of a metal material having a high melting point and low specific resistance such as tungsten, tantalum (Ta), copper (Cu), or the like by using a sputtering method or a CVD method. To form a thickness of about 1000 ~ 5000Å.

As shown in FIG. 3I, the logic portion B may be selectively patterned (photolithography process + etching process) of the second cap insulation layer 36, the conductive layer 35 for the second gate electrode, and the dielectric layer 33. A second gate electrode 35a having a predetermined interval is formed on the surface of the dielectric layer 33. In the memory cell unit A, a capacitor second electrode 35b is formed on a surface of the dielectric film 33 adjacent to the capacitor first electrode 32. Form. Subsequently, a second sidewall spacer 37 is formed in a conventional process using an insulating film on the side surfaces of the patterned second cap insulating layer 36 and the second gate electrode 35a and the side surface of the capacitor second electrode 35b. Form. Subsequently, a second impurity region 38 to be used as a source / drain is formed on the semiconductor substrate 21 under the side of the second gate electrode 35a by an impurity ion implantation process. In this case, the second impurity region 38 is formed of an LDD structure. In this case, the second gate electrode 35a is formed above the isolation layer 24 and is formed to expose the semiconductor substrate 21 to be used as an active region.

As shown in FIG. 3J, a third insulating film 39 is formed on the entire surface of the substrate including the capacitor second electrode 35b and the second gate electrode 35a. Subsequently, the second and second impurity regions 28 and 38 of side surfaces of the memory cell unit A and the logic unit B are exposed to the first and second gate electrodes 26a and 35a. And selectively removing the third insulating films 30 and 39 to form the contact holes 40, and then conducting the conductive films connected to the semiconductor substrate 21 on the entire surface of the third insulating films 39 including the contact holes 40. After the layer is formed, it is selectively patterned to form the conductive layer pattern 41. The conductive layer pattern 41 may be formed of a doped polysilicon layer, or may be formed of a silicide laminated film such as polysilicon and tungsten silicide (WSi ₂ ), or a Bayer metal layer such as Ti / TiN and a metal layer such as tungsten or aluminum. It is formed as a lamination film of and used as a bit line, a metal wiring, or a capacitor first electrode.

4A to 4J are cross-sectional views of a transistor manufacturing process of a semiconductor device according to a third exemplary embodiment of the present invention.

First, as shown in FIG. 4A, the first insulating film 22 is formed on the semiconductor substrate 21 defined by the memory cell portion A and the logic portion B to have a thickness of 1000 to 10000 GPa. Thereafter, the photoresist film PR is coated on the first insulating film 22, and then patterned such that the upper surface of the first insulating film 22 of the memory cell unit A is exposed through an exposure and development process.

As shown in FIG. 4B, the first insulating film 22 of the memory cell unit A is selectively removed by an etching process using the photoresist film PR as a mask. Subsequently, after removing the photoresist film PR, the semiconductor substrate 21 is etched to a predetermined depth by an etching process using the first insulating film 22 as a mask. Subsequently, after the isolation region and the active region are defined in the memory cell unit A, the trench 23 is formed by selectively patterning the semiconductor substrate 21 of the isolation region (photolithography process + etching process). In this case, the isolation region is defined as a predetermined interval from the interface of the memory cell portion A to the logic portion B to the memory cell portion A.

As shown in FIG. 4C, an isolation layer 24 is formed in the trench 23 to define an isolation region and an active region of the memory cell portion A. FIG. In other words, by forming an isolation film using a trench, a shallow trench isolation (STI) is formed using a conventional method. Subsequently, a first gate insulating film 25, a first gate electrode conductive layer 26, and a first cap insulating film 27 are sequentially formed on the entire surface of the substrate of the memory cell portion A including the isolation layer 24. At this time, the first gate insulating film 25 is formed by removing the first insulating film 22 and then heat treating the entire surface of the substrate, or below 500 kW using a dielectric film such as a silicon oxide film. The first gate electrode conductive layer 26 is formed of polysilicon or sputtered a metal material having a relatively high melting point and low resistivity (resistance) such as tungsten (W), tantalum (Ta), or copper (Cu). It is formed to a thickness of 1000 ~ 5000Å by using a CVD method or the like.

As shown in FIG. 4D, the first cap insulating film 27, the first gate electrode conductive layer 26, and the first gate insulating film 25 formed in the memory cell portion A are selectively patterned (photolithography step). + Etching process) to form a first gate electrode 26a having a predetermined interval. Subsequently, a first impurity to be used as a source / drain for both side semiconductor substrates 21 of the first gate electrode 26a of the memory cell unit A by an impurity ion implantation process using the first gate electrode 26a as a mask. Area 28 is formed. Subsequently, first sidewall spacers 29 are formed on the side surfaces of the first cap insulating layer 27 and the first gate electrode 26a by using an insulating layer.

As shown in FIG. 4E, a second insulating film 30 is formed on the entire surface of the memory cell portion A including the first gate electrode 26a. Subsequently, the second insulating layer 30 is selectively removed to expose the first impurity region 28 on the side of the isolation layer 24 of the memory cell unit A to form a node contact hole 31. Next, after the capacitor first electrode 32 is formed on the entire surface of the second insulating layer 30 including the node contact hole 31, the second insulating layer 30 adjacent to the node contact hole 31 and the node contact hole 31 is formed. The capacitor first electrode 32 is patterned so that only the phase remains. In this case, the capacitor first electrode 32 may be formed of a doped polysilicon layer, or may be formed of a silicide laminated film such as WSi ₂ and a polysilicon layer, or a barrier metal layer such as Ti / TiN and a tungsten or aluminum layer. It is formed by applying a laminated film with a metal layer, and may be utilized as a bit line or a metal wiring in the memory cell portion in addition to the capacitor first electrode 32 as described above.

As shown in FIG. 4F, a dielectric film 33 is formed over the second insulating film 30 including the capacitor first electrode 32. Subsequently, the first insulating layer 22 of the logic unit B is removed.

As shown in FIG. 4G, the second gate insulating film 34, the second gate electrode conductive layer 35, and the second cap insulating film 36 are sequentially formed on the semiconductor substrate 21 of the logic unit B. Form. In this case, the thicknesses of the first and second gate insulating layers 25 and 34 of the memory cell unit A and the logic unit B may be different. The second gate electrode conductive layer 35 may be formed of a polysilicon layer, or may be formed of a metal material having a high melting point and low specific resistance such as tungsten, tantalum (Ta), copper (Cu), or the like by using a sputtering method or a CVD method. To form a thickness of about 1000 ~ 5000Å.

As shown in FIG. 4H, the second cap insulating layer 36 and the conductive layer 35 for the second gate electrode are selectively patterned (photolithography process + etching process) to have a predetermined interval in the logic unit B. A second gate electrode 35a is formed, and in the memory cell portion A, a capacitor second electrode 35b is formed on the surface of the dielectric film 33 adjacent to the capacitor first electrode 32. Next, a low concentration impurity region 42 is formed by implanting low concentration impurity ions into the semiconductor substrate 21 under the side surface of the second gate electrode 35a of the logic unit B.

As shown in FIG. 4I, a second sidewall spacer 37 is formed by using an insulating film on the side surfaces of the patterned second cap insulating layer 36 and the second gate electrode 35a and the side surface of the capacitor second electrode 35b. To form. Next, the semiconductor substrate under the side surface of the second gate electrode 35a is formed by a high concentration impurity ion implantation process using the second gate electrode 35a and the second sidewall spacer 37 of the logic unit B as a mask. A second impurity region 38, which is a high concentration impurity region to be used as a source / drain, is formed in 21). In other words, the second impurity region 38 forms an impurity region having an LDD structure.

As shown in FIG. 4J, a third insulating film 39 is formed on the entire surface of the substrate including the second cap insulating film 36 and the second sidewall spacer 37. Subsequently, the first and second impurity regions 28 and 38 on the side surfaces of the memory cell portion A and the logic portion B of the first and second gate electrodes 26a and 35a may be selectively exposed. The contact holes 40 may be formed by selectively removing the second and third insulating layers 30 and 39. Subsequently, a conductive layer connected to the semiconductor substrate 21 is formed on the entire surface of the third insulating layer 39 including the contact hole 40, and then selectively removed to form the conductive layer pattern 41.

The transistor manufacturing method of the semiconductor device according to the present invention has the following effects.

First, since the transistor is formed in the memory cell portion and then the transistor is formed in the logic cell portion, the transistor of the logic portion can be prevented from deteriorating due to excessive heat treatment.

Second, since the thickness of the gate oxide layer of the memory cell unit and the logic unit is formed differently, a transistor suitable for high speed embebed DRAM can be provided.

Third, when the transistor is formed in the memory cell part, the substrate is etched to a certain depth, the transistor and the capacitor are formed, and then the transistor is formed in the logic part to provide an embebed DRAM having improved flatness.

Claims (8)

Forming an isolation layer using trenches having a predetermined interval on the semiconductor substrate defined by the memory cell unit and the logic unit; Forming a first gate insulating film, a conductive layer for a first gate electrode, and a first cap insulating film on the entire surface of the semiconductor substrate; Selectively removing the first cap insulating layer, the first gate electrode conductive layer, and the first gate insulating layer to form first gate electrodes in the memory cell portion, and leaving the conductive layer pattern for the first gate electrode in the logic portion. ; Forming a first impurity region in the semiconductor substrate under both side surfaces of the first gate electrodes; Forming an interlayer insulating film on an entire surface of the substrate including the first gate electrodes; Selectively removing the interlayer insulating layer between the first gate electrodes of the memory cell unit to form a node contact hole; Forming a capacitor first electrode on the node contact hole and an interlayer insulating film adjacent to the node contact hole; Forming a dielectric film on an entire surface of the substrate including the capacitor first electrode; Removing the dielectric layer, the interlayer insulating film, the first cap insulating film, and the conductive layer pattern for the first gate electrode formed in the logic unit; Forming a second gate insulating film, a conductive layer for a second gate electrode, and a second cap insulating film in the logic part; Selectively removing the second cap insulation layer, the conductive layer for the second gate electrode, and the second gate insulation layer to form a second gate electrode in the logic unit, and to form a capacitor second electrode on the dielectric layer of the memory cell unit. step; And forming a second impurity region in the semiconductor substrate under the side of the second gate electrode. The method of claim 1, wherein the first and second gate insulating layers are formed to have different thicknesses. The method of claim 1, wherein the forming of the isolation layer using trenches having a predetermined interval in the semiconductor substrate defined by the memory cell unit and the logic unit is performed by etching the semiconductor substrate of the memory cell unit to a predetermined depth and then forming an isolation layer. Method for manufacturing a transistor of a semiconductor device. The method of claim 1, wherein the removing of the dielectric film, the interlayer insulating film, the first cap insulating film, and the pattern for the first gate electrode formed in the logic part is performed before forming the dielectric film on the front surface of the substrate including the capacitor first electrode. And removing the negative interlayer insulating film, the first cap insulating film, and the conductive layer pattern for the first gate electrode. 5. The substrate of claim 4, wherein after removing the interlayer insulating layer, the first cap insulating layer, and the first gate electrode pattern of the logic unit, the front surface of the substrate including the isolation layer of the logic unit including the capacitor first electrode and the interlayer insulating layer of the memory cell unit. A method for manufacturing a transistor of a semiconductor device, characterized by forming a dielectric film. The method of claim 5, wherein the dielectric layer formed on the logic unit is used as a second gate insulating layer of the logic unit. The method of claim 1, wherein the second gate electrode is formed on the isolation layer. 7. The method of claim 1 or 6, wherein sidewall spacers are formed on side surfaces of the first and second gate electrodes and side surfaces of the capacitor second electrode.

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