KR20000045324A - Method for forming fine contact hole of semiconductor device - Google Patents
Method for forming fine contact hole of semiconductor device Download PDFInfo
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- KR20000045324A KR20000045324A KR1019980061882A KR19980061882A KR20000045324A KR 20000045324 A KR20000045324 A KR 20000045324A KR 1019980061882 A KR1019980061882 A KR 1019980061882A KR 19980061882 A KR19980061882 A KR 19980061882A KR 20000045324 A KR20000045324 A KR 20000045324A
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- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3105—After-treatment
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- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
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- H01L21/3105—After-treatment
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- H01L21/31105—Etching inorganic layers
- H01L21/31111—Etching inorganic layers by chemical means
- H01L21/31116—Etching inorganic layers by chemical means by dry-etching
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- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
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- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
- H01L21/76877—Filling of holes, grooves or trenches, e.g. vias, with conductive material
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Abstract
Description
본 발명은 반도체소자의 미세 콘택홀 형성방법에 관한 것으로, 특히 미세패턴 사이의 공간에 층간 절연층을 증착하면서 빈공간(void)을 형성하고 화학-기계연마법과 건식식각을 이용하여 미세 콘택홀을 형성하는 반도체 제조방법에 관한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for forming a fine contact hole in a semiconductor device. In particular, a void is formed by depositing an interlayer insulating layer in a space between fine patterns, and a fine contact hole is formed by using chemical-mechanical polishing and dry etching. It relates to a semiconductor manufacturing method to be formed.
종래기술을 살펴보면 워드라인이나 비트라인을 형성하고 그 위에 비트라인 콘택이나 전하저장 전극 콘택을 형성함에 있어 층간 절연 산화층을 증착하되 상기 층간 절연 산화막에는 빈 공간(Viod)이 없어야 한다. 그리고, 콘택 마스크를 이용한 노광 및 현상 공정으로 감광막 패턴을 제조하고, 이것을 마스크로 이용한 식각공정으로 콘택홀을 형성하고 있다. 이때 노광공정에서 아래에 위치하는 패턴 예를들어 비트라인 또는 워드라인과의 정렬의 정확도를 높이는 것에서 한계가 있으며, 식각공정시 아래에 위치하는 패턴과의 절연을 시키기 위해 질화막을 식각정지층으로 이용한 자기정렬 콘택 ( self-align contact)방법등 여러 방법을 이용 하고 있으나 공정 마진 측면에서 많은 어려움을 갖고 있다.Referring to the prior art, in forming a word line or a bit line and forming a bit line contact or a charge storage electrode contact thereon, an interlayer insulating oxide layer should be deposited, but there should be no void in the interlayer insulating oxide film. Then, a photoresist pattern is manufactured by an exposure and development process using a contact mask, and a contact hole is formed by an etching process using this as a mask. At this time, there is a limit in increasing the accuracy of alignment of the patterns positioned below, for example, bit lines or word lines, in the exposure process, and the nitride film is used as an etch stop layer to insulate the patterns located below during the etching process. There are many methods such as self-aligned contact method, but it has many difficulties in terms of process margin.
본 발명은 반도체 소자의 미세 콘택홀을 형성할 때 발생되는 문제점을 개선하기 위한 반도체 미세 콘택홀 제조방법을 제공하는데 그 목적이 있다.SUMMARY OF THE INVENTION An object of the present invention is to provide a method for manufacturing a semiconductor fine contact hole for improving a problem occurring when forming a fine contact hole of a semiconductor device.
도1은 본 발명에 의해 설계된 디램 소자의 레이아웃을 도시한 도면.1 shows a layout of a DRAM device designed according to the present invention.
도2a, 도3a, 도4a, 도5a 및 도6a는 본 발명의 실시예에 의해 디램 소자의 콘택홀을 형성하는 과정을 도시하되, 도1의 Ⅰ-Ⅰ를 따라 도시한 단면도이다.2A, 3A, 4A, 5A, and 6A illustrate a process of forming a contact hole of a DRAM device according to an embodiment of the present invention, and are sectional views taken along the line II of FIG. 1.
도2b, 도3b, 도4b, 도5b 및 도6b는 본 발명의 실시예에 의해 디램 소자의 콘택홀을 형성하는 과정을 도시하되, 도1의 Ⅱ-Ⅱ를 따라 도시한 단면도이다.2B, 3B, 4B, 5B, and 6B illustrate a process of forming a contact hole of a DRAM device according to an exemplary embodiment of the present invention, and are sectional views taken along II-II of FIG. 1.
도7a 및 도7b는 본 발명에 의해 콘택홀에 도전층이 남은 비트라인 콘택 플러그와 전하저장전극의 콘택 플러그를 형성한 것을 각각 도시한 도면7A and 7B illustrate the formation of a bit line contact plug having a conductive layer remaining in a contact hole and a contact plug of a charge storage electrode according to the present invention, respectively.
도8은 본 발명에 의해 미세 콘택홀에 콘택 플러그가 형성된 디램의 레이아웃을 도시한 도면.8 is a view showing a layout of a DRAM having a contact plug formed in a fine contact hole according to the present invention.
〈도면의 주요 부분에 대한 부호의 설명〉<Explanation of symbols for main parts of drawing>
10) : 반도체 기판 1 : 소자분리막10): semiconductor substrate 1: device isolation film
2 : 게이트 산화막 3 : 워드라인2 gate oxide 3 word line
4 : 제1질화막 5 : 제1 절연 산화층4: first nitride film 5: first insulating oxide layer
6 : 절연 스페이서 7 : 제 2절연 산화층6: insulating spacer 7: second insulating oxide layer
8 : 빈 공간 10 : 콘택홀8: empty space 10: contact hole
11 : 도전층 13 : 비트라인 콘택 플러그11: conductive layer 13: bit line contact plug
14 : 전하저장전극 콘택 플러그 52 : 소자활동영역14: charge storage electrode contact plug 52: device active area
54 : 워드라인54: wordline
상기한 목적을 달성하기 위한 본 발명은 반도체소자의 미세 콘택홀 제조방법에 있어서,In the present invention for achieving the above object in the method for manufacturing a fine contact hole of a semiconductor device,
반도체 기판 상부에 도전층으로 워드라인을 형성할 때 비트라인 콘택홀 또는 전하 저장전극 콘택홀이 형성될 부분에 인접한 워드라인을 넓게 형성하여 워드라인과 워드라인 사이 공간을 작게 형성하는 단계와,When the word line is formed as a conductive layer on the semiconductor substrate, forming a word line adjacent to a portion where the bit line contact hole or the charge storage electrode contact hole is to be formed to form a small space between the word line and the word line;
절연 산화층을 증착할 때 상기 워드라인과 워드라인 사이에 빈 공간(void)이 발생되는 절연 산화층을 형성하는 단계와,Forming an insulating oxide layer in which a void is generated between the word line and the word line when the insulating oxide layer is deposited;
화학-기계연마법을 통해 상기 절연 산화층의 일정 두께를 연마하여 상기 콘택홀 영역에 있는 빈공간의 입구부분이 드러나도록 하는 단계와,Polishing a predetermined thickness of the insulating oxide layer by a chemical-mechanical polishing method so that the entrance portion of the empty space in the contact hole region is exposed;
식각공정으로 상기 빈공간이 구비된 절연 산화층을 건식식각하여 콘택영역의 실리콘 기판이 노출된 콘택홀을 형성하는 단계를 포함한다.And etching the insulating oxide layer having the empty space by an etching process to form a contact hole in which the silicon substrate in the contact region is exposed.
상기 워드라인은 폴리 실리콘 및 텅스텐 실리사이드의 적층구조 또는 폴리실리콘 및 티타늄 실리사이드의 적층 구조로 이루어지며, 상기 워드라인은 상부 및 측면에는 질화막으로 구비되며, 상기 화학-기계연마법으로 연마 공정시 워드라인 상부에 구비된 질화막을 베리어막으로 이용한다.The word line is formed of a laminated structure of polysilicon and tungsten silicide or a laminated structure of polysilicon and titanium silicide, and the word line is formed of a nitride film on the upper and side surfaces thereof, and the upper part of the word line in the polishing process by the chemical mechanical polishing method. The nitride film provided in the above is used as a barrier film.
그리고, 상기 빈 공간이 발생되는 절연 산화층은 스텝 커버리지(step coverage) 가 나쁜 산화막으로 증착하며, 상기 콘택홀에 콘택 플러그를 형성한다음, 후속 공정을 진행하는 것을 특징으로 한다.In addition, the insulating oxide layer in which the empty space is generated is deposited with an oxide film having poor step coverage, a contact plug is formed in the contact hole, and then a subsequent process is performed.
본 발명은 비트라인 또는 전하 저장전극 콘택이 형성될 소자활동영역(active area)부분의 워드라인을 조금 크게 형성하여 워드라인과 워드라인 사이 공간을 작게 하고, 이 작은 공간에 절연 산화층을 증착할 때 빈 공간(void)이 발생되는 절연 산화층을 형성한다음, 화학-기계연마법(Chemical mechanical Polishing)을 통해 빈공간의 입구부분이 드러나도록 연마를 하고 드러난 홀 부분을 건식식각을 통하여 실리콘 기판까지 식각을 하여 콘택홀을 형성한다음, 콘택홀에 도전층을 채워서 상부 도전층과 콘택하는 기술이다.According to the present invention, when the word line in the portion of the active area where the bit line or the charge storage electrode contact is to be formed is formed to be slightly larger, the space between the word line and the word line is reduced, and when the insulating oxide layer is deposited in the small space. After forming an insulating oxide layer in which voids are generated, chemical mechanical polishing is performed to expose the inlet portion of the voids, and the exposed holes are etched to the silicon substrate through dry etching. Forming a contact hole, and then filling the contact hole with the conductive layer to make contact with the upper conductive layer.
이하, 첨부된 도면을 참조하여 본 발명의 실시예를 상세히 설명하기로 한다.Hereinafter, embodiments of the present invention will be described in detail with reference to the accompanying drawings.
도1은 디램 소자의 레이아웃을 도시한 도면으로서, 소자활동영역(52), 워드라인(54)을 각각 도시하되, 본 발명에 의해 소자활동영역(52)에 콘택홀이 형성될 부분에서 워드라인이 더 넓게 구비되는 것을 도시한다. 여기서, 소자활동영역(52)이 아닌 지역은 필드영역으로 이용된다.FIG. 1 is a diagram illustrating a layout of a DRAM device. The device active area 52 and the word line 54 are illustrated, respectively, and according to the present invention, a word line is formed at a portion where a contact hole is to be formed in the device active area 52. It is shown that this is provided more widely. Here, an area other than the device active area 52 is used as the field area.
도2a, 도3a, 도4a, 도5a 및 도6a는 본 발명의 실시예에 의해 디램 소자의 콘택홀을 형성하는 과정을 도시하되, 도1의 Ⅰ-Ⅰ를 따라 도시한 단면도이다.2A, 3A, 4A, 5A, and 6A illustrate a process of forming a contact hole of a DRAM device according to an embodiment of the present invention, and are sectional views taken along the line II of FIG. 1.
도2b, 도3b, 도4b, 도5b 및 도6b는 본 발명의 실시예에 의해 디램 소자의 콘택홀을 형성하는 과정을 도시하되, 도1의 Ⅱ-Ⅱ를 따라 도시한 단면도이다.2B, 3B, 4B, 5B, and 6B illustrate a process of forming a contact hole of a DRAM device according to an exemplary embodiment of the present invention, and are sectional views taken along II-II of FIG. 1.
도2a 및 도2b는 반도체 기판(100)의 필드 영역에 소자분리막(1)을 형성하고, 소자활동영역에 게이트 산화막(2)을 형성한다음, 워드라인(3)용 도전층, 제1 질화막(4) 및 제1 절연 산화층(5)을 적층하고, 워드라인 마스크를 이용한 식각공정으로 워드라인(3)을 형성하고, 상기 워드라인(3)의 측벽에 질화막으로 된 절연 스페이서(6)를 형성한 단면도이다. 여기서, 소자활동영역 상부에 구비된 워드라인(3)과 워드라인(3) 사이 공간을 소자분리막 상에 구비된 워드라인(3)과 워드라인(3) 사이 공간에 비하여 좁게 형성하도록 하되, 비트라인 형성을 위해 비트라인 콘택홀에 해당되는 부분은 소자활동영역 상부에 구비된 워드라인(3)과 워드라인(3) 사이 공간과 동일하게 좁게 형성한다.2A and 2B show a device isolation film 1 in a field region of a semiconductor substrate 100, a gate oxide film 2 in a device active region, and then a conductive layer for a word line 3 and a first nitride film. (4) and the first insulating oxide layer 5 are laminated, and the word line 3 is formed by an etching process using a word line mask, and an insulating spacer 6 made of a nitride film is formed on the sidewall of the word line 3. It is formed section. Here, the space between the word line 3 and the word line 3 provided above the device active region is formed to be narrower than the space between the word line 3 and the word line 3 provided on the device isolation layer. To form the line, a portion corresponding to the bit line contact hole is formed to be narrow as the space between the word line 3 and the word line 3 provided on the device active region.
상기 소자분리막(1)은 STI(Shallow Trench Isolation)방법으로 형성을 하고, 워드라인(3)은 폴리 실리콘 및 텅스텐 실리사이드(W-Si)(또는 티타늄 실리사이드:TI-Si)로 증착한다. 상기 질화막(4)은 이 후 CMP 공정시 절연 산화층과의 연마량 차이에 의한 장벽(barrier)으로 이용하고 제 1절연 산화층(5)은 워드라인 단차를 높여 절연 산화층 빈 공간(void) 형성시 질화막(4)보다 위에 형성하기 위해 이용된다.The device isolation layer 1 is formed by a shallow trench isolation (STI) method, and the word line 3 is deposited using polysilicon and tungsten silicide (W-Si) (or titanium silicide: TI-Si). The nitride film 4 is then used as a barrier due to the difference in polishing amount from the insulating oxide layer in the CMP process, and the first insulating oxide layer 5 increases the word line step so that the nitride film is formed when the insulating oxide layer void is formed. It is used to form above (4).
도3a 및 도3b는 제 2절연 산화층(7)을 증착하는 경우 빈 공간(8)이 형성 됨을 도시한다. 여기서 절연 산화층은 SiH4 개스를 이용 플라즈마 CVD방식으로 증착하는 PE-산화막과 같은 스텝 커버리지(step coverage) 가 나쁜 산화막을 이용하여 빈 공간을 형성한다. 이 때 비트라인 콘택홀 및 전하저장전극 콘택홀이 형성될 부분에서 빈 공간이 함께 남게 된다.3A and 3B show that an empty space 8 is formed when the second insulating oxide layer 7 is deposited. Here, the insulating oxide layer forms an empty space using an oxide film having poor step coverage, such as a PE-oxide film deposited by plasma CVD using SiH 4 gas. At this time, empty spaces remain together at portions where bit line contact holes and charge storage electrode contact holes are to be formed.
도4a 및 도4b는 제 2절연 산화층(7)을 화학-기계연마법으로 제 1질화막(4)까지 연마하여 빈 공간(8)이 노출되도록 한 것을 도시한 단면도이다. 여기서 질화막(4)은 산화층 연마량에 비해 매우 적게 연마되는 성질이 있어 산화층 연마시 베리어로 이용된다.4A and 4B are sectional views showing that the empty space 8 is exposed by polishing the second insulating oxide layer 7 to the first nitride film 4 by a chemical-mechanical polishing method. In this case, the nitride film 4 has a property of being polished very little compared to the polishing amount of the oxide layer, and thus is used as a barrier when polishing the oxide layer.
도5a 및 도5b는 상기 빈 공간(8)이 노출된 상태에서 전면 산화막 건식식각공정을 진행하여 빈 공간에 남아있는 제2 절연 산화층(7)이 식각되면서 소자활동영역의 반도체기판(100)이 노출되는 콘택홀(10)이 형성된다. 이 때 소자분리막(1) 상에 있는 제2 절연 산화층(7)의 일정 두께도 식각되며, 제 1질화막(4)은 산화막 식각율에 비해 매우 작은 특성이 있어서 거의 식각되지 않는다.5A and 5B show that the semiconductor substrate 100 of the device active region is formed by etching the second insulating oxide layer 7 remaining in the empty space by performing a dry etching process on the entire surface of the oxide film while the empty space 8 is exposed. An exposed contact hole 10 is formed. At this time, a predetermined thickness of the second insulating oxide layer 7 on the device isolation film 1 is also etched, and the first nitride film 4 has a very small property compared to the oxide film etch rate and is hardly etched.
도6a 및 도6b는 도전층(11)으로 폴리 실리콘을 상기 콘택홀(10)이 완전히 채워지는 두께로 증착한 것을 도시한다.6A and 6B illustrate the deposition of polysilicon with a conductive layer 11 to a thickness in which the contact hole 10 is completely filled.
도7a 및 도7b는 화학-기계연마법 또는 에치백 공정으로 상기 제 1질화막(4)의 상부면까지 상기 도전층(11)을 연마하거나 식각하여 콘택홀(10)에 도전층(11)이 남은 비트라인 콘택 플러그(13)과 전하저장전극의 콘택 플러그(14)를 형성한 것을 도시한 것이다.7A and 7B show that the conductive layer 11 remains in the contact hole 10 by polishing or etching the conductive layer 11 to the upper surface of the first nitride film 4 by chemical mechanical polishing or etch back process. The bit line contact plug 13 and the contact plug 14 of the charge storage electrode are formed.
도8은 본 발명에 의해 비트라인 콘택 플러그(13)와 전하저장전극의 콘택 플러그(14)이 형성되는 것을 도시한 레이아웃으로서, 상기 비트라인 콘택 플러그(13)는 소자활동영역 뿐만아니라 아래로 인접된 필드영역까지 길게 형성이 되는 것을 알수가 있다.8 is a layout showing the formation of the bit line contact plug 13 and the contact plug 14 of the charge storage electrode according to the present invention, in which the bit line contact plug 13 is adjacent to the bottom of the device active region as well as down. It can be seen that it is formed to a long field area.
이후의 공정은 일반적인 공정과 같이 비트라인과 전하저장전극을 형성하면 된다.Subsequent processes may form bit lines and charge storage electrodes as in the general process.
본 발명은 콘택홀을 형성하는 공정에서 감광막을 도포하고, 노광 및 현상 공정으로 마스크를 제조하는 공정을 생략하며, 패턴 사이의 콘택이 자동으로 정렬이 될 수 있어 층간 쇼트(interlayer short)을 방지할 수 있고 공정 단순화 및 시간을 단축할 수 있어 생산성을 향상시킬 수 있다.The present invention omits the process of applying a photoresist film in the process of forming a contact hole, manufacturing a mask by an exposure and development process, and the contact between the patterns can be automatically aligned to prevent interlayer shorts. The productivity can be improved by simplifying the process and shortening the time.
Claims (7)
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| KR1019980061882A KR20000045324A (en) | 1998-12-30 | 1998-12-30 | Method for forming fine contact hole of semiconductor device |
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| KR1019980061882A KR20000045324A (en) | 1998-12-30 | 1998-12-30 | Method for forming fine contact hole of semiconductor device |
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Cited By (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR100357195B1 (en) * | 2000-12-15 | 2002-10-19 | 주식회사 하이닉스반도체 | method for forming contact metal line semiconductor device |
| KR20030002752A (en) * | 2001-06-29 | 2003-01-09 | 주식회사 하이닉스반도체 | Method of manufacturing a semiconductor device |
| KR100492898B1 (en) * | 2001-12-14 | 2005-06-03 | 주식회사 하이닉스반도체 | Method for fabricating semiconductor device |
| KR100630666B1 (en) * | 2000-08-09 | 2006-10-02 | 삼성전자주식회사 | Method of manufacturing semiconductor device including metal contact and capacitor |
| KR101034407B1 (en) * | 2009-02-23 | 2011-05-12 | 주식회사 하이닉스반도체 | Nonvolatile memory device and manufacturing method of the same |
-
1998
- 1998-12-30 KR KR1019980061882A patent/KR20000045324A/en not_active Application Discontinuation
Cited By (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR100630666B1 (en) * | 2000-08-09 | 2006-10-02 | 삼성전자주식회사 | Method of manufacturing semiconductor device including metal contact and capacitor |
| KR100357195B1 (en) * | 2000-12-15 | 2002-10-19 | 주식회사 하이닉스반도체 | method for forming contact metal line semiconductor device |
| KR20030002752A (en) * | 2001-06-29 | 2003-01-09 | 주식회사 하이닉스반도체 | Method of manufacturing a semiconductor device |
| KR100492898B1 (en) * | 2001-12-14 | 2005-06-03 | 주식회사 하이닉스반도체 | Method for fabricating semiconductor device |
| KR101034407B1 (en) * | 2009-02-23 | 2011-05-12 | 주식회사 하이닉스반도체 | Nonvolatile memory device and manufacturing method of the same |
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