KR20020035606A - Field programmable gate array hard disk system - Google Patents

Abstract

The FPGA / HD assembly is fully self-contained by integrating the FPGA into the HDD assembly, which stores in-circuit programming for the FPGA, and any selected interface and control under the control of the controller embedded in the HDD. Modify the FPGA to work together. The internal circuit programming data is stored directly on the selected partition of the HDD, leaving the space required for any other data traditionally stored on the HDD. The controller locates a suitable soft core into the FPGA while being commanded to locate specific internal circuit data and identify the bus associated with any selected operation.

Description

Field Programmable Gate Array Hard Disk System {FIELD PROGRAMMABLE GATE ARRAY HARD DISK SYSTEM}

The prior art allows for in-circuit programmability for a field programmable gate array (FPGA). Typically, such data resides in memory or is passed to the FPGA via a host computer. Ultimately, this data resides in some storage device (RAM, ROM, or hard disk that is all accessed through host intervention). The data is used to program the FPGA to perform the specified functions of the FPGA. Due to the limitation of memory capacity and the load on the CPU leading the data to the FPGA, the number of interfaces is substantially limited.

Such limitations are of particular importance in devices such as data reciprocating devices, which are disclosed in related applications incorporated herein by reference. In this application, one data reciprocating device is disclosed and it is particularly useful for portable storage of input data streams from multiple sources, which sources include television signals, SPDIF formatted data and USB buses, ATA buses. Or information received over a bus, such as a 1394 bus. Each of these requires its own interface, increases the number of chips to be integrated, increases the amount of functional silicon, and consequently increases the cost of multi-interface products.

FIELD OF THE INVENTION The present invention generally relates to the field of memory systems incorporating hard disk drives and more particularly to a system that provides a process for a plurality of fully configurable interfaces or hard disk drives.

1 is a block diagram showing the basic configuration diagram of the present invention.

2 is a block diagram illustrating a board level multi-interface in which the present invention is useful.

It is an object of the present invention to make one assembly compatible with multiple interfaces.

More specifically, in the present invention, many interface chips are replaced by one or more FPGA chips.

More specifically, in the present invention the FPGA is characterized by programming information stored on the associated hard disk.

More specifically, the present invention is characterized by an FPGA integrated into a hard disk assembly that stores associated in-circuit programming data.

Another feature on top is that the FPGA is integrated into the hard disk assembly and the programming is modified by a controller embedded in the hard disk assembly.

In summary, the FPGA / HD assembly is complete by integrating the FPGA into the HDD assembly, the HDD stores in-circuit programming for the FPGA, and the HDD is under the control of the controller embedded in the HDD. Modify the FPGA to work with any selected interface. An advantage of the present invention is that the internal circuit programming data is stored directly on the selected partition of the HDD, leaving the space required for any other data traditionally stored on the HDD. The controller locates a suitable soft core into the FPGA while being commanded to locate specific internal circuit data and identify the bus associated with any selected operation.

Other features and advantages of the invention will be apparent to those of ordinary skill in the art having knowledge of the disclosure herein given in conjunction with the following figures.

The following describes a system incorporating a field programmable gate array (FPGA) into a hard disk drive assembly (HDD) to provide a variety of fully configurable interfaces or processors for hard disk drives. However, it should be appreciated that the features and advantages of the present invention are not limited to the specific block diagrams herein. Features of the invention can be used with any number of interfaces or processors; Furthermore, FPGA data can be stored in a partition segment of any size disk drive.

With reference to FIG. 1, the basic components of implementing the present invention include a disk drive assembly 100 and the disk drive assembly includes an FPGA 104 that is preferably embedded or closely coupled with an embedded controller 102. . As is well known in the FPGA art, the functionality of this device 104 may be modified from time to time based on the data downloaded to the FPGA to define functionality specific to its "soft core." For example, in the field of devices required to utilize multiple interfaces, such as an ATA interface, a 1394 interface, or a USB interface, the FPGA 104 may be based on data loaded into it by the controller 102. Employ the necessary signal processing structures and functions at any given time. According to the invention, such data may be stored on a separate partitioned area 110 of the HDD 100 after the required interface is defined. At any time during the use of the FPGA, based on some external control signal, time function, or the like, the FPGA is to provide a special interface to the entire system 10, and the controller 102 is also a board. And a disk drive can download data from the FPGA data partition 110 on the disk drive into the FPGA 104. As soon as the FPGA data is downloaded, the FPGA is used as a separate programmable device.

As such, in accordance with the present invention, any programmable interface from the groups described above or other unspecified groups can be used for assignment by any user as needed. Soft core data may be time multiplex loaded or otherwise allocated to be unloaded without additional host computer intervention and loading under one external signal control received from an external host computer. This can significantly reduce any manufacturing cost by homogenizing the HDD assembly and preliminarily removes the functional silicon required to implement each required interface.

An embodiment of a board level system using multiple interfaces that can be properly implemented by those skilled in the art and which can advantageously incorporate the present invention is a data round trip using the disk storage device shown in FIG. It is a data shuttle.

The data shuttle transfers continuous streams of digital information from multiple sources, passes them through multiple interfaces integrated into the data shuttle, and passes them across the bus to the hard disk drive. In this figure, inputs from multiple devices or sources of data are represented on the left and they become outputs for potential destinations. If the received data is in analog format, it is digitized as shown at the top left, for example at the top left the composite TV video signal 700 and associated audio 702 are applied to a suitable A / D converter 704, 706. And then to the MPEG-2 encoder 710 via the bus. The output of the MPEG-2 encoder 710 is sent to the disk processor 714 via a data packetizer 712, which may be configured for proper file management, bus arbitration, content management ( content management and stream management functions and the resulting data may be stored on a local hard disk drive 720. In this way, any required video input stream may be The data may be converted, digitized, processed and stored for selective access on the data round trip device. The MPEG encoder and decoder may be implemented with an FPGA reprogrammed under the control of an embedded microprocessor 270 using data stored on the local HDD 220. In this way, the number of actual encoder / decoder chips can be substantially reduced.

The data reciprocating device may also be coupled to a larger hard disk drive integrated within a nesting or docking device 760 for the data reciprocating device across the interface. The disk processor 714 can then further transfer the stored digital data from the local disk drive 720 onto the nesting disk drive 740 across the larger capacity ATA bus. In this way, the data reciprocating device can be transferred from one device to another and store the input data through several interfaces shown from one or several sources.

The data reciprocating mobile device operates under the control of its local processor 770 and includes a power source and a monitor 772 and control devices 780-784.

Among other interfaces, the data round trip device also includes an input / output bus 720 that works to manipulate the SPDIF format. The input / output bus 720 is directly connected to the data packetizer 712 and then to the disk processor 714 across the bus. Another SPDIF input 722 for reception of digital audio is an input to an MPEG-2 encoder 710; The output of the MPEG-2 encoder is also passed to the disk processor 714 for storage on the local hard disk 720 or the nesting hard disk 740. The digital audio source 722 can also be applied to the MP3 encoder 724 and the output of the MP3 encoder is directly connected to the data packetizer 712 and then to the disk processor 714 to connect any data in the SPDIF format. Can be stored and selectively accessed.

Multiple bidirectional buses are also provided, including a USB bus 730, a 1394 bus 732, and an ATA bus 734. The USB bus 730 may provide a two-way connection to an MP3 player, digital camera or PC, for example. Through the USB PHY 740 and the packetizer 742, any of these devices are directly coupled to the data packetizer and their inputs and outputs are then passed through the processor 714 to the hard disk drive ( 720). In a similar manner, the 1394 bus 732 can be connected to a digital video camera or PC, or a digital VCR, and through the appropriate PHY 744 and packetizer 746, the data packetizer 712 and disk processor 714. Leads to). Finally, the ATA bus 734 can connect flash memory or other data storage device directly to the disk processor 714 and then to the disk drive 720.

On the output side, when the SPDIF input 722 can be passed through an MP3 encoder for storage, an MP3 decoder 750 is provided and its output is coupled to the SPDIF output bus 752 or alternatively an audio processor ( 754 may be coupled to a modulator amp 756. This provides several alternative output lines including RF modulated AV 758, stereo phone output 760 and audio output 762. The audio output is more typically used with the television output 764 coming out of the modulator amplifier via the MPEG-2 decoder 768 and the digital video encoder 766. The MPEG-2 decoder receives its video information from the depacketizer 712 and the disk processor 714, which may optionally access any file on the local disk 720, as mentioned above. have. All these functions are performed under the control of the CPU 770 and the CPU is a Motorola 823E supported by, for example, a power source 772 and a monitor.

The function is selected and the input, output and destination are recognized via IR control 780 and the selected function is displayed on LCD display 782 in front of the data reciprocating device. Both are supported via control I / O 784 integrated into the data reciprocating device and control the functionality of CPU 770 via bus 786.

Similar to the foregoing, FPGAs may be used where each bus includes a packetizer / depacketizer. When the bus is selected, the microprocessor can download the necessary data from the disk drive to program the FPGA to provide the necessary packetizer / depacketizer.

In this way, the processor board can be simplified without additional burden if it is actually located on the host computer, which means that the embedded processor does not have time to download critical data from the internal disk drive without conflicting with its data storage control. Because it is possible.

Other uses, features and advantages of the present invention will be apparent to those skilled in the art having knowledge of the disclosure. Accordingly, the scope of the invention is not limited only to the claims that follow.

Claims (6)

A system comprising a field programmable gate array (FPGA) integrated into a hard disk drive assembly, the system comprising: The hard disk drive assembly further comprising an integrated microprocessor, The hard disk drive stores data such that the FPGA is arranged to perform a number of different functions under the control of an on-board processor without intervention by a host of the entire system. The method of claim 1, A plurality of interfaces, each of which is connected to the hard disk drive through an encoder or decoder, one or more encoders and decoders are implemented by one FPGA, and the FPGA stores data stored on the hard disk drive And reprogrammed to work with other interfaces. The method of claim 1, A plurality of interfaces, each interface connected to the hard disk drive through a packetizer or depacketizer, one or more packetizers and depacketizers implemented by a single FPGA, and And an FPGA adapted to be programmed to work with a selected one of a number of interfaces by data stored on a hard disk drive. The method of claim 3, wherein The FPGA is adapted to store a plurality of data sets for programming the FPGA in an identifiable section of the hard disk drive and in response to instructions from an embedded processor dependent on the interface selected to send or receive data from the system. And a disk controller adapted to select one of said data sets for programming. A method of implementing a system that includes an FPGA integrated into a hard disk drive assembly, Further comprising a microprocessor to which the hard disk drive assembly is integrated, The hard disk drive stores data such that the FPGA is arranged to perform a number of different functions under embedded processor control without intervention by the host of the entire system, Storing a plurality of data sets for programming the FPGA on a partitioned area of the hard disk drive; Identifying a selected one of the interfaces to send or receive data from the system; And Programming said FPGA with one of a set of data from a hard disk drive in response to confirmation of a selected interface under control of an embedded processor. A system comprising an FPGA integrated into a hard disk drive assembly, Further comprising a microprocessor to which the hard disk drive assembly is integrated, The hard disk drive stores data such that the FPGA is arranged to perform many other functions under the control of an embedded processor without intervention by the host of the entire system, Store a plurality of data sets for programming the FPGA on a partitioned area of the hard disk drive, Means for programming the FPGA with one of a set of data from a hard disk drive in response to confirming the selected interface under control of an embedded processor.