CN100433697C - Multi-channel high-speed data processor and processing method - Google Patents

Multi-channel high-speed data processor and processing method Download PDF

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CN100433697C
CN100433697C CN 200610040769 CN200610040769A CN100433697C CN 100433697 C CN100433697 C CN 100433697C CN 200610040769 CN200610040769 CN 200610040769 CN 200610040769 A CN200610040769 A CN 200610040769A CN 100433697 C CN100433697 C CN 100433697C
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module
data
memory
channel
high
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CN1889503A (en )
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胡爱群
裴文江
杰 黄
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东南大学
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多通道高速数据处理器及处理方法是一种无线网络安全领域的高速数据处理设备,它采用现场可编程门阵列为基础平台,是一种多通道高速数据处理系统。 The processor and high-speed data processing method of multi-channel high-speed data processing device is a radio network security, which uses a field programmable gate array-based platform, a multichannel high-speed data processing systems. 该处理器具体包括以下的四个模块:现场可编程门阵列硬件模块(1),4倍数据速率接口模块(2),可编程只读存储器程序配置模块(3)和软件系统模块(4);首先由网络处理器发出读写信息和数据信息,队列调度模块(4.1)从网络处理器获取读写及其数据信息,接收模块(4.2)从队列调度模块(4.1)获取相应的写命令后,对缓冲区进行相应的写操作,处理后数据一并传入帧效验序列模块(4.5),经校验后传入发送数据缓存模块(4.3),综合处理判断后将数据写入缓冲区,通过对该缓冲区的读操作将处理后的数据输出。 The processor comprises the following four modules: a field programmable gate array hardware modules (1), 4 times the data rate of the interface module (2), programmable read only memory program configuration module (3) and a software system module (4) after the first read information and data information sent by the network processor, queue scheduling module (4.1) and the data acquisition read information from a network processor receiving module (4.2) (4.1) to obtain the corresponding write command from the queue scheduling module; , corresponding to the buffer write operation, the data collectively after treatment efficacy incoming frame sequence module (4.5), after checking the incoming transmission data buffer module (4.3), the integrated process is determined after the data written to the buffer, the output data processed by a read of the buffer.

Description

多通道高速数据处理器及处理方法 Multi-channel high-speed data processor and processing method

技术领域 FIELD

本发明设备是一种无线网络安全领域的髙速数据处理设备,它采用现场可编 The present invention is an apparatus Gao speed data processing device of a wireless network security, which uses a field programmable

程门阵列(FPGA)为基础平台,是一种多通道高速数据处理系统。 Programmable gate array (FPGA) based platform, a multichannel high-speed data processing systems. 背景技术 Background technique

高速分组数据、多媒体数据和Internet等业务的应用推动着码分多址(CDMA) 从IS-95向CDMA2000 IX升级。 Application of high-speed packet data, multimedia, Internet data, and code division multiple access and other business driving (CDMA) to CDMA2000 IX upgrade from IS-95. 国际标准化组织3GPP2制定了CDMA2000 IX分组数据网络的相关标准,采用了IETF在移动IP技术上己有的工作成果,使网络具有快速提供IP接入的能力、与其他IP网的互通能力、更好的漫游能力及私有网络的IP业务能力,并且使系统具有提供144Kbps、 384Kbps和2Mbps接入速率及简单IP和移动IP业务功能。 International Organization for Standardization has developed 3GPP2 standards CDMA2000 IX packet data network, using the results of some work in the IETF Mobile IP technology has the ability to quickly provide IP network access, interoperability with other IP networks, better roaming capabilities and IP service capabilities of a private network, and the system has provided 144Kbps, 384Kbps and 2Mbps access rate and simple IP and mobile IP service function.

在CDMA2000 IX..网络中,移动台MS或移动手机与分组数据服务节点(PDSN) 之间采用端对端协议(PPP)协议作为数据链路协议。 In CDMA2000 IX .. network using Point Protocol (PPP) protocol as the data link protocol between the mobile station MS or a mobile phone with a packet data serving node (PDSN). 对于从广域网到^动节点的IP包,分组数据服务节点会将它对应到一个具体的端对端协议连接上,通过査找目的移动手机的IP地址与相对应A10连接的映射关系,将IP包发送给移动手机终端;对于从二个己经注册的手机终端的归属代理家乡代理(HA)收到一个】P包时,分组数据服务节点可以根据HA的IP地址和手机终端的IP地址找到相应的RP 连接,发送数据包;对于来自移动手机的IP数据包,手机终端将它封装在端对端协议数据包中向网络发送,经过无线空中接口和基站传输后,再由基站控制器的分组控制功能(PCF)部件将移动终端的端对端协议数据封装在通用路由协议(GRE) ^ For the WAN IP packet to the mobile node, a packet data serving node that will correspond to a particular point protocol connection, the mobile phone by finding the relationship between the destination IP address mapping to the corresponding A10 connection the IP packet to the mobile phone terminal; P] for when receiving a packet from the home agent home agent (HA) has two registered mobile terminals, packet data serving node can find the corresponding IP address according to the IP address of the HA and the mobile terminal RP is connected to the transmission data packet; for IP packets from mobile phones, mobile terminals to the network it sends the encapsulated data packet in the to-point protocol, after a wireless air interface and the base station transmission, then the packet by the base station controller control function (PCF) to move the member to-point protocol encapsulated data terminal in a generic routing protocol (GRE)

隧道中向分组数据脤务节点传送,然后由网络侧的分组数据服务节点对隧道封装数据包进行解包、重新组装处理后路由到网络侧的IP骨干网,或通过反向隧道发送到其归属代理HA处。 Sacrificial flesh tunnel packet data service node transmits, to the tunnel encapsulated packet is then unpacks the packet data service node of the network side, reassembled treatment routed to the IP backbone network side, or transmission through a reverse tunnel to its home Acting at the HA.

基于网络处理器的移动互联网内容监管设备在拦截、过滤和分析CDMA分组数据域的信息时,霈要将端对端协议的高速数据链路控制协议(HDLC)帧连成一个完整的数据包,这时需要对离速数据链路控制协议数据帧转义或反转义,恢复出原始的数据。 Mobile Internet-based content regulation apparatus intercepting network processor, filtering and analyzing information CDMA packet data field, Pei Point Protocol want high-speed data link control protocol (HDLC) frame together into a complete data packet, in this case a data frame needs to escape from the sense or reverse speed data link control protocol, to recover the original data. 但如果这种工作交由网络处理器完成,必将加大系统的开销,极大影响系统的性能。 But if the work to a network processor to complete, will increase the performance overhead of the system, which greatly affect the system.

发明内容 SUMMARY

技术问超:本发明的目的是提供一种多通道高速数据处理系统,我们设计了多 Technical Q Ultra: The purpose of the present invention is to provide a multi-channel high-speed data processing systems, we have designed more than

通道高速数据处理系统来辅助主机工作,从而实现移动互联网内容监管数据的高 High-speed data channel to a secondary host processing system work, mobile Internet content to achieve high data Regulated

速实时处理,减少主机的负担,提高效率。 Speed ​​real-time processing, reduce the burden on the host, and improve efficiency.

技术方案:本发明釆用外加现场可编程门阵列协处理器的方式完成多路异步 Technical Solution: The present invention preclude programmable gate array coprocessor with an externally applied field of asynchronous multiplexing is accomplished

高速数据链路控制协议处理功能,并通过4倍数据速率(QDR)接口与主机通信, Control protocol processing function, and by four times the data rate (QDR) interface for communicating with the host high speed data link,

将原来由软件处理的一些工作由硬件来完成,减少主机的负担,提高效率。 Some work will be handled by the original software to complete by the hardware, reducing the burden on the host, and improve efficiency.

随着微电子技术的发展,现场可编程门阵列器件得到了飞速发展,由于该器 With the development of microelectronics technology, a field programmable gate array device has been rapid development, since this is

件具有工作速度快、集成度髙和现场可编程等特点,因而在数字信号处理中得到 Member having a working speed, a field programmable integration Gao and characteristics, thereby obtaining a digital signal processing

了广泛的应用。 A wide range of applications. 本发明基于高速数据链路控制协议的基本原理,在Xilinx公司的 The present invention is based on the basic principle of a high speed data link control protocol, in Xilinx's

现场可编程门阵列芯片Spartan系列器件(XC3S2000—4FG676C)完成了本发明的 A field programmable gate array chip Spartan series devices (XC3S2000-4FG676C) completed the present invention.

设计。 design. 高速数据链路控制协议是一个面向位的协议,支持半双工和全双工通信, High Speed ​​Data Link Control protocol is a bit-oriented protocol that supports full duplex and half-duplex communication,

它被广泛应用与数据通信领域,是其他许多数据链路控制协议的技术。 It is widely used in the field of data communications, techniques are many other data link control protocol. 它具有很 It has a very

强的差错检错、髙效和同步传输的特点。 Strong error detection error, and efficiency characteristics Gao synchronous transmission. 目前许多网络路由设备和交换机均利用 Many network routing devices and switches utilize

高速数据链路控制协议作为其链路协议。 High speed data link control protocol as its link protocol.

本发明髙速数据处理器主要对来自主机的多路高速数据链路控制协议帧进行并行的解封装和端对端协议包反转义处理,最后将结果反馈主机进行下一步的重组和协议处理,从而缓解了主机负担过重,系统开销过大的压力,保证了整个移动互联网监控系统的高速运转。 Gao speed data processor of the present invention mainly multiple high-speed data link control protocol frames from the host and the parallel-point protocol packet decapsulation unescapes process, the final result back to the next host protocol processing and restructuring to relieve the overburdened host system overhead is too much pressure to ensure the functioning of the entire high-speed mobile Internet monitoring system. 本发明提出的多通道髙速数据处理系统,-一方面 The present invention is proposed Gao speed multichannel data processing system, - on the one hand

遵循了IEEE的国际标准,实现了标准规定的基本功能——高速数据链路控制协议帧的转义/反转义以及循环冗余码效验(CRC)校验;另一方面还提供了可扩展的、 灵活借口,根据以后的实际霈要,对处理器进行扩展;另外,该处理器设计完毕后,可以通过在现已开发的软件或硬件上稍加修改,可以将该处理器改造为其他通信产品,例如帧中继系统,综合服务数字网(ISDN), 125数据网,骨干和边缘路由器等各种数据环境网环境中,所以本高速数据链路控制协议处理器仍有相当广泛的应用前景。 It follows the IEEE international standards, the basic functions required standards - escape high speed data link control protocol frames / unescapes efficacy and a cyclic redundancy code (CRC) check; further aspect provides a scalable flexible excuse, according to Pei actual future, to extend the processor; in addition, after the processor design is complete, you can now slightly modified in the development of software or hardware, the processor can be transformed into other communications products such as frame relay systems, integrated services digital network (ISDN), 125 data network backbone and edge routers, and other network environment, the data environment, the present high-speed data link control protocol processor is still a wide range of applications prospect.

本发明设备的结构如下-本发明包含现场可编程门阵列硬件模块,4倍数据速率接口模块,可编程只读 Apparatus of the invention follows the structure - according to the present invention comprises a field programmable gate array hardware module, the interface module 4 times the data rate, programmable read only

存储器程序配置模块和软件系统模块等四个部分。 Configuration four memory modules and software part module. 其中: among them:

1、 现场可编程门阵列硬件模块 1, a field programmable gate array, hardware modules

釆用200万门现场可编程门阵列,作为主机的协处理器,在该设备中居于核心地位。 Bian programmable gate array site with 2 million, as the host coprocessor, the key part of the apparatus. 现场可编程门阵列与4倍数据速率接口之间通过LA一1协议进行通信。 A field programmable gate array 4 and the data rate between the interface 1 communicates through a protocol LA. I/O 电平输出遵循HSTL—1—DCI(1.5V)标准,为此需提供额外的0.75V参考电平。 I / O level output follows the HSTL-1-DCI (1.5V) standard, required for this additional 0.75V reference level. 现场可编程门阵列通过与Flash可编程只读存储器(FLASH PROM)之间的串行接口接受配置信息,此外,还可以通过JTAG接口直接对现场可编程门阵列进行配置和调试。 Field programmable gate array through a serial interface accepts configuration information between Flash programmable read only memory (FLASH PROM) and, in addition, also possible to configure the field programmable gate array and debug directly through the JTAG interface. 上电后,现场可编程门阵列自行向可编程只读存储器(PROM)中读取数据, 在工作状态时还可以通过重置信号进行重新配置。 After power, field programmable gate array programmable read-only to read the data on their own memory (PROM) can be reconfigured in the operating state by a reset signal Shihai.

2、 4倍数据速率接口模块 2, four times the data rate interface module

连接主板和该设备,为该设备提供与主机之间的通信和数据交互。 And a motherboard connected to the device for communication and data exchange between the host and the device provides. 此外,该设备的所有供电都由该接口提供。 In addition, all of the power supply device provided by this interface.

(1) 内部集成电路总线接口,接口通过内部集成电路(I2C)总线访问卡上的内部集成电路E2PR0M来获取该设备识别符、工作电平和温度等设备信息,从而识别该设备。 (1) C bus interface, the interface to acquire the equipment identifier, the working level and the internal temperature of integrated circuits and other equipment information (I2C) inside the integrated circuit on the bus E2PR0M access card, so as to identify the device.

(2) 4倍数据速率接口,该设备的16位数据接口在双时钟驱动下倍频成为逻辑32位。 (2) four times the data rate interface, the 16-bit data interface device dual drive clock frequency becomes logic 32. 总线提供可同时工作的四倍速输入输出端口和24位地址线宽。 Bus provides input and output ports and a quadruple-speed 24-bit address width can operate simultaneously.

(3) JTAG调试接口,虽然LA一1标准中包含JTAG接口,但仅限于提供测试接口(不支持对可编程只读存储器和现场可编程门阵列的烧写),所以在设计中另外引入了JTAG插槽,通过PC机直接下载程序到可编程只读存储器。 (. 3) JTAG debug interface, although a 1 LA standard JTAG interface comprises, but only to provide a test interface (no programming the programmable read-only memory and the field programmable gate array), so the design is additionally introduced JTAG slot, the PC by a direct download to the programmable read-only memory.

(4) 外围供电模块,4倍数据速率接口为该设备提供+3.3V、 +1.8¥和+1.5乂直流电压。 (4) the peripheral power supply module, four times the data rate for the device interface provides + 3.3V, + 1.8 ¥ qe DC voltage and +1.5. 除此以外,诸如2.5V、 1.2V、 0.75V电压都由该设备通过+3.3V本地生成。 In addition, such as 2.5V, 1.2V, 0.75V voltage of + 3.3V by the apparatus by a locally generated.

3、 可编程只读存储器程序配置模块 3, the configuration module program programmable read only memory

(1) 内部集成电路总线可编程只读存储器电路,记录协处理器设备信息, 包括设备ID、工作电平和温度等参数,系统启动时,4倍数据速率接口通过内部集成电路总线对其进行检测以识别该设备。 (1) C bus circuit programmable read only memory, a coprocessor recording information including a device ID, temperature and other parameters of the working level, when the system starts, 4 times the data rate thereof is detected by the interface C bus to identify the device. 此外,内部集成电路可编程只读存储器本身还支持口令加密和密码保护。 In addition, inter-integrated circuit programmable read only memory itself supports password encryption and password protection.

(2) Flash可编程只读存储器电路,在上电时自动对现场可编程门阵列进行配置,其配置方式分主从两种模式,其主要区别在于配置时钟信号源的不同。 (2) Flash programmable read only memory circuits, field programmable gate arrays automatically configured when the power, which arrangement the main points from the two modes, the main difference is the different configuration of the clock signal source. 在现场可编程门阵列主控模式中,现场可编程门阵列为可编程只读存储器提供配置时钟信号,在现场可编程门阵列受控模式中,由外部晶振提供配置时钟信号。 In the master mode field programmable gate array, a field programmable gate array programmable read only memory is configured to provide a clock signal, the field programmable gate array controlled mode, the clock signal provided by an external crystal configuration. 4、软件系统模块: 4, system software modules:

软件系统模块实现整个现场可编程门阵列的多通道数据处理功能。 Software module for the entire multi-channel field-programmable gate array in a data processing function. 各驱动模块均采用动态模块加载的方式编写。 The drive modules are prepared using dynamically loaded modules.

软件系统模块主要包括了以下的几个部分:队列调度模块,接收数据缓存模块、发送数据缓存模块、高速数据链路控制协议数据包反转义及其标志字处理模、 帧效验序列模块。 Software module comprises the following major sections: a queue scheduling module, receiving data buffer module, a transmission data buffer module, a high speed data link control protocol packets and flag word unescapes mold frame sequence module efficacy.

在结构上,该处理器具体包括以下的四个模块:现场可编程门阵列硬件模块; 4倍数据速率接口模块;可编程只读存储器程序配置模块和软件系统模块;所述4 倍数据速率接口模块包括:内部集成电路总线接口、 4倍数据速率接口、 JTAG接口和外围供电模块;现场可编程门阵列硬件模块通过4倍数据速率接口连接外部的主机、通过电源线与外围供电模块连接以及通过JTAG接口与可编程只读存储器程序配置模块中的Flash可编程只读存储器电路相接,Flash可编程只读存储器电路还通过JTAG接口与外部的PC机相接;可编程只读存储器程序配置模块中的内部集成电路总线可编程只读存储器电路通过内部集成电路总线接口连接外部的主机;软件系统模块,包括了:队列调度模块、接收数据缓存模块、发送数据缓存模块、高速数据链路控制协议数据包反转义及其标志字 Structurally, the processor comprises the following four modules: a field programmable gate array hardware module; 4 interface module data rate; programmable read only memory modules and configure software module; 4 times the data rate interface module comprising: an internal bus interface integrated circuit, four times the data rate interface, the JTAG interface, and a peripheral power supply module; field programmable gate array of hardware modules connected to an external host through the interface to four times the data rate, the power line is connected via the peripheral power supply module and by JTAG interface and programmable read only memory program module configuration programmable read only memory circuit contact Flash, Flash programmable read only memory circuit further through the JTAG interface in contact with an external PC,; program programmable read only memory configuration module external host C bus circuit programmable read only memory integrated circuit connected by an internal bus interface; software modules, including: a queue scheduling module, receiving data buffer module, a transmission data buffer module, high speed data link control protocol packet unescapes its flag words 理模和帧校验序列模块,软件系统模块包括的各模块之间通过信号传递连接在一起;软件系统模块驻留在可编程只读存储器程序配置模块中,多通道高速数据处理器工作后,程序被加载到现场可编程门阵列硬件模块中,而现场可编程门阵列硬件模块通过4倍数据速率接口模块与主机的程序连接在一起。 The connection between the modules and a frame check sequence processing mold module, comprising software modules together through the signal transmission; software module residing in a programmable read only memory program module configuration, the multi-channel high-speed data processor operates, program is loaded into the field programmable gate array hardware modules, the field programmable gate array of hardware modules connected together by four times the data rate of the host interface module with the program.

现场可编程门阵列硬件模块采用200万门"XC3S2000"现场可编程门阵列作为主机的协处理器。 A field programmable gate array hardware modules 2000000 "XC3S2000" a field programmable gate array as the host coprocessor.

4倍数据速率接口模块中,外围供电模块在生成2.5V电压时,采用了"TPS75525"电压转换芯片;在生成1.2v电压时,采用了"TPS54312"电压转换芯片;在生成0.75V电压时,采用"MAX1589EZTAFJ"芯片。 4 times the data rate of the interface module, the peripheral power supply voltage is 2.5V when generating module, using the "TPS75525" converting chip; 1.2v voltage when generating, using the "TPS54312" converting chip; 0.75V when the generation voltage, the use of "MAX1589EZTAFJ" chip.

可编程只读存储器程序配置模块中,采用内部集成电路总线可编程只读存储器电路记录所述处理器的设备信息,包括设备识别符、工作电平和温度参数,主机通过内部集成电路总线可编程只读存储器电路进行检测以识别多通道高速数据处理器,内部集成电路总线可编程只读存储器电路本身还支持口令加密和密码保 Programmable read only memory module configuration program using C bus programmable read only memory circuit of the recording apparatus of the information processor, comprising a device identifier, a work level and temperature parameters, the host bus is programmable only through the internal IC read memory circuit is detected to identify a multichannel high-speed data processor, programmable read-only memory C bus circuit itself supports password encryption and password protection

护。 Protection. 可编程只读存储器程序配置模块中,采用Flash可编程只读存储器电路在上电时自动对现场可编程门阵列硬件模块进行配置,配置方式有主控模式和被控模式两种。 Programmable read only memory module configuration program, programmable read-only memory circuit using Flash automatically field programmable gate array hardware modules configured when the configuration is powered and controlled manner with a master mode two modes.

多通道高速数据处理器的高速数据处理方法是:软件系统模块中,首先由高 Multi-channel high-speed data processing method of high speed data processors are: software module, the first by high

速数据处理器发出读写信息和数据信息,队列调度模块从网络处理器获取读写信息及数据信息,接收数据缓存模块从队列调度模块获取相应的写命令后,对接收数据缓存模块的缓冲区进行相应的写操作,以便于高速数据链路控制协议数据包反转义及其标志字处理模的处理,处理后的控制信号有效帧信号、转义信号及高速数据处理器输出数据一并传入帧校验序列模块,经校验后产生控制信号写缓冲信号、帧尾信号、校验错误信号及校验后数据,传入发送数据缓存模块,发送数据缓存模块综合处理判断后将校验后数据数据写入发送数据缓存模块的缓冲区, 结合队列调度模块的读信息,通过对该缓冲区的读操作将处理后的数据输出。 After the processor issues a data write speed and data information, read and write queue scheduling module obtains information and data information from a network processor, the receive data buffer module acquires the corresponding write command from the queue scheduling module, receiving data buffer of the buffer module write operation corresponding to packet processing and inversion flag word sense die in high-speed data link control protocol, a control signal is valid after the frame signal processing, and high-speed data processor escaping signals together with the output data transfer the frame check sequence module, a write buffer signal generates a control signal, frame signal, a parity error signal, and after checking the data after verification, the incoming transmission data buffer module, the transmission data buffer is determined after integration processing module check after the data written to the buffer the transmission data buffer module outputs the combined data queue scheduling module reads the information, the buffer is read by the processing. 软件系统模块对每个通道的数据进行帧头搜索、循环冗余码校验、反转义、丢弃序列的检测、帧长的监测以及帧尾的搜索, 一旦检测到某一帧当前传输的信息位数达到最大帧长或检测到丢弃序列时,软件系统模块中的状态机对当前帧的处理结束,并重新对新的一帧进行帧头搜索,而当前帧中的剩余数据将不被处理。 Software module search data header of each channel, cyclic redundancy check, unescapes, monitoring, and discard the search sequence detection, the frame length of the frame end information upon detection of a frame currently transmitted when the frame length or the maximum number of bits abort sequence is detected, the software modules in the system state machine processing of the current frame is completed, and a new re-search for the header, and the remaining data of the current frame will not be processed . 软件 software

系统模块同时处理高达128通道并行传输的高速数据链路控制协议数据流,它的实现是采用时分复用的方式,其中通道状态存储器用于实现时分复用,每一个通道在该通道状态存储器之中都有一块固定的存储空间,用以存储该通道的数据处理情况,即通道状态信息,为每一个通道每一段需要被处理的数据分配一段长度一定的时间片,每个时间片结束时,当前通道最新的状态信息将被存入通道状态存储器中的相应存储空间,当新的一段数据到达时,此段数据所属的通道在上一个时间片内被刷新的状态信息将从通道状态存储器中读出并加载到状态机中,为新一轮的数据处理做准备。 The system module also handle up to 128 channels of the parallel transmission of high speed data link control protocol data stream, its implementation is to use time division multiplexing manner, wherein the channel state memory used to implement time division multiplexing, each channel in the channel state memory, in both a fixed storage space for storing the data handling of the channel, i.e., channel status information, the data length of a certain time period allocated for each slice channel of each segment to be processed, the end of each time slice, most current channel status information to be stored in a respective memory space in the channel status memory, when a new piece of data arrives, the data channel this section belongs is refreshed in a time slice channel state information from the state memory read out and loaded into the state machine in preparation for a new round of data processing.

有益效果:本发明多通道高速数据处理设备达到了良好功能特性:实现了 Advantages: high-speed multi-channel data processing apparatus according to the present invention is to achieve a good features: realized

RFC1662规定的高速数据链路控制协议功能,实现了标志字检测、转义/反转义、 帧效验序列(FCS)功能,同时具有可扩展性和灵活性的特点,方便以后的升级扩展;本发明设备还通过增加接收和发送模块实现多通道并行处理高速数据链路控制协议数据,提高了处理器的效率;通过把4倍数据速率接口的地址总线作为控制信号利用,实现了总线复用,提高了总线利用率。 RFC1662 predetermined high speed data link control protocol function to achieve the detection flag word, an escape / unescape, efficacy frame sequence (FCS), also has scalability and flexibility features to facilitate future upgrades extension; present invention further parallel processing apparatus for receiving and transmitting modules to increase multi-channel high-speed data link control protocol data, improve the efficiency of the processor; 4 through the address bus the data rate as a control signal using the interface to achieve the multiplexed bus, improves bus utilization. 本发明主要是基于移动互联网内容监管设备中高速数据链路控制协议数据包的高速数据处理的现场可编程门阵列实现。 The present invention is mainly based on live high-speed data processing apparatus of the mobile Internet content regulation speed data link control protocol packets programmable gate array. 本发明在硬件实现方面提出了新的设计结构和实现方法;在功能上实现了高速数据链路控制协议帧的转义/反转义、循环冗余码校验功能、帧头帧尾的搜索及其去除,尤其关键的是通过与主机的通信, 实现了多个用户同时在线时端对端协议包的处理,并达到了200Mbps的高速处理能力。 The present invention proposes a new hardware implementation design structure and implementation; escape realized high-speed data link control protocol frames / unescapes functionally, cyclic redundancy check functions, end of frame header search its removal is especially critical online processing while communicating with the host computer, enabling multiple users to-point protocol packets and achieve high-speed processing capacity of 200Mbps. 在功能上实现了移动互联网内容监管系统中端对端协议包的高速处理。 In function enables high-speed mobile Internet content processing system regulatory point protocol packets.

附图说明 BRIEF DESCRIPTION

图1基于现场可编程门列阵的多通道高速数据处理设备结构框图; 图2 4倍数据速率接口模块2示意图; 1 a block diagram of processing apparatus based on a multichannel high-speed data in a field programmable gate array; FIG. 24 data rate interface module 2 a schematic view;

图3 Flash可编程只读存储器电路3. 2与现场可编程门阵列硬件模块1连接图; FIG 3 Flash Programmable Read Only Memory circuit according field programmable gate array 2 and the hardware modules are connected in FIG. 1;

图4可编程只读存储器程序配置模块3配置流程图; 4 programmable read only memory module configuration flow chart Configuration 3;

图5软件模块连接图; FIG 5 FIG software module connector;

图6本发明设备的软件状态图; The software 6 is a state diagram of the inventive apparatus;

图7单通道高速数据处理器状态转移图。 7 a single channel high-speed data processor a state transition diagram.

以上的图中有:现场可编程门阵列硬件模块1, 4倍数据速率接口模块2,可 The above figures are: Field Programmable Gate Array hardware module 1, four times the data rate interface module 2,

编程只读存储器程序配置模块3和软件系统模块4;内部集成电路总线接口2.1、 4倍数据速率接口2.2、 JTAG调试接口2.3、外围供电模块2.4;内部集成电路总线可编程只读存储器电路3.1和Flash可编程只读存储器电路3. 2;队列调度模块4.1,接收数据缓存模块4.2、发送数据缓存模块4.3、高速数据链路控制协议数据包反转义及其标志字处理模4. 4、帧效验序列模块4. 5。 Programmable Read Only Memory Configuration module 3 and 4 software modules; C bus interfaces 2.1, 4 times the data rate interface 2.2, JTAG debug interface 2.3, 2.4 peripheral power supply module; C bus and programmable read only memory circuit 3.1 Flash programmable Read Only memory circuit 3.2; 4.1 queue scheduling module, receiving data buffer module 4.2, 4.3 transmission data buffer module, a high speed data link control protocol packets and flag word mold unescapes 4.4, frame efficacy sequence module 4.5.

具体实施方式 detailed description

以下结合附图,对本发明设备各个模块的结构和流程进行详细说明。 Conjunction with the drawings, structures and processes of the present invention, the device module described in detail. 本发明设备是一种基于现场可编程门阵列的多通道高速数据处理设备。 The present invention is an apparatus based on the multi-channel high-speed field programmable gate array data processing apparatus. 如图l所示本发明的系统架构可知,该处理器具体包括以下的四个模块:现场可编程门阵列硬件模块l; 4倍数据速率接口模块2;可编程只读存储器程序配置模块3和软件系统模块4;所述4倍数据速率接口模块2包括:内部集成电路总线接 System architecture shown in Figure l of the present invention found that, the processor comprises the following four modules: Field Programmable Gate Array module hardware l; data rate interface module. 4 2; programmable read only memory program and configuration module 3 software module 4; 4 times the data rate of the interface modules 2 comprises: an internal bus interface IC

口2.1、 4倍数据速率接口2.2、 JTAG接口2.3和外围供电模块2.4;现场可编程门 2.1 mouth, four times the data rate interface 2.2, JTAG interface to the peripheral power supply module 2.3 and 2.4; Field Programmable Gate

阵列硬件模块1通过4倍数据速率接口2. 2连接外部的主机、通过电源线与外围供电模块2. 4连接以及通过JTAG接口2. 3与可编程只读存储器程序配置模块3中的Flash可编程只读存储器电路3. 2相接,Flash可编程只读存储器电路3. 2还通过JTAG接口2. 3与外部的PC机相接;可编程只读存储器程序配置模块3中的内部集成电路总线可编程只读存储器电路3. 1通过内部集成电路总线接口2. 1连接外部的主机;软件系统模块4,包括了:队列调度模块4.1、接收数据缓存模块4.2、发送数据缓存模块4. 3、高速数据链路控制协议数据包反转义及其标志字处理模4. 4和帧校验序列模块4. 5,软件系统模块4包括的各模块之间通过信号传递连接在一起; 软件系统模块4驻留在可编程只读存储器程序配置模块3中,多通道高速数据处理器工作后,程序被加载到现场可编程门阵列硬件模块l中,而现场 1 through 4 array hardware module data rate 2.2 connection to an external host interface, 2.4, and 2.3 is connected with a programmable read only memory program module configuration 3 Flash through JTAG interface via the peripheral power supply line and the power supply module programmable read only memory circuit contact 3.2, Flash programmable read only memory circuit further 2.3 3.2 contact with the external PC through the JTAG interface; program programmable read only memory integrated circuit disposed within the module 3 bus programmable read only memory integrated circuit of an internal circuit 3.1 via host interface connected to an external 2.1; software module 4, includes: a queue scheduling module 4.1, the receive data buffer module 4.2, the transmission data buffer module 4.3 , high-speed data link control protocol packets and flag word unescapes mold and a frame check sequence 4.4 4.5 modules, software modules connected between each module 4 comprises a signal transmitted by; software system module 4 resides in a programmable read only memory program modules 3 arranged in the multi-channel high-speed data processor is operating, the program is loaded into the field programmable gate array of hardware modules l, while the field 编程门阵列硬件模块1通过4倍数据速率接口模块2与主机的程序连接在一起。 Programmable gate array of hardware modules 12 are connected together by a host program interface module four times the data rate.

本发明处理器采用200万门Spartan3 XC3S2000现场可编程门阵列。 The present invention is processor 2,000,000 Spartan3 XC3S2000 field programmable gate array. 现场可编程门阵列达到200Mbps的处理速度,接入接口部分与主机之间采用标准内部集成电路方式完成信号连接和时序匹配过程;采用数字控制阻抗匹配(DCI)技术在现场可编程门阵列内部实现的1/0信号线短接;2M系统门结构、320K分布式RAM、 720K Block RAM、 40个专用乘法器、4组数字时钟管理结构(DCM)可以对外提供4个不同的时钟信号、最高可达565个用户1/0最高可达270对差分信号对、支持18种单行I/0标准和8种差分I/0标准。 Field Programmable Gate Array achieve processing speed of 200Mbps, standard inter-integrated circuit manner between the access completion signal to the host interface portion connected to the timing and matching process; digitally controlled impedance (DCI) technology implemented in a field programmable gate array inside 1/0 shorted signal lines; gate structure 2M system, distributed 320K RAM, 720K Block RAM, 40 dedicated multipliers, digital clock management structure group 4 (DCM) can provide external clock signals of four different maximum 1/0 up to 565 up to 270 pairs of user differential signal pair support for 18 one-way I / 0 and 8 standard differential I / 0 standard. 本系统的设计中,采用LA—14倍数据速率接口模块2连接主机和本发明设备,为本发明设备提供与主机之间的通信和数据交互。 Design of the system, the use of LA-14 data rate interface module connected to the host 2 and the device of the present invention, the communication and data exchange between the devices of the present invention to a host. 此外,本发明设备的所有供电都由该接口提供。 Further, all the power supply device by the present invention, the interface provides. 内部集成电路总线接口2.1通过内部集成电路总线访问卡上的I2C E2PR0M来获取本发明设备的识别符、 工作电平和温度等设备信息,从而识别本发明设备。 2.1 Inter-IC bus interface acquires the identifier of the device according to the present invention, the working temperature level equipment information on the inter-integrated circuit I2C E2PR0M bus access card, to identify the device of the present invention. 4倍数据速率接口2.2的16 位数据接口在双时钟驱动下倍频成为逻辑32位,它运用LA一1协议,在实际运用中选择和定制的空间较大;JTAG调试接口2.3仅限于提供测试接口(不支持对可编程只读存储器和现场可编程门阵列的烧写),所以在设计中另外引入了JTAG插槽,通过PC机直接下载程序到可编程只读存储器;外围供电模块2.4在生成2.5V 电压时,我们采用了TI的TPS75525电压转换芯片,5Pin TO-263(KTT)封装;在生成1. 2v电压时,我们采用了TI的TPS54312电压转换芯片,20Pin PWP封装; 在生成0.75V电压时,我们采用MAX1589EZTAFJ, TDFN封装;采用内部集成电路总线可编程只读存储器电路3. 1记录本发明设备信息,包括设备识别符、工作电平和温度等参数。 4 Data Rate Interface 16 2.2 Interface data at double the clock frequency driving becomes logic 32, it uses a 1 LA protocol, select and customize larger space in practical use; the JTAG debug interface is limited to 2.3 to provide test interface (no programming the programmable read-only memory and the field programmable gate array), so the design is additionally introduced JTAG slot, the PC by a direct download to the programmable read-only memory; peripheral power supply module 2.4 generating a voltage of 2.5V, we used the TI TPS75525 voltage converter chip, 5Pin tO-263 (KTT) package; 1. 2v when generating the voltage, we used the TI TPS54312 voltage converter chip, 20Pin PWP package; generated 0.75 when the voltage V, we use MAX1589EZTAFJ, TDFN package; C bus using programmable read only memory circuit according to the information recording apparatus of the present invention, includes a device identifier, a work level and temperature and other parameters. 此外,内部集成电路总线可编程只读存储器电路3. 1本身还支持口令加密和密码保护;采用Flash可编程只读存储器电路3. 2在上电时自动对现场可编程门阵列进行配置,有主控模式和被控模式两种。 Further, the C bus programmable read only memory circuit 3.1 also supports itself password encryption and password protection; Flash Programmable Read Only Memory circuit using 3.2 to automatically configure the field programmable gate array during power-up, there master and charged with two modes.

与本发明设备相关联的外部设备主要有主机和PC。 External device associated with the apparatus according to the present invention, mainly the host and the PC. 本发明设备通过一个114管脚的插座连接主机,接口信号遵循LA一1协议,此外本发明设备的供电也通过该插座引入。 The present invention is connected to a host device, the interface signal through a 114-pin receptacle 1 follows a protocol LA, furthermore the power supply apparatus of the present invention is also introduced through the socket. 与外部计算机之间的连接主要通过JTAG接口,通过该接口调试和烧写现场可编程门阵列以及可编程只读存储器。 The connection between the main computer and the external JTAG interface, programmable gate arrays, and programmable read-only memory through the interface debugging and programming field. 在对现场可编程门阵列的访问中,JTAG 模式享有最高优先级。 Access to field-programmable gate array, JTAG mode has the highest priority.

在我们的发明设备上还设计了针对现场可编程门阵列的硬件复位和软件复位端口,硬件复位通过对现场可编程门阵列PR0G_B管脚置位来清除配置存储区内存,然后可通过JTAG模式重新烧写或可编程只读存储器重新进行自动配置。 In the apparatus of our invention is also designed for a field programmable gate array, hardware reset and software reset port, a hardware reset by field programmable gate array PR0G_B pins to clear set memory configuration memory, and then re-mode through JTAG programming programmable read only memory, or re-configured automatically. 软件复位端口主要用于程序的复位和调试,其功能可由用户自行定义。 Software reset and the reset port is mainly used for debugging, which functions can be user defined.

现场可编程门阵列的工作时钟由40MHZ板载晶振提供,也可以采用114插槽提供的200MHz 4倍数据速率接口时钟,以上两种时钟都由全局时钟端口引入,在现场可编程门阵列内部通过数字时钟管理结构模块进行分频和倍频生成系统时钟。 Field programmable gate arrays operating clock of 40MHZ provided by the on-board oscillator, 200MHz 4 times the data rate interface clock 114 may be used to provide slots, two or more clock ports incorporated by global clock, internal field programmable gate array by digital clock management module dividing structure and generates a system clock frequency.

以下对各个模块进行展开说明。 The following description of each module expansion.

1、现场可编程门阵列硬件模块l 1, a field programmable gate array, hardware modules l

(1)现场可编程门阵列硬件模块1的配置模式 (1) field programmable gate array hardware module configuration mode 1

我们釆用的Spartan现场可编程门阵列兼容多种配置模式,各配置模式的选择通过拨码开关对模式管脚髙低电平的设置来实现的。 We Spartan preclude the use of field programmable gate array compatible with various configuration modes, each of the selected arrangement pattern achieved by the DIP switch settings for the mode pins Gao low. 不同模式对应的管脚电平配置见下表h Pin level modes corresponding to different configurations shown below h

<table>table see original document page 11</column></row> <table> 表h各模式对应的MODE管脚配置 <Table> table see original document page 11 </ column> </ row> <table> h table for each mode MODE pin configuration

说明:JTAG模式不受模式选择的制约而始终可用,为其分配选择模式只是为了防止在配置过程中同其他的配置方式发生冲突。 Description: JTAG mode is not restricted mode selection and always available, select the mode assigned only to prevent conflicts with other configurations in the configuration process. 现场可编程门阵列硬件模块1的系统资源 Field Programmable Gate Array module system hardware resource 1

在单板设计中,我们采用了Xilinx公司的Spartan3XC3S2000现场可编程门阵列,其主要硬件参数如下: 2M系统门结构; In the board design, we used Spartan3XC3S2000 company Xilinx field programmable gate array, hardware main parameters are as follows: 2M system a door structure;

320K分布式RAM、 720K Block RAM; 40个专用乘法器: Distributed 320K RAM, 720K Block RAM; 40 dedicated multipliers:

4组数字时钟管理结构,可以对外提供4个不同的时钟信号; Group 4 digital clock management structure, may be provided outside four different clock signals;

最高可达565个用户I/O; Up to 565 user I / O;

最高可达270对差分信号对; Up to 270 pairs of differential signal pairs;

支持18种单行I/O标准和8种差分I/O标准。 Single-line support for 18 I / O standards and eight differential I / O standards.

现场可编程门阵列的I/O分为8个Bank,每个Bank的I/O输出供电相对独立, 原则上能同时支持8种不同的I/O标准。 A field programmable gate array I / O is divided into eight Bank, Bank of each I / O output power relatively independent, in principle, can support eight different I / O standards.

(2)现场可编程门阵列硬件模块1的供电说明 (2) field programmable gate array of hardware modules of a power supply described

现场可编程门阵列的供电主要分为以下几个部分:现场可编程门阵列核心供 Power field programmable gate array is divided into the following sections: a field programmable gate array core for

电V。 Electric V. . W现场可编程门阵列辅助供电V。 W Field Programmable Gate Array auxiliary power supply V. ,,;输出驱动电平^。 ,,; ^ output drive level. ;输入参考电平Vw。 ; An input reference level Vw.

其中,有的电压如Vccint和Vccaux相对固定,其他的电压随与之对应的Bank 所采用的I/0标准而变化。 Wherein some of the voltage and Vccaux Vccint such relatively fixed, with the other voltage corresponding thereto Bank employed I / 0 standard changes. 在上电是,各电平必须满足相应的要求。 On the power that each level must satisfy the corresponding requirements. 在本设计中, Bankl到Bank3由于采用了与4倍数据速率接口一致的HSTL_I标准,所以在这些Bank中必须采用1. 5Vcco和0. 75V Vref 。 In this design, the Bankl Bank3 A consensus with four times the data rate interface HSTL_I standard, and it must be 0. 75V Vref 1. 5Vcco Bank of these.

在本设计中,Bankl到Bank3由于采用了与4倍数据速率接口一致的HSTL一I 标准,所以在这些Bank中必须采用1. 5Vcco和0. 75V Vref。 In this design, the Bankl Bank3 A consensus with four times the data rate interface HSTL-I standard, and must be 0. 75V Vref 1. 5Vcco Bank of these. 详细的电平配置如下表所示: Detailed level configuration shown in the following table:

<table>table see original document page 12</column></row> <table> <Table> table see original document page 12 </ column> </ row> <table>

表2: 现场可编程门阵列输入电平列表 Table 2: Field Programmable Gate Array input level listing

数字控制阻抗匹配技术是在现场可编程门阵列内部实现的1/0信号线端接, 对于不同的1/0标准往往有不同的实现方法,主要通过向现场可编程门阵列各Bank 的VRN和VRP管脚提供上拉或者下拉的参考电阻,现场可编程门阵列根据各Bank 对应的端接方式和提供的特征阻抗值向各1/0管脚提供数字控制阻抗匹配。 1/0 digital control signal line impedance matching technology is terminated inside a field programmable gate array, often have different implementations for different standards of 1/0, the VRN primarily by field programmable gate array and each Bank VRP pull or pull-down pin provides a reference resistor, a field programmable gate array provides a digital control in accordance with the respective impedance matching termination Bank and features corresponding to the resistance value provided by each 1/0 pins.

在本设计中,主要针对HSTL—I标准配置数字控制阻抗匹配,HSTL一I标准在作为信号输出时不启动端接,在作为信号输入时启用端接,而且是包含上拉和下拉参考电阻的双端接形式。 In this design, mainly for HSTL-I standard digitally controlled impedance, HSTL standard is not a start I as terminated when the signal output as the enable signal input end, and comprising a reference resistor pullup and pulldown doubly terminated form.

现场可编程门阵列硬件模块1的电路上还包括直流1. 2V为现场可编程门阵列模块供电、2. 5V外围供电和O. 75V参考电压三个外围直流电压转换电路以及40附lz 全局时钟信号发生单元和重置开关电路等几个外围电路。 A field programmable gate array circuit further comprises a hardware module 1. 2V DC power supply for field programmable gate array module, 2. 5V power supply and the peripheral reference voltage three peripheral O. 75V DC voltage converter circuit and a global clock 40 is attached lz several peripheral circuit unit, and a reset switch signal generating circuit. 其中,40MHz晶振为现场可编程门阵列提供全局时钟,并且可以通过现场可编程门阵列内部数字时钟管理结构模块实现频率转换。 Wherein, for the 40MHz clock oscillator providing a global field programmable gate array, and the frequency conversion can be realized by a field programmable gate array internal digital clock management module structure. 在现场可编程门阵列受控模式中,为可编程只读存储器提供配置时钟信号。 Field Programmable Gate Array controlled mode, configured to provide a clock signal as a programmable read only memory. 内部集成电路可编程只读存储器与4倍数据速率接口以内部集成电路进行通信,主机以此获得该设备参数。 Inside the integrated circuit programmable read only memory and four times the data rate interface internal to the integrated circuit for communication, the host device in order to obtain this parameter. 2、 4倍数据速率接口模块2 2, four times the data rate interface module 2

4倍数据速率接口模块2为现场可编程门阵列与主机之间的逻辑接口现场可编程门阵列硬件模块1主要对来自主机的多路高速数据链路控制协议帧进行并行的高速数据链路控制协议解封装和端对端协议包反转义,最后将结果反馈主机进行下一步的重组和协议处理。 4 Data Rate Interface Module Field 2 is the logical interface between the host and the field programmable gate array programmable gate array, hardware module 1 mainly multiple high-speed data link control protocol frames from the host parallel high-speed data link control a PPP protocol packet decapsulation and reverse sense, the final result back to the next step of the recombinant host and protocol processing.

(1) 接口操作综述 (1) Summary of Operation Interface

4倍数据速率接口模块2遵循以下几条原则- 4 Data Rate Interface module 2 following the following principles -

>控制信号总是在K时钟上升沿锁存; > Control signal K is always latched on the rising edge of the clock;

>地址和数据信号在K时钟的上升、下降沿读取; > Address and data signals K rising edge, falling edge read;

>进程中的读写数据操作均不能被中断或者重新开始。 > Read and write data manipulation process not be interrupted or restarted.

(2) 4倚数据速率接口模块2的数据传输结构及其操作时序数据写入结构:字写入信号有BWltt和BWO弁两个控制信号,分别控制数据输 (2) a data rate of 4 leaning data transfer interface module structure 2 and the data write operation timing structure: BWltt word write signal has two control signals and BWO Bian, the control data are input

入管脚的高8位(D[15:8])和低8位(D[7:0]),与之相对应的校验位是DPI和DPO。 Pin into the upper 8 bits (D [15: 8]) and the lower 8 bits (D [7: 0]), a parity bit corresponding thereto is DPI and DPO. 一个写周期由检测到K上升沿时Wft为低电平开始。 Wft a write cycle begins detecting the rising edge K is low. 写周期的地址在随后的W上升沿由A提供。 Write cycle address provided by A rising edge of the subsequent W. 在同一个周期内,写入数据在K以及Ktt的上升沿获得。 In the same cycle, the rising edge of the write data in the K and Ktt. 具体数据写入时序为:在K的上升沿,BW1控制的高8位(D[15:8])写入字节0 Bits[31:24], BWO控制的低8位(D[7:0])写入字节1 Bits[23:16];在K糊上升沿,BW1控制的髙8位(D[15:8])写入字节2 Bits[15:8], BWO控制的低8位(D[7:0])写入字节O Bits[7:0]。 Specific data write sequence is: the rising edge of K, BW1 control of the upper 8 bits (D [15: 8]) write byte 0 Bits [31:24], BWO control of the lower 8 bits (D [7: 0]) write byte 1 Bits [23:16]; paste at the rising edge of K, BW1 control Gao 8 (D [15: 8]) write byte 2 Bits [15: 8], BWO control The lower 8 bits (D [7: 0]) write byte O Bits [7: 0].

数据输出结构:数据输出结构与数据写入结构相对应,一个读周期由检测到K 上升沿时RS为低电平开始。 Data output structure: Data output structure corresponding to the structure of data written, a read cycle starting from low RS detecting the rising edge K. 与此同时,读操作的地址在A上读入。 At the same time, the read address of the read operation on A. 数据在下一个K上升沿以后以C和Cft为参考时钟输出。 K data after the next rising edge in the reference clock C and output Cft. (3) 输出寄存器控制(从设备属性) 4倍数据速率接口模块2为寄存输出数据提供两种机制。 (3) the data output register output control register provides two mechanisms (slave property) data rate interface module 4 2. 一般地,控制节拍山C和Cft这对差分输入时钟提供,它们通过微小的相位偏移,允许用户的数据输出在随后的K和Kft时钟信号的基础上有几纳秒的延迟。 Generally, the control rhythm and Hill C Cft which provide differential input clock, are offset by a slight phase, it allows the user to have the output data on the basis of a few nanoseconds of delay subsequent clock signal K and on Kft. 从而使设备以类似传统流水线读设备的方式来工作。 So that the device in a similar manner as a conventional pipelined reading apparatus to work. 基于字节写入控制信号的Burstl和Burst2为可选模式; 在读操作中提供给主机的Echo Clock信号CQ、 CQ#:产生输出校验位。 Byte-write control signal and Burst2 Burstl optional mode; providing CQ Echo Clock signal to the host in a read operation, CQ #: generating an output parity bit. (4) 本发明的LA—l协议运用LA」协议为4倍数据速率接口的运用提供了一个参考方案,在实际运用中选择和定制的空间较大。 (4) LA-l protocol of the present invention is the use of LA "protocol data rate using 4 provides a reference interface for the program, and select the custom in practical use larger space. 在本发明从属设备的设计中,由于内存调度的相对独立性, 地址信号仅起到了片选设备的作用,并不存在与实际内存空间的一一映射。 In the design of the slave device of the present invention, due to the relative independence of the scheduled memory, the address signal only acts chip select device, there is no real memory space with one mapping. 然而, 基于设备的通用性,接口程序的设计还必须包括:*基于字节写入控制信号的Burstl和Burst2可选模式拳在读操作中提供给主机的Echo Clock信号CQ、 CQtt*产生输出校验位(5) 接口供电模块详细设计该设备的主供电来自Mictor 114插口提供的三路直流电源,电压值分别为: 3. 3V、 1. 5V、 1. 8V。 However, design versatility, the device-based interface program must further comprising: providing * CQ Echo Clock signal to the host in a read operation on a byte and a write control signal Burstl Burst2 punches selectable modes, CQtt * generating an output checksum bit (5) the detailed design of the interface power supply module of the apparatus main power supply DC power from the three-way socket provided Mictor 114, voltage values ​​were: 3. 3V, 1. 5V, 1. 8V. 此外,为了驱动Spartan现场可编程门阵列,同时为1至3Bank 提供HSTLj参考电平,还要在卡上利用电压控制芯片本地生成1. 2V、 2. 5V、 0. 75V 电平。 Further, in order to drive Spartan field programmable gate arrays, while providing the reference level HSTLj 1 to 3Bank, generating 1. 2V, 2. 5V, 0. 75V by the voltage level but also to the local control chip on the card. 其中,1.2V为现场可编程门阵列内核供电,2.5V为现场可编程门阵列辅助供电和4至7Bank以及0Bank I/O供电,0. 75V为1至3Bank参考电平。 Wherein, 1.2V is a field programmable gate array core power, 2.5V is a field programmable gate array 4 and the auxiliary power supply and to 7Bank 0Bank I / O power supply, 0. 75V 3Bank 1 to a reference level. 在产生本地电平时,3. 3V生成1.2V和2.5V, 1.8V生成0. 75V。 Generating a local level, 3. 3V and generates 1.2V 2.5V, 1.8V generated 0. 75V. TPS75525 3.3/2.5V电压转换芯片在生成2.5V电压时,我们采用了TI的TPS75525电压转换芯片,5PinT0"263(KTT)封装。其中管脚1 ( EW )为输入使能, 管脚2 (W)为输入电平,管脚3 (GJW?)为地,管脚4 (OC/5TUT)为输出电平,管脚5 (i^/?5)为输入反饿/特定模式下^输出。TPS54312 3.3/1.2V电压转换芯片在生成1.2V电压时,我们采用了TI的TPS54312电压转换芯片,20PinPWP封装。其中管脚l(AGND)模拟地,管脚5(B00T) 保留,管脚19 (FSEL)为频率输入选择,管脚3 (NC)无连接;管脚11 — 13 (PGND) 为功率地,管脚6—10 (PH)为相位输入/输出,管脚4 (PWRGD)为Power Good指示,管脚20 (RT)频率设置电阻输入,管脚18 (SS/ENA)慢启动/输入使能/输出复用管脚,管脚17 (VBIAS)内部偏置输出控制,管脚14一16 (VIN)输入电平, 管脚(VSENSE)误差反馈放大输入。MAX1589 1. 8/0. 75V电压转换芯片通过Mictor 114插口提供的1. 8V电源驱动, 输出0. 75V TPS75525 3.3 / 2.5V voltage conversion to generate a voltage of 2.5V at the chip, we used the TI TPS75525 voltage converter chip, 5PinT0 "263 (KTT) package. Wherein pin 1 (EW) to enable input, pin 2 (W ) is the input level, pin 3 (GJW?) is, the pin 4 (OC / 5TUT) output level, pin 5 (i ^ /? 5) anti-hungry input / output ^ specific pattern. TPS54312 3.3 / 1.2V voltage conversion chip voltage generating 1.2V, we used the TI TPS54312 voltage converter chip, 20PinPWP package where pins l (AGND) analog ground, pin 5 (B00T) reservations, pin 19 ( the FSEL) for the frequency selection input, pin 3 (NC) no connection; pin 11 - 13 (PGND) of the power, the pins 6-10 (PH) is a phase of an input / output pin 4 (PWRGD) of power Good indication, pin 20 (RT) frequency setting resistor input pin 18 (SS / ENA) slow start / enable input / output pin multiplexing, the pin 17 (VBIAS) internal bias output control pin 14 a 16 (VIN) input level pin (the VSENSE) amplifying an error feedback input .MAX1589 1. 8/0. 75V voltage converter chip 1. 8V power by providing a driving socket Mictor 114 outputs 0. 75V HSTL一I参考电平,完整的芯片部件标号为MAX1589EZTAFJ,采用标准TDFN封装。其中管脚6 ( ^ )为电源输入,管脚4 ( GM))为地,管脚5 ( S層)用于关闭信号,低电平有效,管脚3 为重启信号,低电平有效,管脚2(/•C)为内部连接,置空或接地,管脚l (OC/T)为电压输出,中部焊盘EP为地。3、可编程只读存储器程序配置模块3Flash可编程只读存储器电路3.2在上电时自动对现场可编程门阵列有两种配置模式:主控模式和被控模式,其主要区别在于配置时钟信号源的不同。在现场可编程门阵列主控模式中,现场可编程门阵列为可编程只读存储器提供配置时钟信号,在现场可编程门阵列受控模式中,由外部晶振提供配置时钟信号。在设计'中,可以通过调节现场可编程门阵列配置模式选择开关来切换主从两种模式。默.认方式为现场可编程门阵列主控模式,我们通过设置Xilinx Bi I HSTL a reference level, the complete chip part designated MAX1589EZTAFJ, standard TDFN package where pins 6 (^) is a power supply input, pin 4 (GM)) is, the pin 5 (S layer) for off signal, active low, pin 3 of the restart signal, active low, pin 2 (/ • C) for the internal connector, blanking or ground, pin l (OC / T) voltage output, the central EP .3 ground pad, programmable read only memory program module configured 3Flash 3.2 automatic programmable read only memory circuit, there are two configuration modes for field programmable gate array at power: master mode and controlled mode, which the main difference is the configuration of the clock source in the master mode field programmable gate array, a field programmable gate array configured to provide a clock signal as a programmable read only memory, field programmable gate arrays in mode controlled by an external crystal configuration provides a clock signal in the design ', the switch can be selected by adjusting the mode field programmable gate array configured to switch from the master mode. Mo. embodiment is considered master mode field programmable gate array, we provided by Xilinx Bi tGeri软件中速率配置选项来调节可编程只读存储器配置速率。图3为现场可编程门阵列主控模式下现场可编程门阵列硬件模块1与Flash可编程只读存储器模块3. 2的连接图。现场可编程门阵列通过与FLASH可编程只读存储器之间的串行接口接受配置讀息,此外,还可以通过JTAG接口直接对现场可编程门阵列进行配置和DEBUG。 tGeri software configuration options rate programmable read only memory configured to adjust the rate. FIG. 3 is a Field Programmable Gate Array the master mode field programmable gate array, hardware module and a Flash Programmable Read Only Memory module connector of FIG. 3.2 the field programmable gate array configured to accept the read information through the interface between the serial FLASH programmable read only memory and, in addition, also possible to configure the field programmable gate array, and DEBUG directly through the JTAG interface. 上电后,现场可编程门阵列自行向可编程只读存储器中读取数据,在工作状态时还可以通过重置信号进行重新配置。 After power, field programmable gate arrays themselves read data to a programmable read-only memory can be reconfigured in the operating state by a reset signal Shihai. 图4为可编程只读存储器程序配置模块3配置流程图,首先由系统上电,若电源满足供电条件,即Vccin〉lV, Vccaux〉2V, VccoBank4MV三个条件同时满足' 则淸除配置存储区内存,然后判断引脚INT—B是否为高电平,若为高电平,则自动检测配置模式管脚,然后按照对应模式下载配置信息,若CRC校验后无误,则配置完毕,进入用户模式。 FIG 4 is a flowchart of the configuration module 3 configured programmable read only memory program, first by the system power supply when the power supply to satisfy the condition, i.e. Vccin> lV, Vccaux> 2V, VccoBank4MV three conditions are met 'except the configuration memory Qing memory, and then determines whether the pin INT-B is high, if high, the pin configuration mode to automatically detect and download the configuration information in a corresponding mode, when the CRC checks after the configuration is completed, the user enters mode. 若在用户模式下需要重新配置现场可编程门阵列,则将PROG一B管脚电平置低。 If the need to reconfigure the FPGA in user mode, then the PROG B a low level of the set pins. 若在配置过程中,检测到PROG一B引脚为低电平,则清除配置存储区内存,进入新的配置流程;若在初次配置完成后,检测到INTJ5引脚为低电平,则霈要重新进行CRC校验,检测配置信息。 If the configuration process, a B detected PROG pin is low, the memory is cleared configuration memory, the configuration of the new process; if after the initial configuration, the detected INTJ5 pin is low, then Pei to re-checking the CRC detection configurations. 4、本发明的软件模块4图5为软件模块间的连接图。 4, software module 5 of the present invention FIG 4 is a connection diagram between software modules. 各个模块间通过信号传递信息:首先由网络处理器发出读写信息和数据信息,队列调度模块4.1从网络处理器获取读写及其数据信息,接收模块4.2从队列调度模块4. 1获取相应的写命令后,对缓冲区进行相应的写操作,以便于高速数据链路控制协议数据包反转义及其标志字处理模4. 4 的处理,处理后的控制信号有效帧信号、转义信号及其处理器输出数据一并传入帧效验序列模块4.5,经校验后产生控制信号写缓冲信号,帧尾信号,效验错误信号及其效验后数据,传入发送数据缓存模块4.3,综合处理判断后将数据写入缓冲区,结合队列调度模块4.1的读信息,通过对该缓冲区的读操作将处理后的数据输出。 Between the various modules by transmitting information signals: issued by the first network processor to read and write information and data information, queue scheduling module 4.1 and acquires read data information from a network processor, the receiving module to obtain the corresponding 4.2 from the queue scheduling module 4.1 after the write command to the buffer write operation corresponding to high-speed data link control protocol packets and unescapes flag word processing mode 4.4, the control signal is valid after the frame signal processing, the signal escapes and the processor outputs the data sequence together with the incoming frame efficacy module 4.5 generates the control signal after checking the write buffer signal, end of frame signal, the error signal and its efficacy efficacy data after incoming transmission data buffer module 4.3, the integrated treatment Analyzing the buffer after data is written, the information is read in conjunction with the queue scheduling module 4.1, the data output buffer is read by the processing. 软件系统模块4中,首先由网络处理器发出读写信息和数据信息,队列调度模块4.1从网络处理器获取读写及其数据信息,接收模块4. 2从队列调度模块4.1 获取相应的写命令后,对缓冲区进行相应的写操作,以便于高速数据链路控制协议数据包反转义及其标志字处理模4.4的处理,处理后的控制信号有效帧信号、 转义信号及其处理器输出数据一并传入帧效验序列模块4. 5,经校验后产生控制信号写缓冲信号,帧尾信号,效验错误信号及其效验后数据,传入发送数据缓存模块4.3,综合处理判断后将数据写入缓冲区,结合队列调度模块4. 1的读信息,通过对该缓沖区的读操作将处理后的数据输出。 The system software module 4, issued by the first network processor to read and write information and data information, queue scheduling module 4.1 and acquires read data information from a network processor receiving module 4.2 4.1 queue scheduling module acquired from the corresponding write command after the buffer corresponding to the write operation in order to process high-speed data link control protocol packets and flag word unescapes 4.4 mode, the control signal is valid after the frame signal processing, and signal processor escape after the output data sequence together with the incoming frame efficacy module 4.5 generates the control signal after checking the write buffer signal, end of frame signal, the error signal and its efficacy efficacy data after incoming transmission data buffer module 4.3, the integrated process is determined the data written to the buffer, the information is read in conjunction with the queue scheduling module 4.1, the data outputs of the buffer is read by the process. 软件系统模块4对每个通道的数据进行帧头搜索、循环冗余码校验、反转义、丢弃序列的检测、帧长的监测以及帧尾的搜索, 一旦检测到某一帧当前传输的信息位数达到最大帧长或检测到丢弃序列时,状态机对当前帧的处理结束,并重新对新的一帧进行帧头搜索,而当前帧中的剩余数据将不被处理。 4 software module search data header of each channel, cyclic redundancy check, unescapes discarded detected frame length and sequence monitoring frame end of search, upon detection of a frame currently transmitted when the maximum frame length information bits or abort sequence is detected, the state machine processing of the current frame is completed, and a new re-search for the header, and the remaining data of the current frame will not be processed. 软件系统模块4同时处理高达128通道并行传输的高速数据链路控制协议数据流,它的实现是采用时分复用的方式,其中通道状态存储器是实现时分复用的关键,每一个通道在该通道状态存储器之中都有一块固定的存储空间,用以存储该通道的数据处理情况,即通道状态信息,为每一个通道每一段霈要被处理的数据分配一段长度一定的时间片,每个时间片结束时,当前通道最新的状态信息将被存入通道状态存储器中的相应存储空间,当新的一段数据到达时,此段数据所属的通道在上一个时间片内被刷新的状态信息将从通遒状态存储器中读出并加载到状态机中,为新一轮的数据处理做准备。 4 software modules to handle up to 128 channels of high-speed transmission of parallel data link control protocol data stream, its implementation is to use time division multiplexing manner, wherein the channel state memory is the key to time division multiplexing, each channel in the channel a length of the data distribution in a certain time slot has a fixed state memory storage space for storing the data handling of the channel, i.e. the channel state information, for each channel of each segment to be processed Pei, each time at the end pieces, the most current status of the channel information is stored in a respective memory space in the channel status memory, when a new piece of data arrives, the data channel this section belongs is refreshed within a time slice from the state information Qiu through state memory is read out and loaded into the state machine in preparation for a new round of data processing. 图6为本设计的软件设计状态转移图。 6 is a schematic design software design state transition diagram. 本发明可以同时处理高达128通道并行传输的高速数据链路控制协议数据流,它的实现是采用时分复用的方式,核心部分由一个收发独立且可分时处理的髙速数据链路控制协议处理器和一个通道状态存储器构成。 The present invention can handle a high speed data link control protocol data stream of up to 128 parallel transmission channel, it is achieved using time division multiplexing manner, a core part of a transceiver and may be time-independent processing speed data link control protocol Gao The processor and memory constitute a state of the channel. 其中通道状态存储器是实现时分复用的关键,每一个通道在该通道状态存储器之中都有一块固定的存储空间,用以存储该通道的数据处理情况, 即通道状态信息。 Wherein the channel state memory is the key to time division multiplexing, each channel has a fixed in the channel state memory storage space for storing the data handling of the channel, i.e. the channel state information. 本发明为每一个通道每一段需要被处理的数据分配一段长度一定的时间片。 The present invention is a data distribution period of a certain length of time slices each channel of each segment to be processed. 每个时间片结束时,当前通道最新的状态信息(包括:处理结束时状态机所处的状态、对该通道己经处理过的数据的CRC校验码及其未残段数据的长度,当前时间片内已处理完但尚未来得及被输出的接收数据等)将被存入通道状态存储器中的相应存储空间。 At the end of each time slice, the latest current channel state information (including: the length of the CRC for the treated and data channel has not stub data state machine in which the end of the treatment, the current time slice has been processed but not yet had time to output reception data, etc.) to be stored in the respective storage channel status memory. 当新的一段数据到达时,此段数据所属的通道在上一1 个时间片内被刷新的状态信息将从通道状态存储器中读出并加载到状态机中,为新一轮的数据处理做准备。 When a new piece of data arrives, the data channel this segment belongs in a time slice on a refreshed state information from the channel state memory is read out and loaded into the state machine, to make a new data processing ready. 为了实现主机对每个通道的数据传输的监控功能,设计中,在空闲状态中加了一个分支状态,若主机(host)发现某个通道的数据传输有误或长时间未接收到该通道的数据,能且只能在该多通道的等待空闲状态査询该通道的状态信息,以确保不中断对其余通道数据的正常操作。 To achieve the monitoring host data transfer of each channel, design, add a branch state in the idle state, if the host (Host) found a channel data transmission time is incorrect or does not receive the channel data, and can only query the status information of the channel in the idle state waiting for the multiple channels to ensure uninterrupted operation of the remaining normal channel data. 我们在对现场可编程门阵列器件进行功能设计时釆用的是"Top to Doto"(" 从顶到底")的方法,亦即根据要求的功能先设计出顶层的原理框图,该图通常由若干个功能模块组成。 We preclude the use of the "Top to Doto" ( "From the top in the end") method, i.e., according to the functional requirements of the design at the top of the block diagram of a field programmable gate array device functional design, which usually consists of FIG. several functional modules. 再把各个模块细化为子模块,对较复杂的设计还可把各子模块分成一层层的下级子模块,各层的功能可以用硬件描述语言或电路图来实现。 Then subdivided into sub-modules of each module, it may also be of more complex design the submodules into a lower sub-layers of modules, the functions of layers may be implemented in a hardware description language or schematic. 图7为单通道高速数据处理器状态转移图。 FIG 7 is a single-channel high-speed data processor a state transition diagram. 对每个通道的数据进行帧头搜索、 CRC校验、反转义、丟弃序列的检测、帧长的监测以及帧尾的搜索。 Searching for the header, CRC checking, the sense data for each channel inversion discards detected frame length and sequence monitoring frame end of the search. 一旦检测到某一帧当前传输的信息位数达到嚴大帧长或检测到丢弃序列时,状态机对当前帧的处理结束,并重新对新的一帧进行帧头搜索,而当前帧中的剩余数据将不被处理。 Upon detection of information bits of a frame currently transmitted frame length reaches Yan large or abort sequence is detected, the state machine processing of the current frame is completed, and a new re-search for the header, and the remaining data in the current frame will not be processed. Sh缺省状态,进行帧头的搜索;S2:数据的处理,包括反转义,CRC的校验,丢弃序列的检测; S3:对CRC校验码和帧长进行判断,对状态位进行标识。 Sh default state, searching the frame header; S2: data processing, including unescape, CRC checksum, discarding detection sequence; S3: CRC, and frame length of the judgment, the identification of the status bits . 状态机开始工作时处于缺省状态Sl,进行帧头的搜索。 The state machine is in the default state Sl at the beginning of the work, searching the frame header. 结合状态寄存器中存储的数据,移位后,通过逻辑关系判断为(7E)后,状态机才认为己搜索到帧头, 并且立即跳入状态S2,进行数据的处理,包括反转义,丢弃序列的检测。 Binding data stored in the status register, after the shift is determined (7E) through the logic, a state machine that has only to search for the header, and jump into the state S2, a processing data, including unescapes discarded detection sequence. 若状态机检测到丢弃序列,该通道当前帧剩余的数据将被丢弃,即既不被处理,也不送入FIF0中,状态直接由S2转为S1,进行新的一帧的帧头搜索,同时给出错误状态。 If the state machine detects the abort sequence, the channel current frame remaining data is discarded, i.e. neither treated nor into the FIF0, the state directly into Sl S2, a search for a new header frame, At the same time it gives the wrong state. 状态S2中,若搜索到了当前帧的帧尾或下一帧的帧头时,跳入状态S3,首先进行CRC校验码和最终帧长的判断,相应的给出各种错误判断。 State S2, if the end of frame header searched for the current frame or the next frame, jump state S3, the CRC is determined firstly and final frame length, corresponding gives various erroneous determination. 因为在本设计中前一帧的帧尾即为后一帧的帧头,因此无须S1中的帧头搜索,而直接跳入S2;。 Because in this prior design is the end of a frame header of the subsequent frame, it is not necessary in the header search S1, S2 ;. jump directly 由于帧长的计算是在此子状态机之外(但仍在主状态"处理"中),与数据的处理同步且独立的进行,所以当状态机处于状态S2,正处理数据之时, 一旦发现帧长超过了最大允许的长度,如同检测到丢弃序列一样,直接跳入Sl,进行下一帧的帧头搜索,同时给出帧长过长的错误状态,而当前帧的剩余数据将不被处理。 Since the frame length is calculated outside of this sub state machine (but still in the main state "process"), the data synchronization processing is performed and independent, so that when the state machine is in state S2, the timing of processing the data, once found frame length exceeds the maximum allowed length, the same sequence as the detected discarded, Sl is a direct jump, search for the next frame header, the frame length is too long and gives an error state, and the remaining data of the current frame will not It is processed. 状态机由S2跳入S3之后,首先进行各种错误的判断。 After the jump from the state machine S2 S3, judgment is first performed various errors. 当发现接收到的数据帧同时存在多个错误时,状态机以帧效验序列错误为优先级最高的错误状态。 When the received data frame found the presence of a plurality of errors simultaneously, the state machine frame sequence error efficacy as the highest priority error conditions. 由于除了正常状态(接收数据既不在帧头,也不在帧尾),大部分状态都在发现帧尾时(S3状态中)进行判断,并随同接收数据一并输出。 Since the addition to the normal state (neither in the received data header, nor the end of the frame), the majority are found in state (S3 state) for determining the end of a time frame, and output along with the received data together. 而一个高速数据链路控制协议帧的开始, 只能在S1中判断,此时移位寄存器不可能有输出,所以有必要在通道状态RAM中輦一个状态标志位顿开始标志位,当发现帧头时,将其置为1,待到移位寄存器第—次满时,输出状态位。 Begins a high speed data link control protocol frame, Analyzing only in S1, the output of the shift register is impossible, it is necessary in the channel state RAM, a chariot status flag Raton start flag, when discovery frame when the head, which is set to 1, the shift register until - once full time, output status bit. 为了实现反转义的功能';当状态机检测到0x7D时,即将下一数据与0X20异或输出。 In order to realize the function of reversing the sense '; when the state machine detects 0x7D, the next data is about 0X20 output of XOR. 在状态机中为了实现多通道的时分复用,同样也用变量帧长度来控制一个通道的处理时间,即每次处理一位数据,长度减l,直至为0,从而完成了该通道的处理0我们借助于多通道髙速数据链路控制协议的办法,接收时,在数据前端追加通道号(考虑到我们的具体设计对象,该通道号采用KEY号更为合理),每一个通道配有一个通道状态寄存器,记录上次该通道(即相应的KEY号)处理情况,以及CRC校验值,以便下一次在该基础上继续计算CRC校验值,从而完成了校验功能。 In order to achieve the state machine time division multiplexing multi-channel, also with a variable frame length control processing time for one channel, i.e., each time a data processing, reduced length L, up to 0, thereby completing the processing of the channel 0 we speed by means of multi-channel data link control protocol Gao approach is received, the channel number is added at the front end of the data (taking into account our specific design object, the channel number using a more reasonable number KEY), with each channel a channel status register, the last record of the channel (i.e., the corresponding number KEY) process, as well as CRC check value, in order to continue to calculate a CRC checksum based on the lower, thereby completing the check function. 处理过的数据即发相应的ready信号。 The processed data that is made corresponding ready signals. 根据写状态时所获得的信息:本次处理的包中包含完整端对端协议包的个数及其长度,并将数据读出,而剩余残段则寄存在现场可编程门阵列内部,待下一次相同KEY号的数据输入时,构成完整端对端协议包再输出。 The write status information obtained: This process contains a complete end to end protocol packet number and packet length, the data is read out, and the remaining residual segments are registered in the internal field programmable gate array, to be KEY next data input the same number, the full end to end configuration protocol packet and then output. 应当理解的是,对本领域普通技术人员来说,可以根据本发明的较佳实例以及其技术构思做出各种可能的改变或替换,而所有这些改变或替换都应属于本发明所附权利要求的保护范围。 It should be understood that those of ordinary skill in the art may make various changes or substitutions may be in accordance with a preferred embodiment of the present invention and the technical concept, and all such modifications or replacements shall belong to the appended claims of the invention the scope of protection.

Claims (8)

  1. 1、一种多通道高速数据处理器,其特征在于该处理器具体包括以下的四个模块:现场可编程门阵列硬件模块(1);4倍数据速率接口模块(2);可编程只读存储器程序配置模块(3)和软件系统模块(4);所述4倍数据速率接口模块(2)包括:内部集成电路总线接口(2.1)、4倍数据速率接口(2.2)、JTAG接口(2.3)和外围供电模块(2.4);现场可编程门阵列硬件模块(1)通过4倍数据速率接口(2.2)连接外部主机、通过电源线与外围供电模块(2.4)连接以及通过JTAG接口(2.3)与可编程只读存储器程序配置模块(3)中的Flash可编程只读存储器电路(3.2)相接,Flash可编程只读存储器电路(3.2)还通过JTAG接口(2.3)与外部的PC机相接;可编程只读存储器程序配置模块(3)中的内部集成电路总线可编程只读存储器电路(3.1)通过内部集成电路总线接口(2.1)连接外部主机;软件系统模块(4),包括了:队列调度模块(4 1, a multiple channel high-speed data processor, wherein the processor comprises the following four modules: a field programmable gate array hardware module (1); 4-data-rate interface module (2); programmable readonly configuration memory module (3) and a software system module (4); four times the data rate of the interface module (2) comprising: an internal bus interface integrated circuit (2.1), four times the data rate interface (2.2), JTAG interface (2.3 ) and a peripheral power supply module (2.4); field programmable gate array of hardware modules (1) are connected by four times the data rate interface (2.2) external host connected via the power supply line and the peripheral power supply module (2.4) and through the JTAG interface (2.3) and programmable read only memory program module configured Flash programmable read only memory circuit (3.2) (3) in contact, Flash programmable read only memory circuit (3.2) is also (2.3) with an external PC, through the JTAG interface bonding; programmable read only memory program module C bus configuration programmable read only memory circuit (3.1) (3) is connected via an external host inter-integrated circuit bus interface (2.1); software system module (4), including : queue scheduling module (4 .1)、接收数据缓存模块(4.2)、发送数据缓存模块(4.3)、高速数据链路控制协议数据包反转义及其标志字处理模块(4.4)和帧校验序列模块(4.5),软件系统模块(4)包括的各模块之间通过信号传递连接在一起;软件系统模块(4)驻留在可编程只读存储器程序配置模块(3)中,多通道高速数据处理器工作后,程序被加载到现场可编程门阵列硬件模块(1)中,而现场可编程门阵列硬件模块(1)通过4倍数据速率接口模块(2)与外部主机的程序连接在一起。 .1), the receive data buffer module (4.2), the transmission data buffer module (4.3), a high speed data link control protocol packets and flag word processing module unescape (4.4) module and a frame check sequence (4.5), software system module (4) comprises a connection between the modules together by transmitting a signal; the software system module (4) in a programmable read only memory resident program configuration module (3), a multi-channel high-speed data processor operates, program is loaded into the hardware module field programmable gate array (1), and field programmable gate array of hardware modules (1) (2) and the external host program connected together by four times the data rate of the interface module.
  2. 2、 根据权利要求1所述的多通道高速数据处理器,其特征在于现场可编程门阵列硬件模块(1)采用200万门"XC3S2000"现场可编程门阵列作为外部主机的协处理器。 2, according to claim multichannel high-speed data processor of claim 1, wherein the field programmable gate array of hardware modules (1) The coprocessor 2000000 "XC3S2000" field programmable gate array as an external host.
  3. 3、 根据权利要求1所述的多通道高速数据处理器,其特征在于4倍数据速率接口模块(2)中,外围供电模块(2.4)在生成2.5V电压时,采用了"TPS75525" 电压转换芯片;在生成1.2v电压时,采用了"TPS54312"电压转换芯片;在生成0.75V电压时,采用"MAX1589EZTAFJ"芯片。 3, according to the multi-channel high-speed data processor according to claim 1, characterized in that the data rate interface module 4 (2), the peripheral power supply module (2.4) at a voltage of 2.5V is generated, using the "TPS75525" voltage converter chip; 1.2v voltage when generating, using the "TPS54312" converting chip; 0.75V when the generation voltage using "MAX1589EZTAFJ" chip.
  4. 4、 根据权利要求1所述的多通道高速数据处理器,其特征在于可编程只读存储器程序配置模块(3)中,采用内部集成电路总线可编程只读存储器电路(3.1) 记录所述处理器的设备信息,包括设备识别符、工作电平和温度参数,外部主机通过内部集成电路总线可编程只读存储器电路(3.1)进行检测以识别多通道高速数据处理器,内部集成电路总线可编程只读存储器电路(3.1)本身还支持口令加密和密码保护。 4. The process according to claim multichannel high-speed data processor to claim 1, wherein the configuration module program programmable read only memory (3), using the C bus circuit programmable read only memory (3.1) Record device information device, comprising a device identifier, a parameter working temperature level, detected by the external host C bus circuit programmable read only memory (3.1) to identify a multichannel high-speed data processor, a programmable C bus only read-only memory circuit (3.1) itself supports password encryption and password protection.
  5. 5、 根据权利要求1所述的多通道高速数据处理器,其特征在于可编程只读存储器程序配置模块(3)中,采用Flash可编程只读存储器电路(3.2)在上电时自动对现场可编程门阵列硬件模块(1)进行配置,配置方式有主控模式和被控模式两种。 5. The multi-channel high-speed data processor according to claim 1, characterized in that the programmable read-only program memory configuration module (3), the use of Flash programmable read only memory circuit (3.2) automatically at power-site programmable gate array, hardware module (1) is configured, arranged and controlled manner with a master mode two modes.
  6. 6、 一种如权利要求1所述的多通道高速数据处理器的高速数据处理方法,其特征在于软件系统模块(4)中,首先由外部主机处理器发出读写信息和数据信息, 队列调度模块(4.1)从外部主机处理器获取读写信息及数据信息,接收数据缓存模块(4.2)从队列调度模块(4.1)获取相应的写命令后,对接收数据缓存模块(4.2)的缓冲区进行相应的写操作,以便于高速数据链路控制协议数据包反转义及其标志字处理模块(4.4)的处理,处理后的控制信号有效帧信号、转义信号及外部主机处理器输出数据一并传入帧校验序列模块(4.5),经校验后产生控制信号写缓冲信号、帧尾信号、校验错误信号及校验后数据,传入发送数据缓存模块(4.3),发送数据缓存模块(4.3)综合处理判断后将校验后数据写入发送数据缓存模块(4.3)的缓冲区,结合队列调度模块(4.1)的读信息, 6 high-speed data processing method, as claimed in the multi-channel high-speed data processor according to claim 1, characterized in that the software system module (4), first read information and data information sent by an external host processor, scheduling queue module (4.1) after obtaining the information and data information read from an external host processor, the receive data buffer module (4.2) to obtain the corresponding write command from the queue scheduling module (4.1), the received data buffer of the buffer module (4.2) is corresponding write operation in order to handle high-speed data link control protocol packets and flag word unescapes module (4.4), the control signal is valid after the frame signal processing, and external signals escaping host processor output data a and incoming frame check sequence module (4.5), generating a control signal after checking the write buffer signal, frame signal, a parity error signal and verify the data, sending the incoming data buffer module (4.3), the transmission data buffer buffer module (4.3) is determined after checking the integration processing data write transmission data buffer module (4.3), combined with the queue scheduling module (4.1) of reading information, 过对发送数据缓存模块(4.3)的缓冲区的读操作将处理后的数据输出。 Through transmission data buffers cache module (4.3) of the read operation outputs the processed data.
  7. 7、 根据权利要求6所述的多通道高速数据处理器的高速数据处理方法,其特征在于软件系统模块(4)对每个通道的数据进行帧头搜索、循环冗余码校验、反转义、丢弃序列的检测、帧长的监测以及帧尾的搜索, 一旦检测到某一帧当前传输的信息位数达到最大帧长或检测到丢弃序列时,软件系统模块(4)中的状态机对当前帧的处理结束,并重新对新的一帧进行帧头搜索,而当前帧中的剩余数据将不被处理。 High-speed data processing method of the multi-channel high-speed data processor 7, according to claim 6, characterized in that the software system module (4) for searching the data header of each channel, cyclic redundancy check, reverse when Yi discarded detected frame length and sequence monitoring frame end of the search, the information bits upon detection of a current transmission frame reaches the maximum frame length, or abort sequence is detected, the state machine software system module (4) processing of the current frame is completed, and a new re-search for the header, and the remaining data of the current frame will not be processed.
  8. 8、 根据权利要求6所述的多通道高速数据处理器的高速数据处理方法,其特征在于软件系统模块(4)同时处理高达128通道并行传输的高速数据链路控制协议数据流,它的实现是采用时分复用的方式,其中通道状态存储器用于实现时分复用,每一个通道在该通道状态存储器之中都有一块固定的存储空间,用以存储该通道的数据处理情况,即通道状态信息,为每一个通道每一段需要被处理的数据分配一段长度一定的时间片,每个时间片结束时,当前通道最新的状态信息将被存入通道状态存储器中的相应存储空间,当新的一段数据到达时,此段数据所属的通道在上一个时间片内被刷新的状态信息将从通道状态存储器中读出并加载到状态机中,为新一轮的数据处理做准备。 High-speed data processing method of the multi-channel high-speed data processor 8, according to claim 6, characterized in that the software system module (4) to handle up to 128 channels of the parallel transmission of high speed data link control protocol data stream, its realization a time division multiplexing manner, wherein the channel state memory used to implement time division multiplexing, each channel has a fixed in the channel state memory storage space for the storage of the data processing channels, i.e. channel status information data for each channel of each segment to be processed is assigned a length of a certain time slice, the end of each time slice, the most current status of the channel information is stored in a respective memory space in the channel status memory, when the new when a piece of data arrives, the data belongs paragraph channels within a time slice is refreshed on state information from the channel state memory is read out and loaded into the state machine in preparation for a new round of data processing.
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