CN1391695A - Field programmable gate array hard disk system - Google Patents
Field programmable gate array hard disk system Download PDFInfo
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- CN1391695A CN1391695A CN 00815913 CN00815913A CN1391695A CN 1391695 A CN1391695 A CN 1391695A CN 00815913 CN00815913 CN 00815913 CN 00815913 A CN00815913 A CN 00815913A CN 1391695 A CN1391695 A CN 1391695A
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- hard disk
- data
- disk drive
- fpga
- hdd
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
- G06F3/06—Digital input from, or digital output to, record carriers, e.g. RAID, emulated record carriers or networked record carriers
- G06F3/0601—Interfaces specially adapted for storage systems
- G06F3/0602—Interfaces specially adapted for storage systems specifically adapted to achieve a particular effect
- G06F3/0604—Improving or facilitating administration, e.g. storage management
- G06F3/0607—Improving or facilitating administration, e.g. storage management by facilitating the process of upgrading existing storage systems, e.g. for improving compatibility between host and storage device
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F15/00—Digital computers in general; Data processing equipment in general
- G06F15/76—Architectures of general purpose stored program computers
- G06F15/78—Architectures of general purpose stored program computers comprising a single central processing unit
- G06F15/7867—Architectures of general purpose stored program computers comprising a single central processing unit with reconfigurable architecture
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
- G06F3/06—Digital input from, or digital output to, record carriers, e.g. RAID, emulated record carriers or networked record carriers
- G06F3/0601—Interfaces specially adapted for storage systems
- G06F3/0628—Interfaces specially adapted for storage systems making use of a particular technique
- G06F3/0655—Vertical data movement, i.e. input-output transfer; data movement between one or more hosts and one or more storage devices
- G06F3/0661—Format or protocol conversion arrangements
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
- G06F3/06—Digital input from, or digital output to, record carriers, e.g. RAID, emulated record carriers or networked record carriers
- G06F3/0601—Interfaces specially adapted for storage systems
- G06F3/0668—Interfaces specially adapted for storage systems adopting a particular infrastructure
- G06F3/0671—In-line storage system
- G06F3/0673—Single storage device
- G06F3/0674—Disk device
- G06F3/0676—Magnetic disk device
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- Engineering & Computer Science (AREA)
- Theoretical Computer Science (AREA)
- Physics & Mathematics (AREA)
- General Engineering & Computer Science (AREA)
- General Physics & Mathematics (AREA)
- Human Computer Interaction (AREA)
- Computer Hardware Design (AREA)
- Signal Processing For Digital Recording And Reproducing (AREA)
Abstract
An FPGA/HD assembly is self-contained by integrating with the FPGA with the HDD assembly, with the HDD storing the in-circuit programming for the FPGA, and modifying the FPGA to cooperate with any selected interface under the control of the embedded controller in the HDD. The in-circuit programming data is stored directly on a selected partition of the HDD, leaving as much space as needed for any other data traditionally stored on the HDD. The controller would locate the specific in-circuit data and locate the appropriate soft core into the FPGA upon receiving a command identifying the bus which is to be interfaced within any selected operation.
Description
The cross reference relevant with the application
The application based on advocate application on September 20th, 1999, the provisional application sequence number is No.60/154,881, the patented claim that is entitled as " field programmable gate array hard disk system " of being invented by William S.Herz.The patent of this provisional application will join the present invention by reference.
Technical field
The present invention is mainly concerned with the storage system that combines with the hard disk drive device, and or rather, relating to provides various to the abundant configurable interface of hard disk drive or be applicable to the system of the processor of hard disk drive.
Background technology
Present technology status has allowed field programmable gate array (FPGA) is carried out online programming.In general, data programmed resides in the storer or by main frame and is sent among the FPGA.Finally, these data all are kept in some memory devices (by calculating the RAM of function access, ROM, or hard disk).These data are used for the programming to FPGA, to finish the appointed function of FPGA.Owing to when entering data into FPGA, be subjected to the restriction of memory span and cpu load ability, so the docking port number exists actual restriction.
This class restriction is a particular importance to the device such as DEU data exchange unit, and this DEU data exchange unit discloses in the application institute CROSS-REFERENCE TO RELATED APPLICATION.In this application, disclosed DEU data exchange unit, it is specially adapted to the data code flow that portable storage is imported from some sources, these sources comprise TV signal, SPDIF formatted data, and the information that receives on such as buses such as usb bus or ata bus or 1394 buses.These information sources all require it to have separately interface, therefore make the core number multiplication that must comprise, and have also increased the quantity of function silicon chip, have also therefore increased the cost of the many interface product of this class.
Summary of the invention
An object of the present invention is to provide an energy and the mutually compatible single component of multiple interfaces.
Or rather, in the present invention, adopt one or more fpga chips to substitute some interface chips.
Or rather, in the present invention, PFGA has the characteristic that is stored in programming information in the associated hard disk.
Or rather, the present invention has the characteristic that FPGA is integrated with the Hard disc module of storing relevant online programming data.
Also having a characteristic is that FPGA and Hard disc module are integrated, and programming can be revised by the embedded controller in Hard disc module.
In a word, the FPGA/HDD assembly is one to be passed through FPGA and the integrated stand-alone assembly of HDD assembly, it adopts HDD to store data to the FPGA online programming, and under the control of HDD embedded controller the operation realization by any option interface to the modification of FPGA.This has just presented advantage of the present invention, and the online programming data directly are stored in the selected part of HDD, stays abundant space to satisfy the needs of other data of conventional store in HDD.In case receive after the order of identification bus (this bus will be the interface in any selection operation), controller will be sought special-purpose online data and seek the address of the suitable soft nuclear that is input to FPGA.
Concerning reference the following drawings is studied the professional person of this disclosure, other performance of the present invention and advantage will become more clear.
Description of drawings
Fig. 1 is the block diagram of ultimate principle of the present invention; And,
Fig. 2 is a block scheme that shows the many interface product of backplane level that the present invention uses.
Embodiment
Following description has been discussed one with field programmable gate array (FPGA) and the combined system of hard disk drive (HDD) assembly (HDD), so that various and the abundant configurable interface of hard disk drive are provided or are applicable to the processor of hard disk.Yet should be realized that: performance of the present invention and advantage are not limited to the block scheme of appointment discussed herein.The performance that is presented can be applied to the interface or the processor of any number, and in addition, the data of FPGA can be stored in the branch section of random capacity hard disk drive.
With reference to Fig. 1, realize that primary element of the present invention comprises hard disk drive (HDD) assembly 100, it has comprised embedded controller 102 and preferably can also comprise the FPGA104 of an embedding or the FPGA104 that closely links to each other.As everyone knows, in the technical field of FPGA, the function of this device 104 can be revised again and again according to the data that download to FPGA, and data downloaded is specified special function to the soft nuclear of FPGA.For example, this device need adopt multiple interfaces () occasion for example, ata interface, 1394 interfaces, or USB interface, FPGA104 can the given arbitrarily time according to adopting needed signal processing structure and function by controller 102 data downloaded.According to the present invention, after having defined desired interface, these data can be stored in the various piece zone of HDD100.In the random time in FPGA uses, can be according to some external control signal, the function of time or other, make FPGA provide special interface function, make hard disk drive that the data in the FPGA data partition 110 of hard disk drive are downloaded to FPGA104 in conjunction with onboard controller to total system 10.In case the FPGA data have been downloaded, FPGA just uses as a special programming device.
So,, above-mentioned specified or do not have specially appointed any programmable interface can both satisfy user's needs effectively according to the present invention.The data of soft nuclear also can be loaded by time division multiplexing, perhaps wipe under intervention that is not having other main frame under the control of acceptance from the single external signal of designated external main frame and loading.By with the combination of HDD assembly, this has just reduced the cost of making significantly and has eliminated original function silicon chip that needs to realize each required interface and need.
Adopting the example of the backplane level system of multiple interfaces is the DEU data exchange unit of employing memory device shown in Figure 2, and it is that the art technology skilled person can better realize and help in conjunction with of the present invention.
DEU data exchange unit (shuttle) is accepted from the continuous bit stream of the numerical information in multiple source and the various interface by institute's combination code stream to be sent to data link and by bus code stream to be sent to hard disk drive.In the figure, the input from various devices or data source is presented at the left side, the same output that also has to potential purpose.If the signal of accepting is an analog format, then carry out digitizing, compound television video frequency signal 700 and associate audio signal 702 are applied to suitable A here to D analog-digital converter 704 and 706 and transmit MPREG-2 scrambler 710 by bus subsequently as upper left that example is shown in.The output of MPREG-2 scrambler 710 is transferred to hard disk processing device 714 by data packetizer 712 again, and the hard disk processing utensil has suitable file management, bus arbitration, and Content Management and code stream management function are so that data can be stored in local hard disk drive 720.Like this, any desired video input code flow can both be changed, and digitizing is handled and is accessed in the DEU data exchange unit selectively.Mpeg encoder and demoder can embody FPGA, and the FPGA control of microprocessor 270 onboard adopts the data that are stored on the local HDD220 to programme down again.Like this, just can reduce the actual number that uses the encoder/decoder chip.
Switch also can by bus be connected than the big hard disk driver, this hard disk drive can be nested or be arranged on the embedding of switch or deposits in the device 760.Subsequently, hard disk processing device 714 is transferred to embedding hard disk drive 740 with the numerical data of local disk drive memory by ata bus again, and this driver can have bigger capacity.Like this, the various interface shown in DEU data exchange unit can be passed through is transmitted data from a device to another device, or the data of storage input from one or several source.
DEU data exchange unit is operated under the control of the native processor 770 of self, and comprises power unit and monitor 772 and controlling 780-784.
In other interface, DEU data exchange unit has also comprised the input/output bus 720 that can operate the SPDIF form.This input/output bus 720 can directly move data packing device 712 and move hard disk processing device 714 by bus subsequently.Another SPDIF input that is used to accept DAB is the input to MPEG-2 scrambler 71 0; The output of MPEG-2 scrambler 710 also is transferred to hard disk processing device 714 to be stored in local hard drive 720 or nested hard disk 740.Digital audio source 722 also can be applied to MP3 scrambler 724, and the output of MP3 scrambler 724 is directly connected to data packetizer 712, and subsequently to hard disk controller 714, so the data of SPDIF form can both be stored and access selectively arbitrarily.
The multiple bidirectional bus that comprises usb bus 730,1394 buses 732 and ata bus 734 also is provided.Usb bus 730 can provide two-way connection, for example, connects the MP3 player, Digital Video, or PC.By USB PHY 740 and data packetizer 742, arbitrarily this class device can both with they input and output directly and data packetizer 712 be coupled, and be transferred to hard disk drive 720 by handling 714 subsequently.Adopt similar mode, 1394 buses 732 can connect digital video camera or PC or digital VCR, and are connected with hard disk processing device 714 with data packetizer 712 with data packetizer 746 by suitable substance P HY 744.At last, ata bus 734 can directly be connected Flash (flash) storer or other data storage device with hard disk processing device 714, connect hard disk drive 720 subsequently.
At output facet, even by MP3 scrambler 724 SPDIF input 722 is transferred to storer, the output that MP3 decoding device 750 is provided can be coupled to SPDIF output bus 752 or be arrived modulated amplifier 756 by audio process 754 in addition.In having provided several different outgoing routes, comprise radio frequency modulator AV758, stereo output 760 and audio frequency output 762.Audio frequency output more is to adopt TV output 764, and it is by digital video code 766 and MPEG-2 demoder 768 and passes through modulated amplifier.The MPEG-2 demoder is accepted the video information from de-packetizer 712 and hard disk processing device 714, it should be noted that the hard disk processing device can be accessed in any file in the local hard drive 720 selectively.These all functions all are to carry out under the control of CPU770, and CPU is Motorola 823E and by power supply 772 and monitor support in this example.
Function can be selected, and the source and destination of input and output can adopt IR (infrared) controller 780 to discern, and selected function can be presented on the LCD display of panel of switch.By being combined in the control I/O 784 in the switch and can both supporting above-mentioned functions by the function that bus 786 is controlled CPU770.
Be similar to above-mentioned the discussion, on each comprises the bus of packing device/de-packetizer, can adopt FPGA.After having selected bus, microprocessor can be downloaded data necessary from hard disk drive FPGA is programmed, and it is used as required packing device/de-packetizer.
Like this, processor plate is actually have been simplified, and does not have extra burden to be added on the main frame because on the plate on the free slave plate of processor hard disk download the check figure certificate, and can not clash with its storage control function.
Concerning the professional person in the industry who studied disclosed foregoing invention, other application of the present invention, it is more clear that performance and advantage all can become.Therefore, spirit of the present invention only is subjected to the restriction of following claim.
Claims (6)
1. comprise in the integrated system of field programmable gate array (FPGA) and hard disk drive (HDD) assembly at one, hard disk drive (HDD) assembly further comprises integrated microprocessor, with the hard disk drive of storage data, the data of being stored are used to dispose field programmable gate array and finish a plurality of different functions under the interference without system host down with the control of processor onboard.
2. the system as claimed in claim 1, it is characterized in that: it has comprised multiple interfaces, each interface is connected with hard disk drive by scrambler or demoder, one or more scramblers or demoder can be realized by monolithic FPGA, and this FPGA can programme with as different interface work by being stored in data in the hard disk drive again.
3. the system as claimed in claim 1, it is characterized in that comprising multiple interfaces, each interface is connected with hard disk drive by packing device or de-packetizer, one or more packing devices or de-packetizer can be realized that this FPGA can adopt the data that are stored in the hard disk drive to programme to select an interface job in the multiple interfaces by monolithic FPGA.
4. system as claimed in claim 3, it is characterized in that comprising hard disk controller, this hard disk controller is used at a plurality of FPGA of the being used for data programmed collection of the certifiable part of hard disk drive storage, and selects data set FPGA that programmes according to the selected interface that sends data or accept data from system to system from above-mentioned data centralization after the order of processor on the response panel.
5. comprise in the integrated system of field programmable gate array (FPGA) and hard disk drive (HDD) assembly at one, hard disk drive (HDD) assembly further comprises integrated microprocessor, with the hard disk drive of storage data, the data of being stored are used to dispose field programmable gate array and finish a plurality of different functions under the interference without system host down with the control of processor onboard; Its method comprises: a plurality of data sets that will be used for the field programmable gate array programming are stored in the subregion of hard disk drive, discern one and selectedly send data or accept the interface of data, and adopt a data set in the hard disk drive FPGA that programmes according to the identification of selected interface under the control of processor onboard from system to system.
6. comprise in the integrated system of field programmable gate array (FPGA) and hard disk drive (HDD) assembly at one, hard disk drive (HDD) assembly further comprises integrated microprocessor, with the hard disk drive of storage data, the data of being stored are used to dispose field programmable gate array and finish a plurality of different functions under the interference without system host down with the control of controller onboard; Its device comprises: a plurality of data sets that will be used for field programmable gate array programming are stored in the subregion of hard disk, and, adopt a data set in the hard disk drive FPGA that programmes according to the sign of selected interface under the control of processor onboard.
Applications Claiming Priority (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| US15488199P | 1999-09-20 | 1999-09-20 | |
| US60/154,881 | 1999-09-20 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN1391695A true CN1391695A (en) | 2003-01-15 |
Family
ID=22553211
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN 00815913 Pending CN1391695A (en) | 1999-09-20 | 2000-09-20 | Field programmable gate array hard disk system |
Country Status (7)
| Country | Link |
|---|---|
| JP (1) | JP2003510705A (en) |
| KR (1) | KR20020035606A (en) |
| CN (1) | CN1391695A (en) |
| AU (1) | AU7597600A (en) |
| DE (1) | DE10085014T1 (en) |
| GB (1) | GB2371138B (en) |
| WO (1) | WO2001022425A1 (en) |
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1333349C (en) * | 2003-12-23 | 2007-08-22 | 华为技术有限公司 | System and method for loading on-site programmable gate array |
| CN100433697C (en) * | 2006-06-01 | 2008-11-12 | 东南大学 | Multi-channel high-speed data processor and processing method |
| CN102685609A (en) * | 2011-09-28 | 2012-09-19 | 朱良学 | Multi-protocol soft-core digital interphone |
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| US6711558B1 (en) | 2000-04-07 | 2004-03-23 | Washington University | Associative database scanning and information retrieval |
| US7139743B2 (en) | 2000-04-07 | 2006-11-21 | Washington University | Associative database scanning and information retrieval using FPGA devices |
| US7716330B2 (en) | 2001-10-19 | 2010-05-11 | Global Velocity, Inc. | System and method for controlling transmission of data packets over an information network |
| US7711844B2 (en) | 2002-08-15 | 2010-05-04 | Washington University Of St. Louis | TCP-splitter: reliable packet monitoring methods and apparatus for high speed networks |
| EP2528000B1 (en) * | 2003-05-23 | 2017-07-26 | IP Reservoir, LLC | Intelligent data storage and processing using FPGA devices |
| US10572824B2 (en) | 2003-05-23 | 2020-02-25 | Ip Reservoir, Llc | System and method for low latency multi-functional pipeline with correlation logic and selectively activated/deactivated pipelined data processing engines |
| KR100954010B1 (en) * | 2003-11-06 | 2010-04-20 | 엘지노텔 주식회사 | Programmable multimedia apparatus of data processing system |
| JP2008532177A (en) | 2005-03-03 | 2008-08-14 | ワシントン ユニヴァーシティー | Method and apparatus for performing biological sequence similarity searches |
| US7702629B2 (en) | 2005-12-02 | 2010-04-20 | Exegy Incorporated | Method and device for high performance regular expression pattern matching |
| US7921046B2 (en) | 2006-06-19 | 2011-04-05 | Exegy Incorporated | High speed processing of financial information using FPGA devices |
| US7660793B2 (en) | 2006-11-13 | 2010-02-09 | Exegy Incorporated | Method and system for high performance integration, processing and searching of structured and unstructured data using coprocessors |
| US10229453B2 (en) | 2008-01-11 | 2019-03-12 | Ip Reservoir, Llc | Method and system for low latency basket calculation |
| US8374986B2 (en) | 2008-05-15 | 2013-02-12 | Exegy Incorporated | Method and system for accelerated stream processing |
| US20120095893A1 (en) | 2008-12-15 | 2012-04-19 | Exegy Incorporated | Method and apparatus for high-speed processing of financial market depth data |
| CN101673101B (en) * | 2009-09-27 | 2011-06-22 | 电子科技大学 | On-line programming FPGA reconfigurable device |
| CN101808027B (en) * | 2010-03-31 | 2011-11-23 | 哈尔滨工业大学 | Data receiving, storing and forwarding device suitable for various ports |
| JP6045505B2 (en) | 2010-12-09 | 2016-12-14 | アイピー レザボア, エルエルシー.IP Reservoir, LLC. | Method and apparatus for managing orders in a financial market |
| US9990393B2 (en) | 2012-03-27 | 2018-06-05 | Ip Reservoir, Llc | Intelligent feed switch |
| US11436672B2 (en) | 2012-03-27 | 2022-09-06 | Exegy Incorporated | Intelligent switch for processing financial market data |
| US10121196B2 (en) | 2012-03-27 | 2018-11-06 | Ip Reservoir, Llc | Offload processing of data packets containing financial market data |
| US10650452B2 (en) | 2012-03-27 | 2020-05-12 | Ip Reservoir, Llc | Offload processing of data packets |
| US10102260B2 (en) | 2012-10-23 | 2018-10-16 | Ip Reservoir, Llc | Method and apparatus for accelerated data translation using record layout detection |
| US9633093B2 (en) | 2012-10-23 | 2017-04-25 | Ip Reservoir, Llc | Method and apparatus for accelerated format translation of data in a delimited data format |
| EP2912579B1 (en) | 2012-10-23 | 2020-08-19 | IP Reservoir, LLC | Method and apparatus for accelerated format translation of data in a delimited data format |
| WO2015164639A1 (en) | 2014-04-23 | 2015-10-29 | Ip Reservoir, Llc | Method and apparatus for accelerated data translation |
| US10942943B2 (en) | 2015-10-29 | 2021-03-09 | Ip Reservoir, Llc | Dynamic field data translation to support high performance stream data processing |
| WO2018119035A1 (en) | 2016-12-22 | 2018-06-28 | Ip Reservoir, Llc | Pipelines for hardware-accelerated machine learning |
| DE102018123494A1 (en) | 2017-11-17 | 2019-05-23 | Samsung Electronics Co., Ltd. | MEMORY DEVICE DESIGNED TO UPGRADE A FIELD-PROGRAMMABLE GATE ARRAY, AND OPERATING METHOD THEREFOR |
| CN113312098B (en) * | 2020-04-01 | 2022-08-12 | 阿里巴巴集团控股有限公司 | Program loading method, device, system and storage medium |
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| EP0665998A4 (en) * | 1993-08-03 | 1996-06-12 | Xilinx Inc | Microprocessor-based fpga. |
| US5600845A (en) * | 1994-07-27 | 1997-02-04 | Metalithic Systems Incorporated | Integrated circuit computing device comprising a dynamically configurable gate array having a microprocessor and reconfigurable instruction execution means and method therefor |
| US5619728A (en) * | 1994-10-20 | 1997-04-08 | Dell Usa, L.P. | Decoupled DMA transfer list storage technique for a peripheral resource controller |
| EP0718751A3 (en) * | 1994-12-23 | 1997-02-12 | Ibm | Electronic circuit apparatus employing small disk drive with reconfigurable interface |
-
2000
- 2000-09-20 DE DE10085014T patent/DE10085014T1/en not_active Withdrawn
- 2000-09-20 WO PCT/US2000/025846 patent/WO2001022425A1/en active Application Filing
- 2000-09-20 KR KR1020027003625A patent/KR20020035606A/en active IP Right Grant
- 2000-09-20 AU AU75976/00A patent/AU7597600A/en not_active Abandoned
- 2000-09-20 JP JP2001525707A patent/JP2003510705A/en active Pending
- 2000-09-20 GB GB0207720A patent/GB2371138B/en not_active Expired - Fee Related
- 2000-09-20 CN CN 00815913 patent/CN1391695A/en active Pending
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1333349C (en) * | 2003-12-23 | 2007-08-22 | 华为技术有限公司 | System and method for loading on-site programmable gate array |
| CN100433697C (en) * | 2006-06-01 | 2008-11-12 | 东南大学 | Multi-channel high-speed data processor and processing method |
| CN102685609A (en) * | 2011-09-28 | 2012-09-19 | 朱良学 | Multi-protocol soft-core digital interphone |
Also Published As
| Publication number | Publication date |
|---|---|
| GB2371138A (en) | 2002-07-17 |
| GB0207720D0 (en) | 2002-05-15 |
| GB2371138B (en) | 2003-12-10 |
| KR20020035606A (en) | 2002-05-11 |
| WO2001022425A9 (en) | 2002-11-21 |
| AU7597600A (en) | 2001-04-24 |
| WO2001022425A1 (en) | 2001-03-29 |
| JP2003510705A (en) | 2003-03-18 |
| DE10085014T1 (en) | 2003-04-30 |
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