WO2001022425A1 - Field programmable gate array hard disk system - Google Patents

Field programmable gate array hard disk system Download PDF

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Publication number
WO2001022425A1
WO2001022425A1 PCT/US2000/025846 US0025846W WO0122425A1 WO 2001022425 A1 WO2001022425 A1 WO 2001022425A1 US 0025846 W US0025846 W US 0025846W WO 0122425 A1 WO0122425 A1 WO 0122425A1
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WO
WIPO (PCT)
Prior art keywords
hard disk
disk drive
fpga
data
programmable gate
Prior art date
Application number
PCT/US2000/025846
Other languages
French (fr)
Other versions
WO2001022425A9 (en
Inventor
William S. Herz
Original Assignee
Seagate Technology Llc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Seagate Technology Llc filed Critical Seagate Technology Llc
Priority to KR1020027003625A priority Critical patent/KR20020035606A/en
Priority to DE10085014T priority patent/DE10085014T1/en
Priority to AU75976/00A priority patent/AU7597600A/en
Priority to GB0207720A priority patent/GB2371138B/en
Priority to JP2001525707A priority patent/JP2003510705A/en
Publication of WO2001022425A1 publication Critical patent/WO2001022425A1/en
Publication of WO2001022425A9 publication Critical patent/WO2001022425A9/en

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Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F15/00—Digital computers in general; Data processing equipment in general
    • G06F15/76—Architectures of general purpose stored program computers
    • G06F15/78—Architectures of general purpose stored program computers comprising a single central processing unit
    • G06F15/7867—Architectures of general purpose stored program computers comprising a single central processing unit with reconfigurable architecture
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
    • G06F3/06—Digital input from, or digital output to, record carriers, e.g. RAID, emulated record carriers or networked record carriers
    • G06F3/0601—Interfaces specially adapted for storage systems
    • G06F3/0602—Interfaces specially adapted for storage systems specifically adapted to achieve a particular effect
    • G06F3/0604—Improving or facilitating administration, e.g. storage management
    • G06F3/0607—Improving or facilitating administration, e.g. storage management by facilitating the process of upgrading existing storage systems, e.g. for improving compatibility between host and storage device
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
    • G06F3/06—Digital input from, or digital output to, record carriers, e.g. RAID, emulated record carriers or networked record carriers
    • G06F3/0601—Interfaces specially adapted for storage systems
    • G06F3/0628—Interfaces specially adapted for storage systems making use of a particular technique
    • G06F3/0655—Vertical data movement, i.e. input-output transfer; data movement between one or more hosts and one or more storage devices
    • G06F3/0661—Format or protocol conversion arrangements
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
    • G06F3/06—Digital input from, or digital output to, record carriers, e.g. RAID, emulated record carriers or networked record carriers
    • G06F3/0601—Interfaces specially adapted for storage systems
    • G06F3/0668—Interfaces specially adapted for storage systems adopting a particular infrastructure
    • G06F3/0671—In-line storage system
    • G06F3/0673—Single storage device
    • G06F3/0674—Disk device
    • G06F3/0676—Magnetic disk device

Definitions

  • the present invention relates generally to the field of memory systems incorporating a hard disk drive and more specifically to a system which can provide a variety of fully configurable interfaces to or processes for a hard disk drive.
  • FPGA field programmable gate array
  • this data resides in memory or is passed on to the FPGA via a host computer.
  • this data resides in some storage device (RAM, ROM, or a hard disk all accessed via host intervention). This data is used to program the FPGA to perform its specified function. Practical restrictions on the number of interfaces exist, due to the limitation of memory size and the load on the CPU to steer this data to the FPGA.
  • Such a restraint would have special importance in a device such as the data shuttle disclosed in the related application which is incorporated herein by reference.
  • a single data shuttle is disclosed which is especially useful in portably storing input data stream from a number of sources including television signals, SPDIF formatted data, and information received over buses such as a USB bus or ATA bus or 1394 bus.
  • Each of these requires its own interface, multiplying the number of chips which must be incorporated, increasing the amount of functional silicon and therefore the cost of such a multi-interface product.
  • an FPGA is characterized by programming information stored on an associated hard disk.
  • the present invention is characterized by an FPGA integrated with a hard disk assembly which stores the associated in-circuit programming data.
  • the FPGA is integrated with a hard disk assembly and the programming is modified by an embedded controller in the hard disk assembly.
  • the FPGA/HD assembly is self-contained by integrating with the
  • Fig. 1 is a block diagram schematic of the basic elements of the invention
  • Fig. 2 is a block diagram of a board level multi-interface product in which the present invention is useful.
  • the following description describes a system which combines a field programmable gate array (FPGA) with a hard disk drive assembly (HDD) in order to provide a variety of fully configurable interfaces to or processors for the hard disk drive.
  • FPGA field programmable gate array
  • HDD hard disk drive assembly
  • the basic elements implementing the present invention include the disk drive assembly 100 which includes an embedded controller 102 and preferably an embedded or closely associated field programmable gate array FPGA 104.
  • the functions of this device 104 can be modified from time to time based on data which is downloaded to the FPGA to specify specific functions to its "soft core".
  • the FPGA 104 could adopt the necessary signal processing structures and functions at any given time based on the data loaded into it by the controller 102.
  • this data can be stored on a separate partitioned region 110 of the HDD 100 after the desired interfaces have been defined.
  • the FPGA is to provide a particular interface to the overall system 10
  • the controller 102 which is also incorporated on board the disk drive can download the data from the FPGA data partition 110 on the disk drive into the FPGA 104.
  • the FPGA serves as that particular programmable device.
  • any programmable interface from the group identified above or others not specifically identified is available for any user to assign as needed.
  • the soft core data can be time multiplex loaded or otherwise under control of a single external signal received from the external host computer be assigned to be unloaded without further host computer intervention and loading. This will significantly reduce any manufacturing costs by homogenizing the HDD assembly and eliminates previously required functional silicon which would be required to implement each desired interface.
  • FIG. 2 An example of a board level system utilizing multiple interfaces which could well be implemented by a person of skill in the art in this field and which could very profitably incorporate this invention is the data shuttle utilizing a disk storage device shown in Fig. 2.
  • the shuttle accepts continuous streams of digital information from a variety of sources and conveys them through various interfaces incorporated into the data shuttle and conveys them across a bus into a hard disk drive.
  • the inputs from the various devices or sources of data are shown on the left as are the outputs to potential destinations. If the received data is in analog form, it is digitized as shown for example at the upper left where the composite TV video signals 700 and the associated audio 702 are applied to appropriate A to D converters 704, and 706 and then conveyed over buses to an MPEG-2 encoder 710.
  • the outputs of this MPEG-2 encoder 710 are transferred through a data packetizer 712 to the disk processor 714 which does the appropriate file management, bus arbitration, content management and stream management functions so that the data can be stored on a local hard disk drive 720.
  • the MPEG encoders and decoders could be embodied as an FPGA that was reprogrammed under control of the on-board microprocessor 270 utilizing data stored on the local HDD 220. In this way, the number of actual encoder/decoder chips could be substantially reduced.
  • the shuttle can also be connected across an interface to a larger hard disk drive which is incorporated in a nesting or docking device 760 for the shuttle.
  • the disk processor 714 can then further transmit the stored digital data from the local disk drive 720 onto a nesting disk drive 740 across an ATA bus which would have a larger capacity. In this way, the shuttle can be moved from one apparatus to another and store input data from one or several sources through the various interfaces shown.
  • the shuttle operates under control of its own local processor 770 and includes a power supply and monitor 772 and controls 780-784.
  • the shuttle also includes an input/output bus 720 operative to handle SPDIF format.
  • This input/output bus 720 runs directly to the data packetizer 712 and then across a bus to the disk processor 714.
  • Another SPDIF input 722 for receipt of digital audio is an input to the MPEG-2 encoder 710; the outputs of this MPEG-2 encoder are also conveyed to the disk processor 714 for storage on the local hard disk 720 or the nesting hard disk 740.
  • This digital audio source 722 can also be applied to the MP3 encoder 724 whose outputs are connected directly to the data packetizer 712 and then to the disk processor 714, so that any data in SPDIF format can be stored and selectively accessed.
  • a plurality of bidirectional buses including a USB bus 730, a 1394 bus 732 and an ATA bus 734 are also provided.
  • the USB bus 730 may provide a bidirectional connection for example to an MP3 player, a digital camera or a PC.
  • a USB PHY 740, and a packetizer 742 any of these devices is coupled directly to the data packetizer 712 with their inputs and outputs then conveyed through the processor 714 to the hard disk drive 720.
  • the 1394 bus 732 could be connected to a digital video camera or a PC or a digital VCR through an appropriate PHY 744 and packetizer 746 to the data packetizer 712 and disk processor 714.
  • the ATA bus 734 could connect a flash memory or other data storage device directly to the disk processor 714 and then to the disk drive 720.
  • an MP3 decoder 750 is provided whose output may be coupled to an SPDIF output bus 752 or alternatively through an audio processor 754 to a modulator amp 756.
  • This provides several alternative output lines including an RF modulated AV 758, a stereo phone output 760 and audio output 762.
  • the audio output would more typically be used with the television output 764 which comes through the modulator amp via a digital video encoder 766 and an MPEG-2 decoder 768.
  • the MPEG-2 decoder receives its video information from the depacketizer 712 and the disk processor 714 which as noted above can selectively access any file on the local disk 720. All of these functions are conducted under the control of the CPU 770 which in this example is Motorola 823E which is supported by a power supply 772 and monitor.
  • the functions are selected and the input and output sources and destinations are recognized through an IR control 780 and the selected function displayed on an LCD display 782 on the face of the shuttle. Both of these are supported through a control I/O
  • each bus includes a packetizer/depacketizer
  • a FPGA could be utilized.
  • the microprocessor could download the necessary data from the disk drive to program the FPGA to serve the necessary packetizer/depacketizer.
  • processor board could be substantially simplified without extra burdens being placed on the host computer, since the on-board processor would have the time available to download the core data from the on-board disk drive without any conflict with its data storage control functions.

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  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Human Computer Interaction (AREA)
  • Computer Hardware Design (AREA)
  • Signal Processing For Digital Recording And Reproducing (AREA)

Abstract

An FPGA/HD assembly is self-contained by integrating with the FPGA with the HDD assembly, with the HDD storing the in-circuit programming for the FPGA, and modifying the FPGA to cooperate with any selected interface under the control of the embedded controller in the HDD. The in-circuit programming data is stored directly on a selected partition of the HDD, leaving as much space as needed for any other data traditionally stored on the HDD. The controller would locate the specific in-circuit data and locate the appropriate soft core into the FPGA upon receiving a command identifying the bus which is to be interfaced within any selected operation.

Description

FIELD PROGRAMMABLE GATE ARRAY HARD DISK SYSTEM
CROSS-REFERENCE TO A RELATED APPLICATION This application is based on and claims the priority date of Provisional
Application Serial No. 60/154,881 filed September 20, 1999, entitled FIELD PROGRAMMABLE GATE ARRAY HARD DISK SYSTEM, invented by William S. Herz. This provisional application is incorporated herein by reference.
FIELD OF THE INVENTION
The present invention relates generally to the field of memory systems incorporating a hard disk drive and more specifically to a system which can provide a variety of fully configurable interfaces to or processes for a hard disk drive.
BACKGROUND OF THE INVENTION
The current state of the art allows in-circuit programmability for a field programmable gate array (FPGA). Typically, this data resides in memory or is passed on to the FPGA via a host computer. Ultimately, this data resides in some storage device (RAM, ROM, or a hard disk all accessed via host intervention). This data is used to program the FPGA to perform its specified function. Practical restrictions on the number of interfaces exist, due to the limitation of memory size and the load on the CPU to steer this data to the FPGA.
Such a restraint would have special importance in a device such as the data shuttle disclosed in the related application which is incorporated herein by reference. In this application, a single data shuttle is disclosed which is especially useful in portably storing input data stream from a number of sources including television signals, SPDIF formatted data, and information received over buses such as a USB bus or ATA bus or 1394 bus. Each of these requires its own interface, multiplying the number of chips which must be incorporated, increasing the amount of functional silicon and therefore the cost of such a multi-interface product.
SUMMARY OF THE INVENTION
It is an objective of this invention to create a singular assembly, compatible with a multitude of interfaces. More specifically, in this invention a number of interface chips are replaced by one or more FPGA chips.
More specifically, in the present invention an FPGA is characterized by programming information stored on an associated hard disk.
More specifically, the present invention is characterized by an FPGA integrated with a hard disk assembly which stores the associated in-circuit programming data.
Yet another characteristic is that the FPGA is integrated with a hard disk assembly and the programming is modified by an embedded controller in the hard disk assembly.
In summary, the FPGA/HD assembly is self-contained by integrating with the
FPGA with the HDD assembly, with the HDD storing the in-circuit programming for the FPGA, and modifying the FPGA to cooperate with any selected interface under the control of the embedded controller in the HDD. This presents the advantage in this invention that the in-circuit programming data is stored directly on a selective partition of the HDD, leaving as much space as needed for any other data traditionally stored on the HDD. The controller would locate the specific in-circuit data and locate the appropriate soft core into the FPGA upon receiving a command identifying the bus which is to be interfaced within any selected operation.
Other features and advantages of the invention will become apparent to a person of skill in the art who studies this disclosure given in association with the following drawings. BRIEF DESCRIPTION OF THE DRAWINGS
Fig. 1 is a block diagram schematic of the basic elements of the invention; and Fig. 2 is a block diagram of a board level multi-interface product in which the present invention is useful.
DETAILED DESCRIPTION OF AN EMBODIMENT
The following description describes a system which combines a field programmable gate array (FPGA) with a hard disk drive assembly (HDD) in order to provide a variety of fully configurable interfaces to or processors for the hard disk drive. However, it should be recognized that the features and advantages of this invention are not to be limited to the specific block diagram described herein. The present features may be used with any number of interfaces or processors; further, the FPGA data could be stored in a partition segment of any size disk drive.
Referring to Fig. 1 , the basic elements implementing the present invention include the disk drive assembly 100 which includes an embedded controller 102 and preferably an embedded or closely associated field programmable gate array FPGA 104. As is well known in the field of FPGA technology, the functions of this device 104 can be modified from time to time based on data which is downloaded to the FPGA to specify specific functions to its "soft core". For example, in the field of a device which needs to utilize multiple interfaces, for example an ATA interface, a 1394 interface, or a USB interface, the FPGA 104 could adopt the necessary signal processing structures and functions at any given time based on the data loaded into it by the controller 102. According to the present invention, this data can be stored on a separate partitioned region 110 of the HDD 100 after the desired interfaces have been defined. At any time during the use of the FPGA, based on some external control signal, a time function or the like, the FPGA is to provide a particular interface to the overall system 10, the controller 102 which is also incorporated on board the disk drive can download the data from the FPGA data partition 110 on the disk drive into the FPGA 104. As soon as the FPGA data is downloaded, the FPGA serves as that particular programmable device. Thus, according to the present invention, any programmable interface from the group identified above or others not specifically identified is available for any user to assign as needed. The soft core data can be time multiplex loaded or otherwise under control of a single external signal received from the external host computer be assigned to be unloaded without further host computer intervention and loading. This will significantly reduce any manufacturing costs by homogenizing the HDD assembly and eliminates previously required functional silicon which would be required to implement each desired interface.
An example of a board level system utilizing multiple interfaces which could well be implemented by a person of skill in the art in this field and which could very profitably incorporate this invention is the data shuttle utilizing a disk storage device shown in Fig. 2.
The shuttle accepts continuous streams of digital information from a variety of sources and conveys them through various interfaces incorporated into the data shuttle and conveys them across a bus into a hard disk drive. In this figure, the inputs from the various devices or sources of data are shown on the left as are the outputs to potential destinations. If the received data is in analog form, it is digitized as shown for example at the upper left where the composite TV video signals 700 and the associated audio 702 are applied to appropriate A to D converters 704, and 706 and then conveyed over buses to an MPEG-2 encoder 710. The outputs of this MPEG-2 encoder 710 are transferred through a data packetizer 712 to the disk processor 714 which does the appropriate file management, bus arbitration, content management and stream management functions so that the data can be stored on a local hard disk drive 720. In this way, any desired video input stream can be converted, digitized, processed and stored for selective access on the data shuttle. The MPEG encoders and decoders could be embodied as an FPGA that was reprogrammed under control of the on-board microprocessor 270 utilizing data stored on the local HDD 220. In this way, the number of actual encoder/decoder chips could be substantially reduced.
The shuttle can also be connected across an interface to a larger hard disk drive which is incorporated in a nesting or docking device 760 for the shuttle. The disk processor 714 can then further transmit the stored digital data from the local disk drive 720 onto a nesting disk drive 740 across an ATA bus which would have a larger capacity. In this way, the shuttle can be moved from one apparatus to another and store input data from one or several sources through the various interfaces shown.
The shuttle operates under control of its own local processor 770 and includes a power supply and monitor 772 and controls 780-784.
Among other interfaces, the shuttle also includes an input/output bus 720 operative to handle SPDIF format. This input/output bus 720 runs directly to the data packetizer 712 and then across a bus to the disk processor 714. Another SPDIF input 722 for receipt of digital audio is an input to the MPEG-2 encoder 710; the outputs of this MPEG-2 encoder are also conveyed to the disk processor 714 for storage on the local hard disk 720 or the nesting hard disk 740. This digital audio source 722 can also be applied to the MP3 encoder 724 whose outputs are connected directly to the data packetizer 712 and then to the disk processor 714, so that any data in SPDIF format can be stored and selectively accessed.
A plurality of bidirectional buses including a USB bus 730, a 1394 bus 732 and an ATA bus 734 are also provided. The USB bus 730 may provide a bidirectional connection for example to an MP3 player, a digital camera or a PC. Through a USB PHY 740, and a packetizer 742, any of these devices is coupled directly to the data packetizer 712 with their inputs and outputs then conveyed through the processor 714 to the hard disk drive 720. In similar fashion, the 1394 bus 732 could be connected to a digital video camera or a PC or a digital VCR through an appropriate PHY 744 and packetizer 746 to the data packetizer 712 and disk processor 714. Finally, the ATA bus 734 could connect a flash memory or other data storage device directly to the disk processor 714 and then to the disk drive 720.
On the output side, even as the SPDIF input 722 can be conveyed through an MP3 encoder 724 for storage, an MP3 decoder 750 is provided whose output may be coupled to an SPDIF output bus 752 or alternatively through an audio processor 754 to a modulator amp 756. This provides several alternative output lines including an RF modulated AV 758, a stereo phone output 760 and audio output 762. The audio output would more typically be used with the television output 764 which comes through the modulator amp via a digital video encoder 766 and an MPEG-2 decoder 768. The MPEG-2 decoder receives its video information from the depacketizer 712 and the disk processor 714 which as noted above can selectively access any file on the local disk 720. All of these functions are conducted under the control of the CPU 770 which in this example is Motorola 823E which is supported by a power supply 772 and monitor.
The functions are selected and the input and output sources and destinations are recognized through an IR control 780 and the selected function displayed on an LCD display 782 on the face of the shuttle. Both of these are supported through a control I/O
784 incorporated into the shuttle and controlling the functions of the CPU 770 over the bus 786.
Similarly to the above, where each bus includes a packetizer/depacketizer, a FPGA could be utilized. When a bus is selected, the microprocessor could download the necessary data from the disk drive to program the FPGA to serve the necessary packetizer/depacketizer.
In this way the processor board could be substantially simplified without extra burdens being placed on the host computer, since the on-board processor would have the time available to download the core data from the on-board disk drive without any conflict with its data storage control functions.
Other uses, features and advantages of the present invention will become apparent to a person of skill in the art who studies the above invention disclosure. Therefore, the scope of the present invention is to be limited only by the following claims.

Claims

WHAT IS CLAIMED:
1. In a system which includes a field programmable gate array (FPGA) integrated with a hard disk drive assembly, the hard disk drive assembly further comprising an integrated microprocessor, the hard disk drive storing data to configure the field programmable gate array to perform multiple different functions under control of the onboard processor without intervention by the host of the overall system.
2. A system as claimed in claim 1 including a plurality of interfaces, each connected to the hard disk drive through an encoder or decoder, one or more of the encoders and decoders being implemented by a single FPGA which is reprogrammed to work with a different interface by the data stored on the hard disk drive.
3. A system as claimed in claim 1 including a plurality of interfaces, each connected to the hard disk drive through a packetizer or depacketizer, one or more of the packetizer and depacketizers being implemented by a single FPGA adapted to be programmed to work with a selected one of the plurality of interfaces by data stored on the hard disk drive.
4. A system as claimed in claim 3 including a disk controller adapted to store a plurality of data sets for programming the FPGA in identifiable sections of said hard disk drive, and to select one of said data sets for programming the FPGA in response to a command from the on-board processor dependent on the selected interface which is to send or receive data from the system.
5. In a system which includes a field programmable gate array (FPGA) integrated with a hard disk drive assembly, the hard disk drive assembly further comprising an integrated microprocessor, the hard disk drive storing data to configure the field programmable gate array to perform multiple different functions under control of the onboard processor without intervention by the host of the overall system, the method comprising storing a plurality of data sets for programming the field programmable gate array on a partitioned region of the hard disk drive, identifying a selected one of the interfaces which is to send or receive data from the system, and programming the FPGA with one of the data sets from the hard disk drive under the control of the on-board processor in response to the identification of the selected interface.
6. In a system which includes a field programmable gate array integrated with a hard disk drive assembly, the hard disk drive assembly further comprising an integrated microprocessor, the hard disk drive storing data to configure the field programmable gate array to perform multiple different functions under control of the on-board processor without intervention by the host of the overall system, and means for storing a plurality of data sets for programming the field programmable gate array on a partitioned region of the hard disk drive, and programming the FPGA with one of the data sets from the hard disk drive under the control of the on-board processor in response to the identification of the selected interface.
PCT/US2000/025846 1999-09-20 2000-09-20 Field programmable gate array hard disk system WO2001022425A1 (en)

Priority Applications (5)

Application Number Priority Date Filing Date Title
KR1020027003625A KR20020035606A (en) 1999-09-20 2000-09-20 Field programmable gate array hard disk system
DE10085014T DE10085014T1 (en) 1999-09-20 2000-09-20 Hard disk system with field programmable gate array
AU75976/00A AU7597600A (en) 1999-09-20 2000-09-20 Field programmable gate array hard disk system
GB0207720A GB2371138B (en) 1999-09-20 2000-09-20 Field progammable gate array hard disk system
JP2001525707A JP2003510705A (en) 1999-09-20 2000-09-20 Field programmable gate array hard disk drive

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US15488199P 1999-09-20 1999-09-20
US60/154,881 1999-09-20

Publications (2)

Publication Number Publication Date
WO2001022425A1 true WO2001022425A1 (en) 2001-03-29
WO2001022425A9 WO2001022425A9 (en) 2002-11-21

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JP (1) JP2003510705A (en)
KR (1) KR20020035606A (en)
CN (1) CN1391695A (en)
AU (1) AU7597600A (en)
DE (1) DE10085014T1 (en)
GB (1) GB2371138B (en)
WO (1) WO2001022425A1 (en)

Cited By (27)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2005048134A2 (en) * 2002-05-21 2005-05-26 Washington University Intelligent data storage and processing using fpga devices
US7139743B2 (en) 2000-04-07 2006-11-21 Washington University Associative database scanning and information retrieval using FPGA devices
US7181437B2 (en) 2000-04-07 2007-02-20 Washington University Associative database scanning and information retrieval
US7702629B2 (en) 2005-12-02 2010-04-20 Exegy Incorporated Method and device for high performance regular expression pattern matching
US7711844B2 (en) 2002-08-15 2010-05-04 Washington University Of St. Louis TCP-splitter: reliable packet monitoring methods and apparatus for high speed networks
US7716330B2 (en) 2001-10-19 2010-05-11 Global Velocity, Inc. System and method for controlling transmission of data packets over an information network
CN101808027A (en) * 2010-03-31 2010-08-18 哈尔滨工业大学 Data receiving, storing and forwarding device suitable for various ports
CN101673101B (en) * 2009-09-27 2011-06-22 电子科技大学 On-line programming FPGA reconfigurable device
US9672565B2 (en) 2006-06-19 2017-06-06 Ip Reservoir, Llc High speed processing of financial information using FPGA devices
US9990393B2 (en) 2012-03-27 2018-06-05 Ip Reservoir, Llc Intelligent feed switch
US10037568B2 (en) 2010-12-09 2018-07-31 Ip Reservoir, Llc Method and apparatus for managing orders in financial markets
US10062115B2 (en) 2008-12-15 2018-08-28 Ip Reservoir, Llc Method and apparatus for high-speed processing of financial market depth data
US10102260B2 (en) 2012-10-23 2018-10-16 Ip Reservoir, Llc Method and apparatus for accelerated data translation using record layout detection
US10121196B2 (en) 2012-03-27 2018-11-06 Ip Reservoir, Llc Offload processing of data packets containing financial market data
US10146845B2 (en) 2012-10-23 2018-12-04 Ip Reservoir, Llc Method and apparatus for accelerated format translation of data in a delimited data format
US10158377B2 (en) 2008-05-15 2018-12-18 Ip Reservoir, Llc Method and system for accelerated stream processing
US10191974B2 (en) 2006-11-13 2019-01-29 Ip Reservoir, Llc Method and system for high performance integration, processing and searching of structured and unstructured data
US10229453B2 (en) 2008-01-11 2019-03-12 Ip Reservoir, Llc Method and system for low latency basket calculation
US10572824B2 (en) 2003-05-23 2020-02-25 Ip Reservoir, Llc System and method for low latency multi-functional pipeline with correlation logic and selectively activated/deactivated pipelined data processing engines
US10580518B2 (en) 2005-03-03 2020-03-03 Washington University Method and apparatus for performing similarity searching
US10621192B2 (en) 2012-10-23 2020-04-14 IP Resevoir, LLC Method and apparatus for accelerated format translation of data in a delimited data format
US10650452B2 (en) 2012-03-27 2020-05-12 Ip Reservoir, Llc Offload processing of data packets
US10846624B2 (en) 2016-12-22 2020-11-24 Ip Reservoir, Llc Method and apparatus for hardware-accelerated machine learning
US10902013B2 (en) 2014-04-23 2021-01-26 Ip Reservoir, Llc Method and apparatus for accelerated record layout detection
US10942943B2 (en) 2015-10-29 2021-03-09 Ip Reservoir, Llc Dynamic field data translation to support high performance stream data processing
WO2021197182A1 (en) * 2020-04-01 2021-10-07 阿里巴巴集团控股有限公司 Program loading method, device and system and storage medium
US11436672B2 (en) 2012-03-27 2022-09-06 Exegy Incorporated Intelligent switch for processing financial market data

Families Citing this family (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100954010B1 (en) * 2003-11-06 2010-04-20 엘지노텔 주식회사 Programmable multimedia apparatus of data processing system
CN1333349C (en) * 2003-12-23 2007-08-22 华为技术有限公司 System and method for loading on-site programmable gate array
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DE102018123494A1 (en) 2017-11-17 2019-05-23 Samsung Electronics Co., Ltd. MEMORY DEVICE DESIGNED TO UPGRADE A FIELD-PROGRAMMABLE GATE ARRAY, AND OPERATING METHOD THEREFOR

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5600845A (en) * 1994-07-27 1997-02-04 Metalithic Systems Incorporated Integrated circuit computing device comprising a dynamically configurable gate array having a microprocessor and reconfigurable instruction execution means and method therefor
US5619728A (en) * 1994-10-20 1997-04-08 Dell Usa, L.P. Decoupled DMA transfer list storage technique for a peripheral resource controller
US5944813A (en) * 1993-08-03 1999-08-31 Xilinx, Inc. FPGA input output buffer with registered tristate enable

Family Cites Families (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0718751A3 (en) * 1994-12-23 1997-02-12 Ibm Electronic circuit apparatus employing small disk drive with reconfigurable interface

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5944813A (en) * 1993-08-03 1999-08-31 Xilinx, Inc. FPGA input output buffer with registered tristate enable
US5600845A (en) * 1994-07-27 1997-02-04 Metalithic Systems Incorporated Integrated circuit computing device comprising a dynamically configurable gate array having a microprocessor and reconfigurable instruction execution means and method therefor
US5619728A (en) * 1994-10-20 1997-04-08 Dell Usa, L.P. Decoupled DMA transfer list storage technique for a peripheral resource controller

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* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7139743B2 (en) 2000-04-07 2006-11-21 Washington University Associative database scanning and information retrieval using FPGA devices
US7181437B2 (en) 2000-04-07 2007-02-20 Washington University Associative database scanning and information retrieval
US7716330B2 (en) 2001-10-19 2010-05-11 Global Velocity, Inc. System and method for controlling transmission of data packets over an information network
WO2005048134A3 (en) * 2002-05-21 2005-08-04 Univ Washington Intelligent data storage and processing using fpga devices
US10909623B2 (en) 2002-05-21 2021-02-02 Ip Reservoir, Llc Method and apparatus for processing financial information at hardware speeds using FPGA devices
WO2005048134A2 (en) * 2002-05-21 2005-05-26 Washington University Intelligent data storage and processing using fpga devices
US7711844B2 (en) 2002-08-15 2010-05-04 Washington University Of St. Louis TCP-splitter: reliable packet monitoring methods and apparatus for high speed networks
US10929152B2 (en) 2003-05-23 2021-02-23 Ip Reservoir, Llc Intelligent data storage and processing using FPGA devices
US11275594B2 (en) 2003-05-23 2022-03-15 Ip Reservoir, Llc Intelligent data storage and processing using FPGA devices
US10719334B2 (en) 2003-05-23 2020-07-21 Ip Reservoir, Llc Intelligent data storage and processing using FPGA devices
US9898312B2 (en) 2003-05-23 2018-02-20 Ip Reservoir, Llc Intelligent data storage and processing using FPGA devices
US10572824B2 (en) 2003-05-23 2020-02-25 Ip Reservoir, Llc System and method for low latency multi-functional pipeline with correlation logic and selectively activated/deactivated pipelined data processing engines
JP2007524923A (en) * 2003-05-23 2007-08-30 ワシントン ユニヴァーシティー Intelligent data storage and processing using FPGA devices
US10346181B2 (en) 2003-05-23 2019-07-09 Ip Reservoir, Llc Intelligent data storage and processing using FPGA devices
US10957423B2 (en) 2005-03-03 2021-03-23 Washington University Method and apparatus for performing similarity searching
US10580518B2 (en) 2005-03-03 2020-03-03 Washington University Method and apparatus for performing similarity searching
US7702629B2 (en) 2005-12-02 2010-04-20 Exegy Incorporated Method and device for high performance regular expression pattern matching
US10467692B2 (en) 2006-06-19 2019-11-05 Ip Reservoir, Llc High speed processing of financial information using FPGA devices
US10360632B2 (en) 2006-06-19 2019-07-23 Ip Reservoir, Llc Fast track routing of streaming data using FPGA devices
US11182856B2 (en) 2006-06-19 2021-11-23 Exegy Incorporated System and method for routing of streaming data as between multiple compute resources
US10817945B2 (en) 2006-06-19 2020-10-27 Ip Reservoir, Llc System and method for routing of streaming data as between multiple compute resources
US10169814B2 (en) 2006-06-19 2019-01-01 Ip Reservoir, Llc High speed processing of financial information using FPGA devices
US9672565B2 (en) 2006-06-19 2017-06-06 Ip Reservoir, Llc High speed processing of financial information using FPGA devices
US9916622B2 (en) 2006-06-19 2018-03-13 Ip Reservoir, Llc High speed processing of financial information using FPGA devices
US10504184B2 (en) 2006-06-19 2019-12-10 Ip Reservoir, Llc Fast track routing of streaming data as between multiple compute resources
US10191974B2 (en) 2006-11-13 2019-01-29 Ip Reservoir, Llc Method and system for high performance integration, processing and searching of structured and unstructured data
US11449538B2 (en) 2006-11-13 2022-09-20 Ip Reservoir, Llc Method and system for high performance integration, processing and searching of structured and unstructured data
US10229453B2 (en) 2008-01-11 2019-03-12 Ip Reservoir, Llc Method and system for low latency basket calculation
US10411734B2 (en) 2008-05-15 2019-09-10 Ip Reservoir, Llc Method and system for accelerated stream processing
US11677417B2 (en) 2008-05-15 2023-06-13 Ip Reservoir, Llc Method and system for accelerated stream processing
US10965317B2 (en) 2008-05-15 2021-03-30 Ip Reservoir, Llc Method and system for accelerated stream processing
US10158377B2 (en) 2008-05-15 2018-12-18 Ip Reservoir, Llc Method and system for accelerated stream processing
US10062115B2 (en) 2008-12-15 2018-08-28 Ip Reservoir, Llc Method and apparatus for high-speed processing of financial market depth data
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US10949442B2 (en) 2012-10-23 2021-03-16 Ip Reservoir, Llc Method and apparatus for accelerated format translation of data in a delimited data format
US10102260B2 (en) 2012-10-23 2018-10-16 Ip Reservoir, Llc Method and apparatus for accelerated data translation using record layout detection
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US11526531B2 (en) 2015-10-29 2022-12-13 Ip Reservoir, Llc Dynamic field data translation to support high performance stream data processing
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WO2021197182A1 (en) * 2020-04-01 2021-10-07 阿里巴巴集团控股有限公司 Program loading method, device and system and storage medium

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