JP2003510705A - Field programmable gate array hard disk drive - Google Patents

Abstract

(57) [Summary] An FPGA / HD device integrates an FPGA and an HDD storing in-circuit programming for the FPGA, and cooperates with an arbitrary selected interface under the control of a controller embedded in the HDD. By changing the FPGA as described above, it becomes a self-sufficient type. In-circuit programming data is stored directly in selected areas of the HDD, leaving the necessary space for any other data traditionally stored on the HDD. The controller locates specific in-circuit data and places the appropriate soft core in the FPGA upon receiving an instruction identifying the bus to be interfaced in any select operation.

Description

Detailed Description of the Invention

REFERENCE TO RELATED APPLICATION This application is filed under William S. "FIELD invented by Herz
PROGRAMMABLE GATE ARRAY HARD DISK SY
Provisional Application No. 60/154 filed September 20, 1999 under the name "STEM"
881 priority date and will be billed for this priority date. This provisional application is incorporated herein by reference. FIELD OF THE INVENTION The present application relates generally to the field of memory devices incorporating hard disk drives, and in particular can provide various well-configurable interfaces to hard disk drives or processes for such hard disk drives. Regarding the device.

BACKGROUND OF THE INVENTION According to the current state of the art, field programmable gate arrays (FPs)
The possibility of in-circuit programming for GA) is recognized. Generally, this data resides in memory or is sent to the FPGA via the host computer. Finally, this data resides in some storage (RAM, ROM or hard disk, all accessed via host inclusions). This data is used to program the FPGA to perform its particular function.
The actual limit on the number of interfaces is due to the limited memory size and load on the CPU to direct its data to the FPGA.

Such limitations would be particularly important in devices such as the data shuttle disclosed in the related applications incorporated by reference herein. In this application, a single data shuttle is disclosed. This data shuttle is a portable storage of input data streams from a number of sources including television signals, SPDIF format data and information received via a bus such as a USB bus or ATA bus or 1394 bus. It is especially useful when Each of these pieces of information requires its own interface, thus multiplying the number of chips that need to be incorporated, the amount of functional silicon,
Therefore, it increases the cost of such multi-interface products.

SUMMARY OF THE INVENTION It is an object of the present invention to make one assembly compatible with multiple interfaces. In particular, according to the present invention, a considerable number of interface chips have one or more FPGAs.
Replaced by a chip. In particular, in the present invention, a feature of FPGAs is to program the information stored on the associated hard disk. In particular, a feature of the invention is an FPGA integrated with a hard disk drive that stores related in-circuit programming data. Yet another feature is that the FPGA is integrated with the hard disk drive and the programming is modified by the embedded controller of the hard disk drive.

In summary, the FPGA / HD device integrates the FPGA with an HDD that stores the in-circuit programming for the FPGA, and cooperates with any selected interface under the control of a controller embedded in the HDD. It is self-sufficient by modifying the FPGA. As a result, the programming data in the circuit is
The present invention provides the advantage of leaving as much space as needed for any other data stored directly in the selected area of the HDD and traditionally stored in the HDD. The controller is
Upon receipt of an instruction that identifies the bus to be interfaced within any optional operation,
The specific in-circuit data is located and the appropriate soft core is placed in the FPGA. Other features and advantages of the present invention will be apparent to one of ordinary skill in the art who studies the disclosure given in connection with the following drawings.

Detailed Description of the Embodiments The following description describes various hard disk drive (HDD) devices in order to provide various fully configurable interfaces or processors for the HDD devices.
A device for coupling a D device and a field programmable gate array (FPGA) is described. However, the features and advantages of the invention are not limited to the particular block diagrams disclosed herein. This feature can be used with any number of interfaces or processors, and FPGA data can be stored within the area of any size disk drive.

In FIG. 1, the basic element for implementing the present invention is an embedded controller 102.
Preferably, a disk drive assembly 100 having an embedded or closely related field programmable gate array FPGA 104 is provided. FP
As is known in the GA technology field, the functionality of this device 104 may change from time to time based on the data downloaded to the FPGA to demonstrate the particular functionality for its "soft core." For example, in the field of devices that require the use of many interfaces, such as an ATA interface, a 1394 interface, or a USB interface, the FPGA 4 may be needed at any given time based on the data stored by the controller 102. Signal processing structures and functions can be employed.

According to the present invention, this data is stored in the H
It can be stored in a separate partition area 110 of the DD 100. During use of the FPGA, at any time, based on some external control signal, time function, etc., the FPGA is configured to provide a specific interface to the entire device 10 and is also incorporated into the disk drive. The controller 102 can download data from the FPGA data area 110 of the disk drive to the FPGA 104. As soon as the FPGA data is downloaded, the FPGA will serve as that particular programmable device.

Therefore, according to the present invention, any programmable interface from the above identified or unidentified groups is available for assignment to any user as needed. Assigning soft core data to be loaded in a time multiplexed manner or to be unloaded under the control of a single external signal received from an external host computer without the intervention or loading of a further host computer. You can Thus, by homogenizing the HDD device, any manufacturing cost is greatly reduced and the previously required functional silicon required to implement each desired interface is removed.

An example of a board-level device that utilizes many interfaces that can be better implemented by those skilled in the art and can very advantageously incorporate the present invention utilizes the disk storage device shown in FIG. It is a data shuttle.

The data shuttle accepts continuous streams of digital information from various sources and sends the stream of information through various interfaces incorporated within the data shuttle, and further through a bus to a hard disk drive. Send it in. In this figure, inputs from various data devices or sources are shown on the left as well as outputs to potential destinations. If the received data is in analog form, it is digitized, for example as shown in the upper left. In this case, the composite TV video signal 700 and associated audio signal 702 will be output to the appropriate A / D converters 704 and 70.
6 and is sent to the MPEG-2 encoder 710 via the bus.

The output of the MPEG-2 encoder 710 is transferred to the disk processor 714 via the data packetizer 712. The disk processor 714 performs appropriate file management, bus arbitration, content management, and flow management functions so that data can be stored on the local hard disk drive 720. Thus, any desired video input stream is converted, digitized, processed and stored on the data shuttle for selective access. The MPEG encoder and MPEG decoder are
It can be embodied as an FPGA that is reprogrammed under the control of the in-device microprocessor 270 using the data stored in the DD 220. In this way, the actual number of encoder / decoder chips can be substantially reduced.

The data shuttle may also be interfaced to a larger hard disk drive incorporated in the nesting or docking device 760 for the data shuttle. The disk processor 714 can also send the stored digital data from the local disk drive 720 to the nesting disk drive 740 via the ATA bus, which will have a greater capacity. Thus, the data shuttle can be moved from one device to another and input data from one or several data sources can be stored via the various interfaces shown. The data shuttle operates under the control of its own local processor 770 and has a power / monitor 772 and controls 780-784.

Among other interfaces, the data shuttle also has an I / O bus 720 that operates to handle the SPDIF format. The input / output bus 720 is
Extends directly to the data packetizer 712, and then the disk processor 7 via the bus.
It extends to 14. Another SPDIF input 72 for receiving digital audio
2 is an input to the MPEG-2 encoder 710. The output of this MPEG-2 encoder 710 is also sent to the disk processor 714 for storage in the local hard disk 720 or nesting hard disk 740. Digital audio source 722 can also be added to MP3 encoder 724. The output of this MP3 encoder 724 is directly connected to the data packetizer 712 and then to the disk processor 714 so that any data in SPDIF format can be stored and selectively accessed.

A plurality of bidirectional buses including a USB bus 730, a 1394 bus 732, and an ATA bus 734 are similarly provided. The USB bus 730 may be, for example, a bidirectional connection to an MP3 player, a digital camera or a PC. Any of these devices are directly connected to the data packetizer 712 via the USB PHY 740 and the packetizer 742, and their inputs and outputs are connected to the processor 7
14 to the hard disk drive 720. In a similar fashion, 139
4 bus 732 may be connected to a digital video camera or PC or digital VCR via a suitable PHY 744 and packetizer 746, a data packetizer 712 and a disk processor 714. Finally, the ATA bus 734
Flash memory or other data storage can be connected directly to the desk processor 714 and to the disk drive 720.

On the output side, an MP3 decoder 750 is provided whose output is sent to the SPDIF output bus 752 or via an audio processor 754, just as the SPDIF input 722 can be sent via the MP3 encoder 724 for storage. Can be connected to the modulation amplifier 756. This allows RF modulation AV758
, Several alternative output lines are provided with a stereo horn output 760 and an audio output 762. The audio output is typically used with the television output 764 coming through a digital video encoder 766 and an MPEG-2 decoder 768 via a modulation amplifier 756. The MPEG-2 decoder receives video information from the disk processor 714 and depacketizer 712 that can selectively access any file on the local desk 720, as described above. All of these functions are performed under control of the CPU 770, which in this example is a Motorola 823E supported by a power supply 772 and monitor.

These functions are selected, the input / output source and the destination are recognized through the IR controller 780, and the selected functions are displayed on the LCD display on the front of the data shuttle. Both of these are control I / O784 integrated in the data shuttle.
Supported via a bus 786 to control the functions of the CPU 770. Similar to the above, if each bus has a packetizer / depacketizer, the FPG
A can be used. Once the bus is selected, the microprocessor will move from the disk drive to the FP to service the required packetizer / depacketizer.
The data required to program the GA can be downloaded. In this way, the processor board can be substantially simplified without imposing extra load on the host computer. That is because the in-device processor has available time to download core data from the in-device disk drive without contention with its data storage control functions.

Other uses, features and advantages of the invention will be apparent to those of skill in the art upon studying the above disclosure of the invention. Therefore, the scope of the invention should be limited only by the claims.

[Brief description of drawings]

[Figure 1]   It is a schematic block diagram of the basic elements of the present invention.

FIG. 2 is a block diagram of a board level multi-interface product in which the present invention is useful.

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Claims (6)

[Claims] 1. A device comprising a field programmable gate array (FPGA) integrated with a hard disk drive assembly, said hard disk drive assembly further comprising an integrated microprocessor, said hard disk drive assembly A device adapted to store data that configures the field programmable gate array (FPGA) to perform many different functions under the control of the in-device processor without host intervention of the entire device. 2. A hard disk drive assembly having a plurality of interfaces, each interface being connected to the hard disk drive assembly via an encoder or a decoder, wherein at least one of the encoder and the decoder is data stored in the hard disk drive assembly. The apparatus of claim 1 implemented by a single FPGA reprogrammed to handle different interfaces according to. 3. A plurality of interfaces, each interface being connected to the hard disk drive assembly via a packetizer or depacketizer,
The one or more of the packetizer and depacketizer are implemented by a single FPGA programmed to handle a selection of the plurality of interfaces with data stored in the hard disk drive assembly. Equipment. 4. The selected interface for storing a plurality of data sets for programming the FPGA in an identifiable area of the hard disk drive assembly and for transmitting or receiving data from the device. 4. The apparatus of claim 3, further comprising a disk controller responsive to select instructions from the on-board processor to select one of the data sets for programming the FPGA. 5. A device comprising a field programmable gate array (FPGA) integrated with a hard disk drive assembly, said hard disk drive assembly further comprising an integrated microprocessor, said hard disk drive. An assembly is provided for storing data that configures the field programmable gate array (FPGA) to perform many different functions under the control of the in-device processor without host intervention of the entire device. Storing a plurality of data sets for programming the field programmable gate array in an area of the hard disk drive assembly and selecting a selected one of the interfaces for transmitting or receiving data from the device. Identify and select this Wherein F is one of a set of data from the hard disk assembly under the control of the device in the processor was in response to the identification of the interface is
How to program a PGA. 6. A device comprising a field programmable gate array integrated with a hard disk drive assembly, said hard disk drive assembly further comprising an integrated microprocessor, said hard disk drive assembly comprising: A hard disk in a device adapted to store data that configures the field programmable gate array (FPGA) to perform many different functions under the control of the in-device processor without host intervention of the entire device. Storing a plurality of data sets for programming the field programmable gate array in the area of a drive assembly and responsive to the identification of the selected interface, the hard disk assembly under the control of the in-device processor. Or A device comprising means for programming said FPGA with one of these data sets.