KR20020032175A - 와이어 본딩 구조 및 그 방법 - Google Patents
와이어 본딩 구조 및 그 방법 Download PDFInfo
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- KR20020032175A KR20020032175A KR1020000063190A KR20000063190A KR20020032175A KR 20020032175 A KR20020032175 A KR 20020032175A KR 1020000063190 A KR1020000063190 A KR 1020000063190A KR 20000063190 A KR20000063190 A KR 20000063190A KR 20020032175 A KR20020032175 A KR 20020032175A
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- wire
- bonding
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- ball
- bonded
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- 238000000034 method Methods 0.000 title claims abstract description 19
- 239000004065 semiconductor Substances 0.000 claims abstract description 53
- 239000000758 substrate Substances 0.000 claims abstract description 38
- 230000008878 coupling Effects 0.000 description 3
- 238000010168 coupling process Methods 0.000 description 3
- 238000005859 coupling reaction Methods 0.000 description 3
- 238000010586 diagram Methods 0.000 description 2
- 239000000463 material Substances 0.000 description 2
- 230000000149 penetrating effect Effects 0.000 description 2
- 230000004888 barrier function Effects 0.000 description 1
- 230000007547 defect Effects 0.000 description 1
- 230000006866 deterioration Effects 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 238000004519 manufacturing process Methods 0.000 description 1
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Abstract
Description
Claims (4)
- 반도체칩의 입출력패드와 섭스트레이트의 리드가 상호 전기적으로 도통되도록 도전성 와이어가 본딩된 와이어 본딩 구조에 있어서,상기 섭스트레이트의 어느 한 리드에 제1도전성 와이어의 일단이 볼 본딩되고, 상기 제1도전성 와이어의 타단은 상기 반도체칩의 입출력패드에 스티치 본딩되며, 상기 스티치 본딩된 입출력패드에 제2도전성 와이어의 일단이 볼 본딩되며, 상기 제2도전성 와이어의 타단은 섭스트레이트의 다른 리드에 스티치 본딩된 것을 특징으로 하는 와이어 본딩 구조.
- 제1항에 있어서, 상기 반도체칩의 입출력패드에는 와이어볼이 형성되어 있고, 상기 와이어볼 상에 제1도전성 와이어가 스티치 본딩된 것을 특징으로 하는 와이어 본딩 구조.
- 반도체칩의 입출력패드와 섭스트레이트의 리드가 상호 전기적으로 도통되도록 도전성 와이어를 이용하여 본딩하는 와이어 본딩 방법에 있어서,상기 섭스트레이트의 어느 한 리드에 제1도전성 와이어의 일단을 볼 본딩하는 단계와;상기 제1도전성 와이어의 타단을 상기 반도체칩의 입출력패드에 스티치 본딩하는 단계와;상기 스티치 본딩된 입출력패드에 제2도전성 와이어의 일단을 볼 본딩하는 단계와;상기 제2도전성 와이어의 타단을 섭스트레이트의 다른 리드에 스티치 본딩하는 단계를 포함하여 이루어진 와이어 본딩 방법.
- 제3항에 있어서, 상기 제1도전성 와이어의 타단을 반도체칩의 입출력패드 표면에 스티치 본딩하는 단계는, 상기 반도체칩의 입출력패드 표면에 와이어볼을 미리 형성한 후, 상기 와이어볼 상에 스티치 본딩함을 특징으로 하는 와이어 본딩 방법.
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US8008785B2 (en) | 2009-12-22 | 2011-08-30 | Tessera Research Llc | Microelectronic assembly with joined bond elements having lowered inductance |
US9054105B2 (en) | 2012-07-09 | 2015-06-09 | Samsung Electronics Co., Ltd. | Semiconductor package and method for fabricating the same |
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US8008785B2 (en) | 2009-12-22 | 2011-08-30 | Tessera Research Llc | Microelectronic assembly with joined bond elements having lowered inductance |
WO2011087485A3 (en) * | 2009-12-22 | 2012-01-26 | Tessera, Inc | Microelectronic assembly with joined bond elements having lowered inductance |
US8410618B2 (en) | 2009-12-22 | 2013-04-02 | Tessera, Inc. | Microelectronic assembly with joined bond elements having lowered inductance |
US8816514B2 (en) | 2009-12-22 | 2014-08-26 | Tessera, Inc. | Microelectronic assembly with joined bond elements having lowered inductance |
US9054105B2 (en) | 2012-07-09 | 2015-06-09 | Samsung Electronics Co., Ltd. | Semiconductor package and method for fabricating the same |
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