KR20020028462A - Manufacturing method for shallow trench isolation in semiconductor device - Google Patents

Manufacturing method for shallow trench isolation in semiconductor device Download PDF

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Publication number
KR20020028462A
KR20020028462A KR1020000059485A KR20000059485A KR20020028462A KR 20020028462 A KR20020028462 A KR 20020028462A KR 1020000059485 A KR1020000059485 A KR 1020000059485A KR 20000059485 A KR20000059485 A KR 20000059485A KR 20020028462 A KR20020028462 A KR 20020028462A
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South Korea
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substrate
oxide film
oxide layer
trench
density plasma
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KR1020000059485A
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Korean (ko)
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최명규
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박종섭
주식회사 하이닉스반도체
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Priority to KR1020000059485A priority Critical patent/KR20020028462A/en
Publication of KR20020028462A publication Critical patent/KR20020028462A/en

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76—Making of isolation regions between components
    • H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
    • H01L21/76224—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using trench refilling with dielectric materials
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02041—Cleaning
    • H01L21/02057—Cleaning during device manufacture
    • H01L21/0206—Cleaning during device manufacture during, before or after processing of insulating layers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02107—Forming insulating materials on a substrate
    • H01L21/02225—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer
    • H01L21/0226—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process
    • H01L21/02263—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process deposition from the gas or vapour phase
    • H01L21/02271—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process deposition from the gas or vapour phase deposition by decomposition or reaction of gaseous or vapour phase compounds, i.e. chemical vapour deposition

Abstract

PURPOSE: A method for fabricating a shallow trench isolation structure of a semiconductor device is provided to prevent a cusped part of a substrate from being exposed without an additional process, by depositing a thermal oxide layer to restore the substrate damaged by a dry etch process and by making the thickness of a high density plasma oxide layer higher than its peripheral portion by 400 angstrom. CONSTITUTION: A hard mask pattern wherein an oxide layer(2) and a nitride layer are stacked is formed on a substrate(1). A trench is formed in the substrate by an etch process using the hard mask pattern as an etch mask. The first cleaning process is performed regarding the resultant structure in a temperature atmosphere of 50 deg.C for 10 minutes while using a cleaning solution wherein NH4OH, H2O2 and H2O are mixed at a ratio of 1:5:50. The second cleaning process is performed regarding the resultant structure for 6 minutes while using a cleaning solution wherein HF and H2O are mixed at a ratio of 99:1. A thermal oxide layer(4) is deposited at a temperature of 1050-1200 deg.C. The high density plasma oxide layer(5) is deposited on the resultant structure, and is planarized to make the high density plasma oxide layer located in the trench have a thickness higher than its peripheral portion by 400 angstrom.

Description

반도체 장치의 얕은 트랜치 분리구조 제조방법{MANUFACTURING METHOD FOR SHALLOW TRENCH ISOLATION IN SEMICONDUCTOR DEVICE}Manufacturing method of shallow trench isolation structure of semiconductor device {MANUFACTURING METHOD FOR SHALLOW TRENCH ISOLATION IN SEMICONDUCTOR DEVICE}

본 발명은 얕은 반도체 장치의 얕은 트랜치 분리구조 제조방법에 관한 것으로, 특히 공정조건을 변경하여 트랜치 표면의 손상을 방지하고, 트랜치 상부의 첨점부를 완만하게 형성할 수 있는 반도체 장치의 얕은 트랜치 분리구조 제조방법에 관한 것이다.The present invention relates to a method for manufacturing a shallow trench isolation structure of a shallow semiconductor device, and in particular, to manufacture a shallow trench isolation structure of a semiconductor device capable of changing the process conditions to prevent damage to the trench surface and smoothly forming peaks on the trench. It is about a method.

도1a 내지 도1c는 종래 반도체 장치의 얕은 트랜치 분리구조 제조공정 수순단면도로서, 이에 도시한 바와 같이 기판(1)의 상부에 포토레지스트 또는 하드마스크(2)를 형성하여 상기 기판(1)의 일부영역만을 노출시킨 후, 건식식각방법으로 3500Å 깊이의 트랜치를 형성하는 단계(도1a)와; 상기 포토레지스트 또는 하드마스크(2)를 제거하고, 트랜치가 형성된 기판(1)의 상부전면에 고밀도 플라즈마 산화막(3)을 증착하는 단계(도1b)와; 상기 고밀도 플라즈마 산화막(3)을 평탄화하여 상기 트랜치 내에 분리구조(4)를 형성하는 단계(도1c)로 구성된다.1A through 1C are cross-sectional views of a process of manufacturing a shallow trench isolation structure of a conventional semiconductor device. As shown in FIG. 1A through FIG. 1C, a photoresist or a hard mask 2 is formed on a portion of the substrate 1. After exposing only the region, forming a trench of 3500 mm depth by a dry etching method (FIG. 1A); Removing the photoresist or hard mask (2) and depositing a high density plasma oxide film (3) on the upper surface of the substrate (1) in which the trench is formed (FIG. Planarizing the high-density plasma oxide film 3 to form an isolation structure 4 in the trench (FIG. 1C).

이하, 상기와 같은 종래 반도체 장치의 얕은 트랜치 분리구조 제조방법을 좀 더 상세히 설명한다.Hereinafter, a method of manufacturing a shallow trench isolation structure of a conventional semiconductor device as described above will be described in more detail.

먼저, 도1a에 도시한 바와 같이 반도체 기판(1)의 상부에 포토레지스트 패턴을 직접 형성하거나, 산화막 또는 산화막/질화막을 순차적으로 증착하고, 그 증착된 물질을 사진식각공정으로 패터닝하여 반도체 기판(1)의 일부를 노출시키는 하드마스크 패턴(2)을 형성한다.First, as shown in FIG. 1A, a photoresist pattern is directly formed on the semiconductor substrate 1, or an oxide film or an oxide film / nitride film is sequentially deposited, and the deposited material is patterned by a photolithography process. A hard mask pattern 2 exposing a part of 1) is formed.

그 다음, 건식식각법을 사용하여 상기 노출된 기판(1)을 식각하여 트랜치를 형성한다. 이때 트랜치의 형성으로 트랜치의 상부측면의 기판(1)은 첨점을 갖게되며, 이 부분을 둥글게 만드는 추가공정이 없는한 누설전류의 발생 등, 이후의 공정에서 형성하는 반도체 소자의 특성을 열화시키는 요인이 된다.The exposed substrate 1 is then etched using dry etching to form a trench. At this time, the formation of the trench causes the substrate 1 on the upper side of the trench to have a sharp point, and deteriorates the characteristics of the semiconductor device formed in a subsequent process, such as generation of a leakage current unless there is an additional process of rounding the portion. Becomes

그 다음, 도1b에 도시한 바와 같이 상기 하드마스크(2)를 제거하고, 고밀도 플라즈마 산화막(3)을 상기 기판(1)의 상부전면에 상기 트랜치가 모두 채워질정도로 증착한다.Next, as shown in FIG. 1B, the hard mask 2 is removed, and a high density plasma oxide film 3 is deposited to fill all of the trenches on the upper surface of the substrate 1.

그 다음, 도1c에 도시한 바와 같이 상기 증착된 고밀도 플라즈마 산화막(3)을 화학적 기계적 연마법을 이용하여 평탄화하여 상기 트랜치내에 분리구조(4)를 형성한다.Then, as shown in Fig. 1C, the deposited high density plasma oxide film 3 is planarized by chemical mechanical polishing to form a separation structure 4 in the trench.

상기한 바와 같이 종래 반도체 장치의 얕은 트랜치 분리구조 제조방법은 트랜치의 상부 측면측 기판이 첨점을 갖도록 형성되고, 트랜치 분리구조의 형성시 그 첨점부가 노출됨으로써, 전계의 집중에 의한 누설전류가 발생하여 반도체 장치의 특성을 열화시키는 문제점이 있으며, 이를 해결하기 위해 추가공정으로 상기 첨점부를 완만하게 식각하는 경우 공정이 복잡해지는 문제점이 있었다.As described above, in the method of manufacturing a shallow trench isolation structure of a conventional semiconductor device, the upper side side substrate of the trench is formed to have a peak, and when the trench isolation structure is formed, the peak portion is exposed, so that a leakage current due to concentration of an electric field is generated. There is a problem of deteriorating the characteristics of the semiconductor device, and in order to solve this problem, when the etched portion is gently etched as an additional process, the process becomes complicated.

이와 같은 문제점을 감안한 본 발명은 추가공정없이 공정조건을 변경하여 기판의 첨점부가 노출되지 않도록 하는 반도체 장치의 얕은 트랜치 분리구조 제조방법을 제공함에 그 목적이 있다.It is an object of the present invention to provide a method of manufacturing a shallow trench isolation structure of a semiconductor device in which the process conditions are not exposed by changing the process conditions without an additional process.

도1a 내지 도1c는 종래 반도체 장치의 얕은 트랜치 분리구조 제조공정 수순단면도.1A to 1C are cross-sectional views of a process for manufacturing a shallow trench isolation structure of a conventional semiconductor device.

도2a 내지 도2e는 본 발명 반도체 장치의 얕은 트랜치 분리구조 제조공정 수순단면도.2A to 2E are cross-sectional views of a shallow trench isolation structure manufacturing process of the semiconductor device according to the present invention.

*도면의 주요 부분에 대한 부호의 설명** Description of the symbols for the main parts of the drawings *

1:기판2:산화막1: Substrate 2: Oxide Film

3:질화막4:열산화막3: nitride film 4: thermal oxide film

5:고밀도 플라즈마 산화막5: high density plasma oxide film

상기와 같은 목적은 기판의 상부에 산화막과 질화막이 적층된 하드마스크 패턴을 형성하는 단계와; 상기 하드마스크 패턴을 식각마스크로 하는 식각공정으로 상기 기판에 트랜치를 형성하는 단계와; 상기 구조를 NH4OH, H2O2, H2O가 1:5:50 으로 혼합된 세정용액을 사용하여 50℃의 온도분위기에서 10분간 1차 세정하고, 다시 HF와 H2O가 99:1로 혼합된 용액으로 6분간 2차 세정한 후, 1050 ~ 1200℃의 증착온도를 갖는 열산화막을 증착하는 단계와; 상기 구조의 상부전면에 고밀도 플라즈마 산화막을 증착한 후, 평탄화하여 상기 트랜치 내에 위치하는 고밀도 플라즈마 산화막의 두께가 주변부보다 400Å 높게 형성되도록 하는 단계로 구성함으로써 달성되는 것으로, 이와 같은 본 발명을 첨부한 도면을 참조하여 상세히 설명하면 다음과 같다.The above object is to form a hard mask pattern in which an oxide film and a nitride film are stacked on the substrate; Forming a trench in the substrate by an etching process using the hard mask pattern as an etching mask; The structure was first washed in a temperature atmosphere of 50 ° C. for 10 minutes using a cleaning solution mixed with NH 4 OH, H 2 O 2 , and H 2 O 1: 5: 50, and HF and H 2 O were 99%. Performing a second rinse for 6 minutes with the solution mixed at 1: and then depositing a thermal oxide film having a deposition temperature of 1050 to 1200 ° C .; A high density plasma oxide film is deposited on the upper surface of the structure, and then planarized so that the thickness of the high density plasma oxide film positioned in the trench is formed to be 400 Å higher than the periphery. When described in detail with reference to as follows.

도2a 내지 도2e는 본 발명 반도체 장치의 얕은 트랜치 분리구조 제조공정 수순단면도로서, 이에 도시한 바와 같이 기판(1)의 상부전면에 산화막(2)과 질화막(3)을 순차적으로 증착한 후, 사진식각공정으로 상기 질화막(3)과 산화막(2)의 일부를 제거하여 상기 기판(1)의 일부를 노출시킨 후, 상기 질화막(3)을 식각마스크로 하는 식각공정으로 상기 노출된 기판(1)을 식각하여 트랜치를 형성하는 단계(도2a)와; 상기 구조를 세정한 후, 열산화막(4)을 상기 트랜치 내에 증착하는 단계(도2b)와; 상기 구조의 상부전면에 고밀도 플라즈마 산화막(5)을 증착하고, 어닐링하는 단계(도2c)와; 상기 트랜치 내에 위치하는 고밀도 플라즈마 산화막(5)을 주변부 보다 400Å 높은 상태가 되도록 평탄화하는 단계(도2d)와; 상기 노출된 질화막(3)을 제거하는 단계(도2e)로 이루어진다.2A to 2E are cross-sectional views of a process for manufacturing a shallow trench isolation structure of a semiconductor device according to the present invention. As shown therein, an oxide film 2 and a nitride film 3 are sequentially deposited on an upper surface of a substrate 1. The photolithography process removes a portion of the nitride film 3 and the oxide film 2 to expose a portion of the substrate 1, and then exposes the exposed substrate 1 by an etching process of using the nitride film 3 as an etching mask. Etching to form a trench (FIG. 2A); After cleaning the structure, depositing a thermal oxide film 4 into the trench (FIG. 2B); Depositing and annealing a high density plasma oxide film (5) on the upper surface of the structure (FIG. 2C); Planarizing the high density plasma oxide film (5) located in the trench so as to be 400 kHz higher than the peripheral portion (FIG. 2D); The exposed nitride film 3 is removed (FIG. 2E).

이하, 상기와 같은 본 발명 반도체 장치의 얕은 트랜치 분리구조 제조방법을 좀 더 상세히 설명한다.Hereinafter, a method of manufacturing a shallow trench isolation structure of the semiconductor device as described above will be described in more detail.

먼저, 도2a에 도시한 바와 같이 기판(1)의 상부전면에 산화막(2)과 질화막(3)을 순차적으로 증착한다. 이때의 산화막(2)은 140Å, 질화막(3)은 1000Å이 되도록 한다.First, as shown in FIG. 2A, an oxide film 2 and a nitride film 3 are sequentially deposited on the upper surface of the substrate 1. At this time, the oxide film 2 is 140 kPa and the nitride film 3 is 1000 kPa.

그 다음, 사진식각공정을 통해 상기 질화막(3)의 일부와 그 하부의 산화막(2)을 식각하여 기판(1)의 일부를 노출시킨다.Subsequently, a portion of the nitride film 3 and an oxide film 2 below it are etched through a photolithography process to expose a portion of the substrate 1.

그 다음, 상기 질화막(3)을 식각마스크로 사용하는 건식식각공정으로 노출된 기판(1)을 식각하여 기판(1)의 표면으로부터의 깊이가 3500Å이 되는 트랜치를 형성한다.Subsequently, the substrate 1 exposed by the dry etching process using the nitride film 3 as an etching mask is etched to form a trench having a depth of 3500 kPa from the surface of the substrate 1.

그 다음, 도2b에 도시한 바와 같이 NH4OH, H2O2, H2O가 1:5:50 으로 혼합된 세정용액을 사용하여 50℃의 온도분위기에서 10분간 1차 세정하고, 다시 HF와 H2O가 99:1로 혼합된 용액으로 6분간 2차 세정하여 상기 식각에 의한 트랜치의 손상을 복원한다.Then, as shown in Figure 2b, using a washing solution mixed with NH 4 OH, H 2 O 2 , H 2 O 1: 5: 50, the first wash in a temperature atmosphere of 50 ℃ 10 minutes, and again Secondary cleaning with a solution mixed with HF and H 2 O 99: 1 for 6 minutes restores damage to the trench due to the etching.

그 다음, 상기 트랜치에 100Å 두께의 열산화막(4)을 증착한다. 이때의 증착조건은 그 온도가 1050 내지 1200℃의 온도범위에서 증착되도록 한다.Next, a thermal oxide film 4 having a thickness of 100 Å is deposited on the trench. At this time, the deposition conditions are such that the temperature is deposited in a temperature range of 1050 to 1200 ℃.

그 다음, 도2c에 도시한 바와 같이 상기 구조의 상부에 6000Å의 두께를 갖는 고밀도 플라즈마 산화막(5)을 증착한다.Then, as shown in Fig. 2C, a high density plasma oxide film 5 having a thickness of 6000 Å is deposited on top of the structure.

그 다음, 상기 구조를 질소분위기에서 1150 내지 1200℃로 어닐링한다.The structure is then annealed at 1150 to 1200 ° C. in a nitrogen atmosphere.

그 다음, 도2d에 도시한 바와 같이 상기 증착된 고밀도 플라즈마 산화막(5)을 평탄화하여 트랜치의 상부측 산화막(5)이 주변부보다 400Å이상 높게 형성되도록 한다.Then, as shown in FIG. 2D, the deposited high density plasma oxide film 5 is planarized so that the oxide film 5 on the upper side of the trench is formed 400 kV or more higher than the peripheral portion.

그 다음, 도2e에 도시한 바와 같이 상기 질화막(3)을 제거한다.Then, the nitride film 3 is removed as shown in Fig. 2E.

상기한 바와 같이 본 발명은 열산화막의 증착으로 건식식각에 의한 기판의 손상을 복원하고, 고밀도 플라즈마 산화막의 두께를 주변부보다 400Å 높게 유지함으로써, 기판의 첨점부가 노출되는 것을 추가공정 없이 방지하여, 반도체 장치의 특성이 열화되는 것을 방지하는 효과가 있다.As described above, the present invention restores damage to the substrate by dry etching by depositing a thermal oxide film, and maintains the thickness of the high-density plasma oxide film 400 보다 higher than the periphery, thereby preventing the exposed portion of the substrate from being exposed to the semiconductor. There is an effect of preventing the deterioration of the characteristics of the device.

Claims (1)

기판의 상부에 산화막과 질화막이 적층된 하드마스크 패턴을 형성하는 단계와; 상기 하드마스크 패턴을 식각마스크로 하는 식각공정으로 상기 기판에 트랜치를 형성하는 단계와; 상기 구조를 NH4OH, H2O2, H2O가 1:5:50 으로 혼합된 세정용액을 사용하여 50℃의 온도분위기에서 10분간 1차 세정하고, 다시 HF와 H2O가 99:1로 혼합된 용액으로 6분간 2차 세정한 후, 1050 ~ 1200℃의 증착온도를 갖는 열산화막을 증착하는 단계와; 상기 구조의 상부전면에 고밀도 플라즈마 산화막을 증착한 후, 평탄화하여 상기 트랜치 내에 위치하는 고밀도 플라즈마 산화막의 두께가 주변부보다 400Å 높게 형성되도록 하는 단계로 이루어진 것을 특징으로 하는 반도체 장치의 얕은 트랜치 분리구조 제조방법.Forming a hard mask pattern in which an oxide film and a nitride film are stacked on the substrate; Forming a trench in the substrate by an etching process using the hard mask pattern as an etching mask; The structure was first washed in a temperature atmosphere of 50 ° C. for 10 minutes using a cleaning solution mixed with NH 4 OH, H 2 O 2 , and H 2 O 1: 5: 50, and HF and H 2 O were 99%. Performing a second rinse for 6 minutes with the solution mixed at 1: and then depositing a thermal oxide film having a deposition temperature of 1050 to 1200 ° C .; And depositing a high density plasma oxide film on the upper surface of the structure, and then planarizing it so that a thickness of the high density plasma oxide film positioned in the trench is formed to be 400 Å higher than a peripheral portion. .
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