KR20020018606A - 테이퍼된 랜딩을 갖는 구조 및 그 제조 방법 - Google Patents

테이퍼된 랜딩을 갖는 구조 및 그 제조 방법 Download PDF

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Publication number
KR20020018606A
KR20020018606A KR1020010053303A KR20010053303A KR20020018606A KR 20020018606 A KR20020018606 A KR 20020018606A KR 1020010053303 A KR1020010053303 A KR 1020010053303A KR 20010053303 A KR20010053303 A KR 20010053303A KR 20020018606 A KR20020018606 A KR 20020018606A
Authority
KR
South Korea
Prior art keywords
layer
region
conductive
thick portion
landing
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Withdrawn
Application number
KR1020010053303A
Other languages
English (en)
Korean (ko)
Inventor
도니스테판워드
해리스에드워드벨든
머천트세일리시맨신
Original Assignee
추후기재
에이저 시스템즈 가디언 코포레이션
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 추후기재, 에이저 시스템즈 가디언 코포레이션 filed Critical 추후기재
Publication of KR20020018606A publication Critical patent/KR20020018606A/ko
Withdrawn legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D1/00—Resistors, capacitors or inductors
    • H10D1/60—Capacitors
    • H10D1/68—Capacitors having no potential barriers
    • H10D1/692—Electrodes
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W20/00—Interconnections in chips, wafers or substrates
    • H10W20/40—Interconnections external to wafers or substrates, e.g. back-end-of-line [BEOL] metallisations or vias connecting to gate electrodes
    • H10W20/495—Capacitive arrangements or effects of, or between wiring layers
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W20/00—Interconnections in chips, wafers or substrates
    • H10W20/40—Interconnections external to wafers or substrates, e.g. back-end-of-line [BEOL] metallisations or vias connecting to gate electrodes
    • H10W20/495—Capacitive arrangements or effects of, or between wiring layers
    • H10W20/496—Capacitor integral with wiring layers

Landscapes

  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
  • Semiconductor Integrated Circuits (AREA)
KR1020010053303A 2000-08-31 2001-08-31 테이퍼된 랜딩을 갖는 구조 및 그 제조 방법 Withdrawn KR20020018606A (ko)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US65349200A 2000-08-31 2000-08-31
US09/653492 2000-08-31

Publications (1)

Publication Number Publication Date
KR20020018606A true KR20020018606A (ko) 2002-03-08

Family

ID=24621097

Family Applications (1)

Application Number Title Priority Date Filing Date
KR1020010053303A Withdrawn KR20020018606A (ko) 2000-08-31 2001-08-31 테이퍼된 랜딩을 갖는 구조 및 그 제조 방법

Country Status (4)

Country Link
JP (1) JP2002124576A (https=)
KR (1) KR20020018606A (https=)
GB (1) GB2371408B (https=)
TW (1) TW582090B (https=)

Families Citing this family (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP4949656B2 (ja) * 2005-08-12 2012-06-13 ルネサスエレクトロニクス株式会社 半導体装置およびその製造方法
US11869725B2 (en) 2021-11-30 2024-01-09 Texas Instruments Incorporated Multi-stacked capacitor

Family Cites Families (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5838605A (en) * 1996-03-20 1998-11-17 Ramtron International Corporation Iridium oxide local interconnect
US6114766A (en) * 1997-12-18 2000-09-05 Advanced Micro Devices, Inc. Integrated circuit with metal features presenting a larger landing area for vias

Also Published As

Publication number Publication date
GB2371408A (en) 2002-07-24
GB2371408B (en) 2004-12-22
JP2002124576A (ja) 2002-04-26
TW582090B (en) 2004-04-01
GB0121205D0 (en) 2001-10-24

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Legal Events

Date Code Title Description
PA0109 Patent application

Patent event code: PA01091R01D

Comment text: Patent Application

Patent event date: 20010831

PG1501 Laying open of application
PC1203 Withdrawal of no request for examination
WITN Application deemed withdrawn, e.g. because no request for examination was filed or no examination fee was paid