KR20020017496A - Semiconductor package and its manufacturing method - Google Patents

Semiconductor package and its manufacturing method Download PDF

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Publication number
KR20020017496A
KR20020017496A KR1020000050859A KR20000050859A KR20020017496A KR 20020017496 A KR20020017496 A KR 20020017496A KR 1020000050859 A KR1020000050859 A KR 1020000050859A KR 20000050859 A KR20000050859 A KR 20000050859A KR 20020017496 A KR20020017496 A KR 20020017496A
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semiconductor chip
semiconductor
substrate
input
connection means
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KR1020000050859A
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KR100633884B1 (en
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이기욱
하선호
정지영
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마이클 디. 오브라이언
앰코 테크놀로지 코리아 주식회사
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Priority to KR1020000050859A priority Critical patent/KR100633884B1/en
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/03—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes
    • H01L25/04—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers
    • H01L25/065—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L27/00
    • H01L25/0657—Stacked arrangements of devices
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/495—Lead-frames or other flat leads
    • H01L23/49572—Lead-frames or other flat leads consisting of thin flexible metallic tape with or without a film carrier
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32135—Disposition the layer connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
    • H01L2224/32145—Disposition the layer connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being stacked
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73251—Location after the connecting process on different surfaces
    • H01L2224/73265—Layer and wire connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/91—Methods for connecting semiconductor or solid state bodies including different methods provided for in two or more of groups H01L2224/80 - H01L2224/90
    • H01L2224/92—Specific sequence of method steps
    • H01L2224/922—Connecting different surfaces of the semiconductor or solid-state body with connectors of different types
    • H01L2224/9222—Sequential connecting processes
    • H01L2224/92242—Sequential connecting processes the first connecting process involving a layer connector
    • H01L2224/92247—Sequential connecting processes the first connecting process involving a layer connector the second connecting process involving a wire connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/1015—Shape
    • H01L2924/10155—Shape being other than a cuboid
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/1015—Shape
    • H01L2924/10155—Shape being other than a cuboid
    • H01L2924/10158—Shape being other than a cuboid at the passive surface
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181—Encapsulation

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  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
  • Lead Frames For Integrated Circuits (AREA)

Abstract

PURPOSE: A semiconductor package and a fabricating method thereof are provided to laminate a multitude of semiconductor chip having different sizes. CONSTITUTION: The first semiconductor chip(1) has the first side(1a) and the second side(1b). The first and the second sides(1a,1b) have a planar shape, respectively. A multitude of input/output pad(1c) is formed on the second side(1b) of the first semiconductor chip(1). The second semiconductor chip(2) has the first side(2a), the second side(2b), and the third side(2c). The first and the second sides(2a,2b) of the second semiconductor(2) have a planar shape, respectively. The third side(2d) is formed between the first and the second sides(2a,2b). The first side(2a) of the second semiconductor chip(2) is adhered to the second side(1b) of the first semiconductor chip(1). A substrate(S) is mounted on a mother board. The substrate(S) is adhered to the first side(1a) of the first semiconductor chip(1). The substrate(S) is connected electrically with the first and the second semiconductor chips(1,2) by an electric connection portion(30). A sealant is used for sealing the first and second semiconductor chips(1,2), the electric connection portion(30), and a part of the substrate(S).

Description

반도체패키지 및 그 제조 방법{Semiconductor package and its manufacturing method}Semiconductor package and its manufacturing method

본 발명은 반도체패키지 및 그 제조 방법에 관한 것으로, 더욱 상세하게 설명하면 다수의 반도체칩을 적층한 적층형 반도체패키지 및 그 제조 방법에 관한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor package and a method of manufacturing the same, and more particularly, to a stacked semiconductor package in which a plurality of semiconductor chips are stacked and a method of manufacturing the same.

통상 반도체패키지는 반도체칩을 외부 환경으로부터 안전하게 보호함은 물론, 그 반도체칩과 마더보드(Mother Board)와의 전기적 신호가 용이하게 교환되도록 한 것을 말한다.In general, the semiconductor package not only protects the semiconductor chip from the external environment, but also means that the electrical signal between the semiconductor chip and the motherboard is easily exchanged.

최근에는 상기한 반도체패키지 내부에 다수의 반도체칩을 적층함으로써 고기능화를 구현한 적층형 반도체패키지가 출시되고 있으며, 이러한 종래의 통상적인 적층형 반도체패키지(100')를 도1에 도시하였다.Recently, a multilayer semiconductor package having high functionality by stacking a plurality of semiconductor chips inside the semiconductor package has been released. Such a conventional multilayer semiconductor package 100 'is shown in FIG.

도시된 바와 같이 통상 수지층(18')을 중심으로 상,하면에 본드핑거(20a') 및 볼랜드(20b')를 갖는 회로패턴(20')이 형성되어 있고, 상기 회로패턴(20')의 표면은 커버코트(23')로 코팅된 회로기판(16')이 구비되어 있다. 또한, 상기 회로기판(16')의 상면 중앙부에는 제1반도체칩(2')이 접착층에 의해 접착되어 있고, 상기 제1반도체칩(2')의 상면에는 제2반도체칩(6')이 접착층으로 접착되어 있다. 물론, 상기 제1반도체칩(2') 및 제2반도체칩(6')의 상면에는 다수의 입출력패드(4',8')가 형성되어 있다. 상기 제1반도체칩(2') 및 제2반도체칩(6')의 입출력패드(4',8')는 각각 회로기판(16')에 형성된 회로패턴(20')중 본드핑거(20a')에 도전성와이어(60')로 본딩되어 있다. 또한, 제1반도체칩(2'), 제2반도체칩(6'), 도전성와이어(60') 및 회로기판(16')의 상면은 봉지재(40')로 봉지되어 있다. 상기 회로기판(16')의 하면에 형성된 회로패턴(20')중 볼랜드(20b')에는 다수의 도전성볼(50')이 융착되어 있으며, 이 도전성볼(50')이 차후 마더보드의 소정 패턴에 본딩된다. 도면중 미설명 부호 20c'는 도전성 비아홀이다.As shown, a circuit pattern 20 'having a bond finger 20a' and a borland 20b 'is formed on the upper and lower surfaces of the resin layer 18', and the circuit pattern 20 'is formed. The surface of the circuit board 16 'is coated with a cover coat 23'. In addition, the first semiconductor chip 2 'is bonded to the center of the upper surface of the circuit board 16' by an adhesive layer, and the second semiconductor chip 6 'is attached to the upper surface of the first semiconductor chip 2'. It is bonded by an adhesive layer. Of course, a plurality of input / output pads 4 'and 8' are formed on the upper surfaces of the first semiconductor chip 2 'and the second semiconductor chip 6'. The I / O pads 4 'and 8' of the first semiconductor chip 2 'and the second semiconductor chip 6' are bonded fingers 20a 'of the circuit patterns 20' formed on the circuit board 16 ', respectively. Is bonded to the conductive wire 60 '. In addition, the upper surface of the first semiconductor chip 2 ', the second semiconductor chip 6', the conductive wire 60 ', and the circuit board 16' is sealed with an encapsulant 40 '. A plurality of conductive balls 50 'are fused to the ball lands 20b' among the circuit patterns 20 'formed on the bottom surface of the circuit board 16', and the conductive balls 50 'are subsequently fixed on the motherboard. Bonded to the pattern. In the figure, reference numeral 20c 'denotes a conductive via hole.

이러한 반도체패키지(100')는 제1반도체칩(2') 및 제2반도체칩(6')의 전기적 신호가 도전성와이어(60'), 회로기판(16')의 본드핑거(20a'), 도전성 비아홀(20c'), 볼랜드 (20b') 및 도전성볼(50')을 통해서 마더보드와 교환되며, 두개의 반도체칩이 적층된 상태이므로 반도체패키지가 고용량, 고기능화되고 또한 실장밀도를 높일 수 있는 장점이 있다.In the semiconductor package 100 ', the electrical signals of the first semiconductor chip 2' and the second semiconductor chip 6 'are transmitted to the conductive wire 60', the bond finger 20a 'of the circuit board 16', It is exchanged with the motherboard through the conductive via hole 20c ', the borland 20b', and the conductive ball 50 ', and since the two semiconductor chips are stacked, the semiconductor package can have high capacity, high functionality, and high mounting density. There is an advantage.

그러나, 상기 제1반도체칩의 입출력패드에 본딩되는 도전성와이어와의 접촉을 피하기 위해, 상기 제2반도체칩의 넓이 또는 부피가 상기 제1반도체칩의 넓이 또는 부피보다 반듯이 작아야 하는 단점이 있다. 즉, 상기 제2반도체칩의 부피가 제1반도체칩의 부피와 같거나 클 경우에는 그 제2반도체칩의 저면과 도전성와이어가 상호 쇼트됨으로써 제1반도체칩의 전기적 기능이 마비되는 문제가 있어, 반듯이 그 제2반도체칩의 크기가 제1반도체칩의 크기보다 작아야 한다.However, in order to avoid contact with conductive wires bonded to the input / output pads of the first semiconductor chip, an area or volume of the second semiconductor chip must be smaller than the width or volume of the first semiconductor chip. That is, when the volume of the second semiconductor chip is equal to or larger than the volume of the first semiconductor chip, the bottom surface of the second semiconductor chip and the conductive wire are shorted to each other, thereby causing paralysis of the electrical function of the first semiconductor chip. On the contrary, the size of the second semiconductor chip should be smaller than that of the first semiconductor chip.

이러한 문제는 동일한 크기의 반도체칩을 다수 적층하여야 하는 메모리 반도체패키지(예를 들면 다수의 DRAM을 적층한 반도체패키지)에 적용할 수 없어, 패키징할 수 있는 반도체칩의 종류를 극히 제한시키고 있다.Such a problem cannot be applied to a memory semiconductor package (for example, a semiconductor package in which a plurality of DRAMs are stacked) in which a plurality of semiconductor chips of the same size must be stacked, thereby limiting the types of semiconductor chips that can be packaged.

따라서 본 발명은 상기와 같은 종래의 문제점을 해결하기 위해 안출한 것으로, 동일하거나 또는 더 큰 크기의 반도체칩을 적층할 수 있는 반도체패키지 및 그 제조 방법을 제공하는데 있다.Accordingly, the present invention has been made to solve the above-mentioned conventional problems, to provide a semiconductor package and a method of manufacturing the same or larger semiconductor chips can be stacked.

도1은 종래의 반도체패키지를 도시한 단면도이다.1 is a cross-sectional view showing a conventional semiconductor package.

도2a 내지 도2c는 본 발명에 의한 반도체패키지로서, 봉지재가 제거된 상태를 도시한 상태도이다.2A to 2C are state diagrams showing a state in which a sealing material is removed as a semiconductor package according to the present invention.

도3a 및 도3b는 본 발명에 의한 반도체패키지의 일례를 도시한 단면도이다.3A and 3B are sectional views showing an example of a semiconductor package according to the present invention.

도4a 내지 도4f는 본 발명에 의한 반도체패키지의 제조 방법을 도시한 설명도이다.4A to 4F are explanatory views showing a method of manufacturing a semiconductor package according to the present invention.

도5a 및 도5b는 본 발명에 의한 반도체패키지의 제조 방법중 웨이퍼에서 반도체칩을 소잉하는 상태를 도시한 사시도이다.5A and 5B are perspective views showing a state of sawing a semiconductor chip from a wafer in the method of manufacturing a semiconductor package according to the present invention.

도6a 및 도6b는 도5b에서 사용되는 블레이드의 예를 도시한 단면도이다.6A and 6B are sectional views showing an example of the blade used in Fig. 5B.

- 도면중 주요 부호에 대한 설명 --Description of the main symbols in the drawings-

101,102; 본 발명에 의한 반도체패키지101,102; Semiconductor package according to the present invention

1; 제1반도체칩 1a,2a,11a,70a; 제1면One; First semiconductor chips 1a, 2a, 11a, 70a; Front page

1b,2b,11b,70b; 제2면 1c,2c; 입출력패드1b, 2b, 11b, 70b; Second page 1c, 2c; I / O pad

2; 제2반도체칩 2d; 제3면2; Second semiconductor chip 2d; Page 3

10; 인쇄회로기판 11; 수지층10; Printed circuit board 11; Resin layer

12; 회로패턴 12a; 본드핑거12; Circuit pattern 12a; Bondfinger

12b; 볼랜드 13; 비아홀12b; Borland 13; Via Hole

14; 커버코트 20; 접착층14; Covercoat 20; Adhesive layer

30; 접속수단 50; 봉지재30; Connecting means 50; Encapsulant

60; 도전성볼 70; 리드60; Conductive ball 70; lead

71a; 랜드 71b; 본드핑거71a; Land 71b; Bondfinger

상기한 목적을 달성하기 위해 본 발명에 의한 반도체패키지는 대략 평면인 제1면과 제2면을 가지고, 상기 제2면에는 다수의 입출력패드가 형성된 제1반도체칩과; 대략 평면인 제1면과 제2면을 가지며, 상기 제2면에는 다수의 입출력패드가 형성되고, 측면에는 상기 제1면과 제2면 사이에 그것과 대략 수평을 이루는 또다른 제3면이 형성되어 있으며, 상기 제1면이 상기 제1반도체칩의 제2면에 접착층으로 접착된 제2반도체칩과; 제1반도체칩의 제1면에 접착되고, 상기 제1반도체칩 및 제2반도체칩과 전기적 접속수단으로 접속되며, 마더보드에 실장되는 섭스트레이트와; 상기 제1반도체칩, 제2반도체칩, 전기적 접속수단 및 섭스트레이트의 일면을 봉지하는 봉지재를 포함하여 이루어진 것을 특징으로 한다.In order to achieve the above object, the semiconductor package according to the present invention has a first plane and a second surface which are substantially planar, and the second surface comprises: a first semiconductor chip having a plurality of input / output pads; It has a first surface and a second surface that is substantially planar, a plurality of input and output pads are formed on the second surface, and another third surface substantially parallel to it between the first surface and the second surface A second semiconductor chip having a first surface bonded to the second surface of the first semiconductor chip by an adhesive layer; A substrate bonded to the first surface of the first semiconductor chip and connected to the first semiconductor chip and the second semiconductor chip through electrical connection means and mounted on a motherboard; It characterized in that it comprises a first semiconductor chip, a second semiconductor chip, an electrical connection means and an encapsulant for sealing one surface of the substrate.

상기 제1반도체칩은 상기 제1면과 제3면이 이루는 높이가 상기 제1면과 제2면이 이루는 높이 h의 대략 1/2 h가 되도록 함이 바람직하다.The first semiconductor chip is preferably such that the height formed by the first and third surfaces is approximately 1/2 h of the height h formed by the first and second surfaces.

상기 제2반도체칩의 입출력패드는 상기 제3면과 대응되는 영역의 제2면에 형성됨이 바람직하다.Preferably, the input / output pad of the second semiconductor chip is formed on a second surface of an area corresponding to the third surface.

상기 제1반도체칩의 입출력패드는 상기 제2반도체칩의 제3면과 대응되는 영역의 제2면에 형성됨이 바람직하다.The input / output pad of the first semiconductor chip may be formed on a second surface of an area corresponding to the third surface of the second semiconductor chip.

상기 섭스트레이트는 대략 평면인 제1면과 제2면을 갖는 수지층을 중심으로, 상기 제1면에는 볼랜드를 갖고 상기 제2면에는 본드핑거를 갖는 회로패턴을 포함하여 이루어진 인쇄회로기판, 써킷필름 또는 서킷테이프중 어느 하나인 것이 바람직하다. 이때, 상기 볼랜드에는 도전성볼이 더 융착됨이 바람직하다.The substrate includes a circuit pattern including a circuit pattern having a first surface and a second surface that are substantially planar, and having a borland on the first surface and a bond finger on the second surface. It is preferable that it is either a film or a circuit tape. At this time, it is preferable that the conductive ball is further fused to the ball land.

상기 섭스트레이트는 대략 평면인 제1면과 제2면을 갖고, 상기 제1면에는 봉지재 외부로 노출된 랜드가 형성되고, 상기 제2면에는 반도체칩과 전기적 접속수단으로 접속되는 본드핑거를 갖는 다수의 리드일 수도 있다.The substrate has a first plane and a second plane that are substantially planar, and lands exposed to the outside of the encapsulant are formed on the first surface, and bond fingers connected to the semiconductor chip and the electrical connection means are formed on the second surface. It may be a plurality of leads having.

또한 상기한 목적을 달성하기 위해 본 발명에 의한 반도체패키지의 제조 방법은 인쇄회로기판, 써킷필름, 써킷테이프 또는 리드 중 어느 하나를 선택하여 섭스트레이트를 제공하는 단계와; 상기 섭스트레이트의 중앙에, 대략 평면인 제1면과 제2면을 가지고, 상기 제2면에는 다수의 입출력패드가 형성된 제1반도체칩을 접착층으로 접착시키는 단계와; 상기 제1반도체칩의 입출력패드와 섭스트레이트를 전기적 접속수단으로 본딩시키는 단계와; 상기 제1반도체칩의 제2면에, 대략 평면인 제1면과 제2면을 가지며, 상기 제2면에는 다수의 입출력패드가 형성되고, 측면에는 상기 제1면과 제2면 사이에 그것과 대략 수평을 이루는 또다른 제3면이 형성된 제2반도체칩을 접착층으로 접착시키는 단계와; 상기 제2반도체칩의 입출력패드와 섭스트레이트를 전기적 접속수단으로 본딩시키는 단계와; 상기 제1반도체칩, 제2반도체칩, 전기적 접속수단 및 섭스트레이트를 봉지재로 봉지하는 단계를 포함하여 이루어진 것을 특징으로 한다.In addition, to achieve the above object, a method of manufacturing a semiconductor package according to the present invention comprises the steps of providing a substrate by selecting any one of a printed circuit board, a circuit film, a circuit tape or a lead; Bonding a first semiconductor chip having a first plane and a second plane that are substantially planar to a center of the substrate, and having a plurality of input / output pads formed thereon, with an adhesive layer; Bonding the input and output pads and the substrate of the first semiconductor chip with electrical connection means; The second surface of the first semiconductor chip has a first plane and a second surface that are substantially planar, and the second surface is formed with a plurality of input / output pads, and a side thereof between the first surface and the second surface. Bonding a second semiconductor chip having another third surface that is substantially horizontal with the adhesive layer; Bonding the input and output pads and the substrate of the second semiconductor chip with electrical connection means; And sealing the first semiconductor chip, the second semiconductor chip, the electrical connection means, and the substrate with an encapsulant.

상기 제2반도체칩은 다수의 반도체칩이 스크라이브 라인을 따라 대략 바둑판 모양으로 형성된 웨이퍼를 제공하는 단계와; 상기 반도체칩이 형성된 웨이퍼의 후면을 두께 t를 갖는 블레이드로 부분 1차 소잉하는 단계와; 대략 두께 1/2 t를 갖는 블레이트로 완전 2차 소잉하여 낱개의 반도체칩으로 분리하는 단계에 의해 제공될 수 있다.The second semiconductor chip comprises: providing a wafer in which a plurality of semiconductor chips are formed in a substantially checkered shape along a scribe line; Partially primary sawing the back surface of the wafer on which the semiconductor chip is formed with a blade having a thickness t; It can be provided by the step of completely secondary sawing into a blister having a thickness of approximately 1/2 t and separating it into individual semiconductor chips.

상기 제2반도체칩은 다수의 반도체칩이 스크라이브 라인을 따라 대략 바둑판 모양으로 형성된 웨이퍼를 제공하는 단계와; 상기 반도체칩이 형성된 웨이퍼의 후면을 블레이드로 소잉하되, 상기 블레이드는 단부가 대략 두께 1/2 t이고, 상기 단부의 상부는 두께가 t인 블레이드로 소잉하여, 낱개의 반도체칩으로 분리하는 단계에 의해 제공될 수 있다.The second semiconductor chip comprises: providing a wafer in which a plurality of semiconductor chips are formed in a substantially checkered shape along a scribe line; Sawing the back surface of the wafer on which the semiconductor chip is formed with a blade, wherein the blade is sawn with a blade having a thickness of about 1/2 t, and the top of the end is separated by a single semiconductor chip. Can be provided by

상기 섭스트레이트는 대략 평면인 제1면과 제2면을 갖는 수지층을 중심으로, 상기 제1면에는 볼랜드를 갖고 상기 제2면에는 본드핑거를 갖는 회로패턴을 포함하여 이루어진 인쇄회로기판, 써킷필름 또는 서킷테이프중 어느 하나가 이용될 수 있다. 이때, 상기 섭스트레이의 볼랜드에는 도전성볼을 융착하는 단계가 더 포함될 수 있다.The substrate includes a circuit pattern including a circuit pattern having a first surface and a second surface that are substantially planar, and having a borland on the first surface and a bond finger on the second surface. Either film or circuit tape can be used. At this time, the ball land of the substray may further comprise the step of fusion bonding the conductive ball.

상기 섭스트레이트는 대략 평면인 제1면과 제2면을 갖고, 상기 제1면에는 봉지재 외부로 노출되는 랜드가 형성되며, 상기 제2면에는 반도체칩과 전기적 접속수단으로 접속되는 본드핑거를 갖는 다수의 리드가 이용될 수 있다.The substrate has a first plane and a second plane which are substantially planar, and lands are exposed to the outside of the encapsulant on the first surface, and bond fingers connected to the semiconductor chip and the electrical connection means are formed on the second surface. Multiple leads having may be used.

상기와 같이 하여 본 발명에 의한 반도체패키지 및 그 제조 방법에 의하면, 제2반도체칩의 측면 근처에 두께가 더욱 얇도록 제3면을 형성하여 소정 공간을 확보함으로써, 그 하부에 위치되는 제1반도체칩의 입출력패드와 섭스트레이트 사이를 연결한 전기적 접속수단과 제2반도체칩의 제2면이 상호 간섭하거나 쇼트 또는 그 접속수단의 파손을 방지하게 된다.According to the semiconductor package and the manufacturing method of the present invention as described above, by forming a third surface near the side surface of the second semiconductor chip so that the thickness is thinner to secure a predetermined space, the first semiconductor is located below Electrical connection means connecting the input and output pads and the substrate of the chip and the second surface of the second semiconductor chip to prevent mutual interference or breakage of the short or the connection means.

더불어, 동일한 크기의 반도체칩을 다수 적층할 수 있음으로써, 고용량 고기능의 반도체패키지를 제공하게 되고, 또한 섭스트레이트의 패턴 설계 자유도도 높아진다.In addition, by stacking a large number of semiconductor chips of the same size, it is possible to provide a high-capacity, high-performance semiconductor package, and also to increase the degree of freedom of pattern design of the substrate.

이하 본 발명이 속한 기술분야에서 통상의 지식을 가진 자가 본 발명을 용이하게 실시할 수 있을 정도로 본 발명의 바람직한 실시예를 첨부된 도면을 참조하여 상세하게 설명하면 다음과 같다.Hereinafter, preferred embodiments of the present invention will be described in detail with reference to the accompanying drawings such that those skilled in the art can easily implement the present invention.

도2a 내지 도2c는 본 발명에 의한 반도체패키지로서, 봉지재가 제거된 상태를 도시한 상태도이다.2A to 2C are state diagrams showing a state in which a sealing material is removed as a semiconductor package according to the present invention.

먼저 도2a를 참조하면, 대략 평면인 제1면(1a)과 제2면(1b)을 가지고, 상기 제2면(1b)의 주연 근처에는 다수의 입출력패드(1c)가 형성된 제1반도체칩(1)이 구비되어 있다.First, referring to FIG. 2A, a first semiconductor chip having a first surface 1a and a second surface 1b that are substantially planar, and a plurality of input / output pads 1c are formed near the periphery of the second surface 1b. (1) is provided.

또한, 대략 평면인 제1면(2a)과 제2면(2b)을 가지며, 상기 제2면(2b)의 주연 근처에는 다수의 입출력패드(2c)가 형성되고, 측면에는 상기 제1면(2a)과제2면(2b) 사이에 그것과 대략 수평을 이루는 또다른 제3면(2d)이 형성되어 있으며, 상기 제1면(2a)이 상기 제1반도체칩(1)의 제2면(1b)에 접착층으로 접착된 제2반도체칩(2)이 구비되어 있다.In addition, the first surface 2a and the second surface 2b are substantially planar, and a plurality of input / output pads 2c are formed near the periphery of the second surface 2b, and the first surface 2 Another third surface 2d is formed between the second surface 2b and the second surface 2b, which is substantially horizontal to the second surface 2b, and the first surface 2a is the second surface of the first semiconductor chip 1. A second semiconductor chip 2 bonded to 1b) with an adhesive layer is provided.

여기서, 상기 제2반도체칩(2)의 제3면(2d)은 제1면(2a) 및 제2면(2b)과 수평을 이루며, 상기 제3면(2d)과 대응되는 영역에 제1반도체칩(1)의 입출력패드(1c)가 형성되어 있음으로써, 하기할 전기적 접속수단(30)이 충분히 상기 입출력패드(1c)에 접속되어 위치할 공간이 확보된다.Here, the third surface 2d of the second semiconductor chip 2 is parallel to the first surface 2a and the second surface 2b, and has a first surface in an area corresponding to the third surface 2d. Since the input / output pad 1c of the semiconductor chip 1 is formed, the space for the electrical connection means 30 to be described below is sufficiently connected to the input / output pad 1c to be positioned.

또한, 상기 제2반도체칩(2)의 입출력패드(2c) 역시 상기 제2반도체칩(2)의 제3면(2d)과 대응되는 영역의 제2면(2b)에 형성되어 있다.In addition, the input / output pad 2c of the second semiconductor chip 2 is also formed on the second surface 2b of the region corresponding to the third surface 2d of the second semiconductor chip 2.

더불어, 상기 제2반도체칩(2)의 제2면(2b)에는 상기와 같이 제3면(2d)을 갖는 또다른 반도체칩을 다수 적층할 수 있음은 당연하며, 여기서 한정하는 것은 아니다.In addition, it is natural that a plurality of other semiconductor chips having the third surface 2d may be stacked on the second surface 2b of the second semiconductor chip 2, but the present invention is not limited thereto.

계속해서, 상기 제1반도체칩(1)의 제1면(1a)에는 접착층(20)으로 섭스트레이트(S)가 접착되어 있는데, 상기 섭스트레이트로서는 통상적인 인쇄회로기판, 리드프레임, 써킷필름, 써킷테이프 등등이 이용될 수 있다.Subsequently, the substrate S is bonded to the first surface 1a of the first semiconductor chip 1 by the adhesive layer 20. As the substrate, a substrate, a lead frame, a circuit film, Circuit tape and the like can be used.

또한, 상기 제1반도체칩(1) 및 제2반도체칩(2)의 입출력패드(1c,2c)는 골드와이어나 알루미늄와이어와 같은 도전성와이어에 의해 섭스트레이트의 소정 영역에 본딩되어 있다.In addition, the input / output pads 1c and 2c of the first semiconductor chip 1 and the second semiconductor chip 2 are bonded to a predetermined region of the substrate by conductive wires such as gold wires or aluminum wires.

다음으로, 도2b를 참조한다. 상기 도2b 역시 도2a와 유사하므로 그 차이점만을 설명하기로 한다.Next, reference is made to FIG. 2B. Since FIG. 2B is also similar to FIG. 2A, only the differences will be described.

도시된 바와 같이 제1반도체칩(1)의 제2면(1b)에는 접착층이 개재되어 제2반도체칩(2)이 접착되어 있다. 상기 제2반도체칩(2)은 대략 평면인 제1면(2a)과 제2면(2b)을 가지고, 상기 제1면(2a)과 제2면(2b) 사이에는 또다른 제3면(2d)이 형성되어 있다. 상기 제3면(2d)은 도시된 바와 같이 상기 제1면(2a) 및 제2면(2b)에 대하여 일정한 각도로 경사져 형성된 것이 특징이다. 여기서도, 상기와 같이 제3면(2d)이 경사진 채 형성됨으로써, 제1반도체칩(1)의 입출력패드(1c)에 본딩되는 도전성와이어(30)의 위치를 충분히 확보하게 된다.As illustrated, the second semiconductor chip 2 is bonded to the second surface 1b of the first semiconductor chip 1 with an adhesive layer interposed therebetween. The second semiconductor chip 2 has an approximately planar first surface 2a and a second surface 2b, and another third surface between the first surface 2a and the second surface 2b ( 2d) is formed. As shown in the drawing, the third surface 2d is inclined at a predetermined angle with respect to the first surface 2a and the second surface 2b. In this case, the third surface 2d is inclined as described above, thereby sufficiently securing the position of the conductive wire 30 bonded to the input / output pad 1c of the first semiconductor chip 1.

또한, 도2c를 참조하면, 제2반도체칩(2)의 제3면(2d)이 라운드(Round) 처리 되어 있는 것이 특징이다. 즉, 제2반도체칩(2)의 제1면(2a)과 제2면(2b) 사이에는 또다른 제3면(2d)이 형성되어 있는데, 이 제3면(2d)은 상기 제1면(2a)과 일정 직경을 갖도록 라운드 처리되어 있는 것이 특징이다. 이 경우에 있어서도, 제1반도체칩(1)의 입출력패드(1a)에 본딩되는 도전성와이어(30)의 위치를 충분히 확보하게 된다.2C, the third surface 2d of the second semiconductor chip 2 is rounded. That is, another third surface 2d is formed between the first surface 2a and the second surface 2b of the second semiconductor chip 2, and the third surface 2d is the first surface. It is characterized by being rounded so as to have a constant diameter with (2a). Also in this case, the position of the conductive wire 30 bonded to the input / output pad 1a of the first semiconductor chip 1 is sufficiently secured.

도3a 및 도3b는 본 발명에 의한 반도체패키지(101,102)의 일례를 도시한 단면도이다. 여기서, 상기 반도체패키지(101,102)는 상기 도2a에 도시된 반도체패키지 구조를 일례로 하지만, 상기 도2b 및 도2c의 구조를 모두 채택할 수 있음은 당연하다.3A and 3B are cross-sectional views showing examples of semiconductor packages 101 and 102 according to the present invention. Here, although the semiconductor packages 101 and 102 take the semiconductor package structure shown in FIG. 2A as an example, it is obvious that all of the structures of FIGS. 2B and 2C may be adopted.

먼저 도3a의 반도체패키지(101)를 참조하면, 대략 평면인 제1면(1a)과 제2면(1b)을 가지고, 상기 제2면(1b)의 주연 근처에는 다수의 입출력패드(1c)가 형성된 제1반도체칩(1)이 구비되어 있다.First, referring to the semiconductor package 101 of FIG. 3A, the semiconductor package 101 includes a first plane 1a and a second plane 1b that are substantially planar, and a plurality of input / output pads 1c near the periphery of the second surface 1b. Is provided with a first semiconductor chip (1).

또한, 대략 평면인 제1면(2a)과 제2면(2b)을 가지며, 상기 제2면(2b)의 주연 근처에는 다수의 입출력패드(2c)가 형성되고, 측면에는 상기 제1면(2a)과 제2면(2b) 사이에 그것과 대략 수평을 이루는 또다른 제3면(2d)이 형성되어 있으며, 상기 제1면(2a)이 상기 제1반도체칩(1)의 제2면(1b)에 접착층(20)으로 접착된 제2반도체칩(2)이 구비되어 있다.In addition, the first surface 2a and the second surface 2b are substantially planar, and a plurality of input / output pads 2c are formed near the periphery of the second surface 2b, and the first surface 2 Another third surface 2d is formed between 2a) and the second surface 2b, which is substantially parallel to it, and the first surface 2a is the second surface of the first semiconductor chip 1. The second semiconductor chip 2 adhered to (1b) with the adhesive layer 20 is provided.

여기서, 상기 제1반도체칩(1)의 입출력패드(1c)는 상기 제2반도체칩(2)의 제3면(2d)과 대응되는 영역의 제2면(1b)에 형성되어 있음으로써, 하기할 전기적 접속수단(30)이 충분히 상기 입출력패드(1c)에 접속되어 위치할 공간이 확보된다.Here, the input / output pad 1c of the first semiconductor chip 1 is formed on the second surface 1b of the region corresponding to the third surface 2d of the second semiconductor chip 2. An electrical connection means 30 is sufficiently connected to the input / output pad 1c to secure a space for positioning.

또한, 상기 제2반도체칩(2)의 입출력패드(2c) 역시 상기 제2반도체칩(2)의 제3면(2d)과 대응되는 영역의 제2면(2b)에 형성되어 있다.In addition, the input / output pad 2c of the second semiconductor chip 2 is also formed on the second surface 2b of the region corresponding to the third surface 2d of the second semiconductor chip 2.

더불어, 상기 제2반도체칩(2)의 제2면(2b)에는 상기와 같이 제3면(2d)을 갖는 또다른 반도체칩을 다수 적층할 수 있음은 당연하며, 여기서 한정하는 것은 아니다.In addition, it is natural that a plurality of other semiconductor chips having the third surface 2d may be stacked on the second surface 2b of the second semiconductor chip 2, but the present invention is not limited thereto.

계속해서, 상기 제1반도체칩(1)의 제1면(1a)에는 접착층(20)으로 섭스트레이트가 접착되어 있는데, 도면에서는 상기 섭스트레이트의 한 예로서 인쇄회로기판(10)이 도시되어 있다.Subsequently, the substrate is bonded to the first surface 1a of the first semiconductor chip 1 by the adhesive layer 20. In the drawing, the printed circuit board 10 is shown as an example of the substrate. .

상기 섭스트레이트는 대략 평면인 제1면(11a)과 제2면(11b)을 갖는 수지층(11)을 중심으로, 상기 제1면(11a)에는 볼랜드(12b)를 갖고 상기 제2면(11b)에는 본드핑거(12a)를 갖는 회로패턴(12)이 형성되어 있다. 상기 회로패턴(12)은 주지된 바와 같이 구리박막(Cu Foil)이며, 이러한 구조는 인쇄회로기판(10)뿐만 아니라, 써킷필름 또는 써킷테이프도 가능하다. 여기서, 상기 섭스트레이트로서 인쇄회로기판, 써킷필름, 또는 써킷테이프 모두 가능하며, 어느 하나로 한정하는 것은 아니다.The substrate has a resin layer 11 having a first plane 11a and a second plane 11b that are substantially planar, and has a ball land 12b on the first plane 11a and the second plane ( 11b), a circuit pattern 12 having a bond finger 12a is formed. The circuit pattern 12 is a copper foil (Cu Foil), as is well known, this structure may be a circuit film or a circuit tape as well as the printed circuit board 10. Here, the substrate may be a printed circuit board, a circuit film, or a circuit tape, but is not limited thereto.

또한, 상기 인쇄회로기판(10)은 상기 수지층(11)의 제1면(11a)과 제2면(11b)에 형성된 회로패턴(12)이 도전성 비아홀(13)에 의해 상호 연결되어 있으며, 상기 볼랜드(12b) 및 본드핑거(12a)를 제외한 회로패턴(12) 및 수지층(11) 표면은 커버코트(14)로 코팅되어 있다. 상기 커버코트(14)는 통상적인 절연성 고분자 수지이다.In addition, the printed circuit board 10 has circuit patterns 12 formed on the first and second surfaces 11a and 11b of the resin layer 11 connected to each other by conductive via holes 13. The surface of the circuit pattern 12 and the resin layer 11 except for the borland 12b and the bond finger 12a is coated with a cover coat 14. The cover coat 14 is a conventional insulating polymer resin.

또한, 상기 제1반도체칩(1) 및 제2반도체칩(2)의 입출력패드(1c,2c)는 상기 인쇄회로기판(10)의 본드핑거(12a)와 전기적 접속수단(30)에 의해 상호 본딩되어 있다. 상기 접속수단(30)은 통상적인 골드와이어(Au Wire) 또는 알루미늄와이어(Al Wire)와 같은 도전성와이어이다.In addition, the input and output pads 1c and 2c of the first semiconductor chip 1 and the second semiconductor chip 2 are mutually connected by the bond fingers 12a of the printed circuit board 10 and the electrical connection means 30. Bonded The connection means 30 is a conductive wire such as a conventional gold wire (Au Wire) or aluminum wire (Al Wire).

또한, 상기 제1반도체칩(1), 제2반도체칩(2), 전기적 접속수단(30)과 상기 인쇄회로기판(10)의 일면은 에폭시 몰딩 컴파운드(Epoxy Molding Compound) 또는 글럽탑(Glop Top)과 같은 봉지재(50)로 봉지되어 상기의 것들이 외부환경으로부터 보호되도록 되어 있다.In addition, one surface of the first semiconductor chip 1, the second semiconductor chip 2, the electrical connection means 30 and the printed circuit board 10 may be formed of an epoxy molding compound or a glop top. It is encapsulated with an encapsulant 50 such as) so that the above are protected from the external environment.

마지막으로, 상기 인쇄회로기판(10)의 볼랜드(12b)에는 솔더볼과 같은 도전성볼(60)이 융착되어 차후 마더보드(Mother Board)에 실장 가능하게 되어 있다.Finally, conductive balls 60, such as solder balls, are fused to the ball lands 12b of the printed circuit board 10 to be mounted on a motherboard later.

계속해서, 도3b의 반도체패키지(102)에서와 같이 섭스트레이트로서 다수의 리드(70)가 이용될 수도 있다. 즉, 대략 평면인 제1면(70a)과 제2면(70b)을 갖고,상기 제1면(70a)에는 봉지재(50) 외부로 노출된 랜드(71a)가 형성되고, 상기 제2면(70b)에는 제1반도체칩(1) 및 제2반도체칩(2)과 전기적 접속수단(30)으로 접속되는 본드핑거(71b)를 갖는 구리(Cu) 또는 철(Fe) 계열의 리드(70)일 수도 있다.Subsequently, a plurality of leads 70 may be used as the substrate as in the semiconductor package 102 of FIG. 3B. That is, the first surface 70a and the second surface 70b are substantially planar, and the land 71a exposed to the outside of the encapsulant 50 is formed on the first surface 70a and the second surface. A copper (Cu) or iron (Fe) series of lead 70 having a bond finger 71b connected to the first semiconductor chip 1 and the second semiconductor chip 2 by an electrical connection means 30 is formed in the 70b. )

여기서, 상기 랜드(71a)를 제외한 리드(70)의 제1면(70a)은 화학용액에 의한 부분 에칭 또는 할프 에칭(Half Etching)에 의해 그 두께가 더 얇게 되어 있음으로써 상기 랜드(71a)만이 봉지재(50) 외측으로 노출되고, 나머지 부분은 봉지재(50) 내측에 위치하게 된다. 따라서 상기 리드(70)는 봉지재(50)로부터 쉽게 이탈되거나 빠지지 않게 된다.Here, the first surface 70a of the lead 70 except for the land 71a is thinner by partial etching or half etching with a chemical solution, so that only the land 71a is formed. The encapsulant 50 is exposed to the outside, and the remaining part is positioned inside the encapsulant 50. Therefore, the lead 70 is not easily separated or removed from the encapsulant 50.

도4a 내지 도4f는 본 발명에 의한 반도체패키지(101)의 제조 방법을 도시한 설명도이며, 이를 참조하여 본 발명에 의한 반도체패키지의 제조 방법을 상세히 설명하면 다음과 같다.4A to 4F are explanatory views illustrating a method of manufacturing the semiconductor package 101 according to the present invention. Referring to this, the method of manufacturing the semiconductor package according to the present invention will be described in detail as follows.

1. 섭스트레이트 제공 단계로서, 인쇄회로기판(10), 써킷필름, 써킷테이프 또는 리드(70) 중 어느 하나를 선택하여 섭스트레이트로서 제공한다. 이하에서는 상기 인쇄회로기판(10)을 예로 하여 설명하지만, 이것만으로 본 발명을 한정하는 것은 아니다.1. Substrate providing step, any one of the printed circuit board 10, the circuit film, the circuit tape or the lead 70 is selected and provided as a substrate. Hereinafter, the printed circuit board 10 will be described as an example, but the present invention is not limited thereto.

상기 인쇄회로기판(10)은 전술한 바와 같이 대략 평면인 제1면(11a)과 제2면(11b)을 갖는 수지층(11)을 중심으로, 상기 제1면(11a)에는 볼랜드(12b)를 제2면(11b)에는 본드핑거(12a)를 갖는 회로패턴(12)이 형성되어 있고, 상기 볼랜드(12b) 및 본드핑거(12a)를 제외한 나머지 회로패턴(12) 및 수지층(11)의 표면은 커버코트(14)로 코팅되어 있다.As described above, the printed circuit board 10 has a resin layer 11 having a first plane 11a and a second plane 11b that are substantially planar, and a ball land 12b on the first surface 11a. The circuit pattern 12 having the bond finger 12a is formed on the second surface 11b, and the remaining circuit patterns 12 and the resin layer 11 except for the borland 12b and the bond finger 12a are formed. The surface of) is coated with a cover coat 14.

2. 제1반도체칩 접착 단계로서, 상기 인쇄회로기판(10)에서 수지층(11)의 제2면(11b) 중앙부에 접착층(20)을 개재하여 대략 평면인 제1면(1a)과 제2면(1b)을 가지고, 상기 제2면(1b)에는 다수의 입출력패드(1c)가 형성된 제1반도체칩(1)을 접착한다.(도4a 참조)2. A step of bonding the first semiconductor chip, wherein the first surface 1a and the first surface 1a which are substantially planar are interposed between the printed circuit board 10 and the center of the second surface 11b of the resin layer 11 via the adhesive layer 20. A first semiconductor chip 1 having two surfaces 1b and a plurality of input / output pads 1c formed thereon is bonded to the second surface 1b (see FIG. 4A).

3. 전기적 접속 단계로서, 상기 제1반도체칩(1)의 입출력패드(1c)와 인쇄회로기판(10)의 본드핑거(12a)를 전기적 접속수단(30)으로 접속한다. 여기서 상기 전기적 접속수단(30)은 골드와이어 또는 알루미늄와이어와 같은 도전성와이어이다.(도4b 참조)3. In the electrical connection step, the input / output pad 1c of the first semiconductor chip 1 and the bond finger 12a of the printed circuit board 10 are connected to the electrical connection means 30. The electrical connection means 30 is a conductive wire such as a gold wire or an aluminum wire (see FIG. 4B).

4. 제2반도체칩 접착 단계로서, 상기 제1반도체칩(1)의 제2면(1b)에, 대략 평면인 제1면(2a)과 제2면(2b)을 가지며, 상기 제2면(2b)에는 다수의 입출력패드(2c)가 형성되고, 측면에는 상기 제1면(2a)과 제2면(2b) 사이에 그것과 대략 수평을 이루는 또다른 제3면(2d)이 형성된 제2반도체칩(2)을 접착층(20)으로 접착한다.(도4c 참조)4. A second semiconductor chip bonding step, comprising a first surface 2a and a second surface 2b which are substantially planar on the second surface 1b of the first semiconductor chip 1, wherein the second surface A plurality of input / output pads 2c are formed at (2b), and another third surface (2d) is formed on the side surface between the first surface (2a) and the second surface (2b) substantially parallel to it 2 The semiconductor chip 2 is adhered to the adhesive layer 20 (see Fig. 4C).

여기서, 상기 제3면(2d)을 갖는 제2반도체칩(2)의 제공 단계를 좀더 상세히 설명하면 다음과 같다.Here, the step of providing the second semiconductor chip 2 having the third surface 2d will be described in more detail.

즉, 도5a 및 도5b는 웨이퍼(w)에서 반도체칩(c)을 소잉하는 상태를 도시한 사시도이고, 도6a 및 도6b는 도5b에서 사용되는 블레이드(b)의 예를 도시한 단면도이다.5A and 5B are perspective views showing a state of sawing the semiconductor chip c from the wafer w, and Figs. 6A and 6B are cross-sectional views showing an example of the blade b used in Fig. 5B. .

도시된 바와 같이 웨이퍼(w)의 전면(f)에는 다수의 반도체칩(c)이 스크라이브 라인(s, Scribe Line)을 따라 대략 바둑판 모양으로 형성되어 있다. 통상 이러한 웨이퍼(w)는 낱개의 반도체칩(c)을 분리해내기 위해 상기 웨이퍼(w)의 스크라이브 라인(s)을 따라 다이아몬드 블레이드(b)를 이용하여 소잉 작업을 수행한다. 그러나, 본 발명은 도6b에 도시된 바와 같이 상기 웨이퍼(w)의 후면(r)에서부터 소잉 작업을 수행한다(종래에는 전면(f)에서 소잉 작업을 수행함) 물론, 상기 웨이퍼(w)의 후면(r)에서 소잉 작업을 수행할 때도 전면(f)의 스크라이브 라인(s)과 대응되는 영역을 따라 소잉한다.As illustrated, a plurality of semiconductor chips c are formed in a substantially checkerboard shape along a scribe line s on the front surface f of the wafer w. Typically, such a wafer w performs a sawing operation using a diamond blade b along the scribe line s of the wafer w to separate the individual semiconductor chips c. However, the present invention performs the sawing operation from the rear surface r of the wafer w as shown in FIG. 6B (in the past, the sawing operation is performed from the front surface f). When the sawing operation is performed in (r), the sawing is performed along the area corresponding to the scribe line s of the front surface f.

한편, 상기 소잉시 사용되는 블레이드(b)는 단부가 대략 두께 1/2 t를 갖고, 상기 단부의 상부 영역은 두께가 t인 것으로 소잉하여 낱개의 반도체칩(c)으로 분리한다.On the other hand, the blade (b) used during sawing has an edge having a thickness of approximately 1/2 t, and the upper region of the end is sawed to have a thickness of t and separated into individual semiconductor chips (c).

물론, 상기 두께가 t인 블레이드(b)의 중앙 영역은 웨이퍼(w)의 스크라이브라인(s)을 완전히 관통하지 않고, 중간 근처에서 멈춘다. 하지만 두께 1/2 t인 블레이드(b) 단부 영역에 의해 상기 스크라이브라인(s)은 완전히 관통된다. 따라서, 예를 들면, 제1면(2a) 및 제2면(2b) 외에 그 사이의 영역에 제3면(2d)이 형성된 제2반도체칩(2)을 제공할 수 있게 된다.Of course, the central region of the blade b of thickness t stops near the middle without completely penetrating the scribe brine s of the wafer w. However, the scribe brine s is completely penetrated by the blade b end region having a thickness of 1/2 t. Therefore, for example, it is possible to provide the second semiconductor chip 2 having the third surface 2d formed in the region therebetween in addition to the first surface 2a and the second surface 2b.

물론, 도6b에 도시된 바와 같이 2개의 블레이드(b1,b2)를 순차적으로 이용할 수도 있다. 즉, 먼저 두께 t를 갖는 블레이드(b1)를 이용하여 웨이퍼(w)의 후면(r)에서부터 전체 두께의 대략 절반을 소잉하고, 또한 대략 두께 1/2 t를 갖는 두번째 블레이드(b2)를 이용하여 웨이퍼(w)를 완전히 관통하여 소잉함으로써, 낱개의 반도체칩으로 분리해낼 수도 있다. 이와 같은 방법 역시, 예를 들면, 제1면(2a) 및 제2면(2b) 외에 그 사이의 영역에 제3면(2d)이 형성된 제2반도체칩(2)을 제공할 수 있다.Of course, as shown in FIG. 6B, the two blades b1 and b2 may be used sequentially. That is, first sawing about half of the total thickness from the rear surface r of the wafer w using the blade b1 having the thickness t, and further using the second blade b2 having the thickness 1/2 t, It can also be separated into individual semiconductor chips by sawing through the wafer w completely. Such a method can also provide, for example, a second semiconductor chip 2 having a third surface 2d formed in a region between the first surface 2a and the second surface 2b.

여기서, 상기와 같은 구조의 블레이드(b, b1,b2)를 이용했을 경우에는 도2a 및 도3a,3b에 개시된 제2반도체칩(2)의 구조를 얻을 수 있다. 그러나, 상기한 블레이드 구조외에 하단부가 중심을 경계로 경사져 있거나, 또는 라운드 처리된 블레이드를 이용했을 경우에는 도2b 및 도2c에 개시된 제2반도체칩(2)의 구조도 얻을 수 있음은 당연하다.When the blades b, b1, and b2 having the above structure are used, the structure of the second semiconductor chip 2 shown in Figs. 2A and 3A and 3B can be obtained. However, in addition to the blade structure described above, when the lower end portion is inclined with respect to the center or a rounded blade is used, the structure of the second semiconductor chip 2 shown in FIGS. 2B and 2C can also be obtained.

5. 전기적 접속 단계로서, 상기 제2반도체칩(2)의 입출력패드(2c)와 인쇄회로기판(10)의 본드핑거(12a)를 전기적 접속수단(30)으로 본딩한다.(도4d 참조)5. In the electrical connection step, the input / output pad 2c of the second semiconductor chip 2 and the bond finger 12a of the printed circuit board 10 are bonded by the electrical connection means 30 (see FIG. 4D).

6. 봉지 단계로서, 상기 제1반도체칩(1), 제2반도체칩(2), 전기적 접속수단(30) 및 인쇄회로기판(10)을 봉지재(50)로 봉지한다.(도4e 참조)6. In the encapsulation step, the first semiconductor chip 1, the second semiconductor chip 2, the electrical connection means 30 and the printed circuit board 10 are encapsulated with an encapsulant 50 (see Fig. 4e). )

7. 도전성볼 융착 단계로서, 상기 인쇄회로기판(10)의 볼랜드(12b)에 솔더볼과 같은 도전성볼(60)을 융착하여 마더보드에 실장 가능한 형태가 되도록 한다.(도4f 참조)7. As a conductive ball fusion step, the conductive ball 60 such as solder ball is fused to the ball land 12b of the printed circuit board 10 so as to be mounted on the motherboard (see Fig. 4f).

만약, 상기 섭스트레이트로서 인쇄회로기판(10), 써킷필름 또는 써킷테이프를 이용하지 않고 리드(70)를 이용했을 경우에는 물론, 상기 도전성볼(60) 융착 단계가 생략될 수도 있다.If the lead 70 is used without using the printed circuit board 10, the circuit film, or the circuit tape as the substrate, the fusion step of the conductive balls 60 may be omitted.

이상에서와 같이 본 발명은 비록 상기의 실시예에 한하여 설명하였지만 여기에만 한정되지 않으며, 본 발명의 범주 및 사상을 벗어나지 않는 범위내에서 여러가지로 변형된 실시예도 가능할 것이다.As described above, although the present invention has been described with reference to the above embodiments, the present invention is not limited thereto, and various modified embodiments may be possible without departing from the scope and spirit of the present invention.

따라서, 본 발명에 의한 반도체패키지 및 그 제조 방법에 의하면, 제2반도체칩의 측면 근처에 두께가 더욱 얇도록 제3면을 형성하여 소정 공간을 확보함으로써, 그 하부에 위치되는 제1반도체칩의 입출력패드와 섭스트레이트 사이를 연결한 전기적 접속수단과 제2반도체칩의 제2면이 상호 간섭하거나 쇼트 또는 그 접속수단의 파손을 방지하게 되는 효과가 있다.Therefore, according to the semiconductor package and the manufacturing method thereof according to the present invention, by forming a third surface near the side surface of the second semiconductor chip so as to have a thinner thickness to secure a predetermined space, The electrical connection means connected between the input / output pad and the substrate and the second surface of the second semiconductor chip interfere with each other or prevent a short or breakage of the connection means.

더불어, 동일한 크기의 반도체칩을 다수 적층할 수 있음으로써, 고용량 고기능의 반도체패키지를 제공하게 되고, 또한 섭스트레이트의 패턴 설계 자유도도 높아지는 효과가 있다.In addition, by stacking a plurality of semiconductor chips of the same size, it is possible to provide a high-capacity, high-functional semiconductor package, and also has the effect of increasing the degree of freedom in designing the substrate.

Claims (6)

대략 평면인 제1면과 제2면을 가지고, 상기 제2면에는 다수의 입출력패드가 형성된 제1반도체칩과;A first semiconductor chip having a first plane and a second plane which are substantially planar, and having a plurality of input / output pads formed thereon; 대략 평면인 제1면과 제2면을 가지며, 상기 제2면에는 다수의 입출력패드가 형성되고, 측면에는 상기 제1면과 제2면 사이에 그것과 대략 수평을 이루는 또다른 제3면이 형성되어 있으며, 상기 제1면이 상기 제1반도체칩의 제2면에 접착층으로 접착된 제2반도체칩과;It has a first surface and a second surface that is substantially planar, a plurality of input and output pads are formed on the second surface, and another third surface substantially parallel to it between the first surface and the second surface A second semiconductor chip having a first surface bonded to the second surface of the first semiconductor chip by an adhesive layer; 제1반도체칩의 제1면에 접착되고, 상기 제1반도체칩 및 제2반도체칩과 전기적 접속수단으로 접속되며, 마더보드에 실장되는 섭스트레이트와;A substrate bonded to the first surface of the first semiconductor chip and connected to the first semiconductor chip and the second semiconductor chip through electrical connection means and mounted on a motherboard; 상기 제1반도체칩, 제2반도체칩, 전기적 접속수단 및 섭스트레이트의 일면을 봉지하는 봉지재를 포함하여 이루어진 반도체패키지.A semiconductor package comprising an encapsulant for encapsulating one surface of the first semiconductor chip, the second semiconductor chip, the electrical connection means and the substrate. 제1항에 있어서, 상기 제2반도체칩은 상기 제1반도체칩의 입출력패드가 형성된 영역과 대응되는 위치에 제3면이 형성된 것을 특징으로 하는 반도체패키지.The semiconductor package of claim 1, wherein the second semiconductor chip has a third surface formed at a position corresponding to a region where an input / output pad of the first semiconductor chip is formed. 제1항에 있어서, 상기 제2반도체칩은 제3면이 상기 제1반도체칩의 제1면 및 제2면과 수평하게 형성되어 있거나, 경사지게 형성되어 있거나, 또는 라운드 처리된 것중 어느 한 구조인 것을 특징으로 하는 반도체패키지.The semiconductor device of claim 1, wherein the second semiconductor chip has a structure in which a third surface is formed horizontally with the first surface and the second surface of the first semiconductor chip, is inclined, or is rounded. A semiconductor package, characterized in that. 인쇄회로기판, 써킷필름, 써킷테이프 또는 리드 중 어느 하나를 선택하여 섭스트레이트를 제공하는 단계와;Selecting a printed circuit board, a circuit film, a circuit tape, or a lead to provide a substrate; 상기 섭스트레이트의 중앙에, 대략 평면인 제1면과 제2면을 가지고, 상기 제2면에는 다수의 입출력패드가 형성된 제1반도체칩을 접착층으로 접착시키는 단계와;Bonding a first semiconductor chip having a first plane and a second plane that are substantially planar to a center of the substrate, and having a plurality of input / output pads formed thereon, with an adhesive layer; 상기 제1반도체칩의 입출력패드와 섭스트레이트를 전기적 접속수단으로 본딩시키는 단계와;Bonding the input and output pads and the substrate of the first semiconductor chip with electrical connection means; 상기 제1반도체칩의 제2면에, 대략 평면인 제1면과 제2면을 가지며, 상기 제2면에는 다수의 입출력패드가 형성되고, 측면에는 상기 제1면과 제2면 사이에 그것과 대략 수평을 이루는 또다른 제3면이 형성된 제2반도체칩을 접착층으로 접착시키는 단계와;The second surface of the first semiconductor chip has a first plane and a second surface that are substantially planar, and the second surface is formed with a plurality of input / output pads, and a side thereof between the first surface and the second surface. Bonding a second semiconductor chip having another third surface that is substantially horizontal with the adhesive layer; 상기 제2반도체칩의 입출력패드와 섭스트레이트를 전기적 접속수단으로 본딩시키는 단계와;Bonding the input and output pads and the substrate of the second semiconductor chip with electrical connection means; 상기 제1반도체칩, 제2반도체칩, 전기적 접속수단 및 섭스트레이트를 봉지재로 봉지하는 단계를 포함하여 이루어진 반도체패키지의 제조 방법.And encapsulating the first semiconductor chip, the second semiconductor chip, the electrical connection means, and the substrate with an encapsulant. 제4항에 있어서, 상기 제2반도체칩은 다수의 반도체칩이 스크라이브 라인을 따라 대략 바둑판 모양으로 형성된 웨이퍼를 제공하는 단계와;The method of claim 4, wherein the second semiconductor chip comprises: providing a wafer in which a plurality of semiconductor chips are formed in a substantially checkered shape along a scribe line; 상기 반도체칩이 형성된 웨이퍼의 후면을 두께 t를 갖는 블레이드로 부분 1차 소잉하는 단계와;Partially primary sawing the back surface of the wafer on which the semiconductor chip is formed with a blade having a thickness t; 대략 두께 1/2 t를 갖는 블레이트로 완전 2차 소잉하여 낱개의 반도체칩으로 분리하는 단계에 의해 제공된 것을 특징으로 하는 반도체패키지의 제조 방법.A method of manufacturing a semiconductor package, characterized in that it is provided by a step of completely secondary sawing into a single chip having a thickness of approximately 1/2 t. 제4항에 있어서, 상기 제2반도체칩은 다수의 반도체칩이 스크라이브 라인을 따라 대략 바둑판 모양으로 형성된 웨이퍼를 제공하는 단계와;The method of claim 4, wherein the second semiconductor chip comprises: providing a wafer in which a plurality of semiconductor chips are formed in a substantially checkered shape along a scribe line; 상기 반도체칩이 형성된 웨이퍼의 후면을 블레이드로 소잉하되, 상기 블레이드는 단부가 대략 두께 1/2 t이고, 상기 단부의 상부는 두께가 t인 블레이드로 소잉하여, 낱개의 반도체칩으로 분리하는 단계에 의해 제공된 것을 특징으로 하는 반도체패키지의 제조 방법.Sawing the back surface of the wafer on which the semiconductor chip is formed with a blade, wherein the blade is sawed with a blade having a thickness of about 1/2 t and an upper portion of the end with a blade having a thickness of t, and separated into individual semiconductor chips. Method for producing a semiconductor package, characterized in that provided by.
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