KR20020017103A - Gate contact in a semiconductor device and fabricating method thereof - Google Patents
Gate contact in a semiconductor device and fabricating method thereof Download PDFInfo
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- H—ELECTRICITY
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- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
- H01L21/76802—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
- H01L21/28008—Making conductor-insulator-semiconductor electrodes
- H01L21/28017—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon
- H01L21/28026—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor
- H01L21/28035—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor the final conductor layer next to the insulator being silicon, e.g. polysilicon, with or without impurities
- H01L21/28044—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor the final conductor layer next to the insulator being silicon, e.g. polysilicon, with or without impurities the conductor comprising at least another non-silicon conductive layer
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- H—ELECTRICITY
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- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3105—After-treatment
- H01L21/311—Etching the insulating layers by chemical or physical means
- H01L21/31144—Etching the insulating layers by chemical or physical means using masks
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- H—ELECTRICITY
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- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
- H01L21/76877—Filling of holes, grooves or trenches, e.g. vias, with conductive material
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- H—ELECTRICITY
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- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02107—Forming insulating materials on a substrate
- H01L21/02109—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates
- H01L21/02112—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer
- H01L21/02123—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon
- H01L21/02126—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon the material containing Si, O, and at least one of H, N, C, F, or other non-metal elements, e.g. SiOC, SiOC:H or SiONC
- H01L21/02129—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon the material containing Si, O, and at least one of H, N, C, F, or other non-metal elements, e.g. SiOC, SiOC:H or SiONC the material being boron or phosphorus doped silicon oxides, e.g. BPSG, BSG or PSG
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02107—Forming insulating materials on a substrate
- H01L21/02225—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer
- H01L21/0226—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process
- H01L21/02263—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process deposition from the gas or vapour phase
- H01L21/02271—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process deposition from the gas or vapour phase deposition by decomposition or reaction of gaseous or vapour phase compounds, i.e. chemical vapour deposition
Abstract
Description
본 발명은 반도체장치의 게이트 콘택 및 그 형성방법에 관한 것으로서, 특히, 폴리실리콘과 금속으로 이루어진 적층구조의 게이트에 대한 게이트 콘택을 하부에 위치한 폴리실리콘층 표면까지 연장되도록 형성하여 폴리실리콘과 금속 사이에 형성되는 기생캐패시턴스 성분을 제거하여 신호지연을 정확히 예측하도록 하여 반도체장치의 신뢰성을 개선하도록 한 반도체장치의 금속-실리콘 게이트 콘택 및 그 형성방법에 관한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a gate contact of a semiconductor device and a method for forming the same. In particular, a gate contact for a gate of a multilayer structure made of polysilicon and a metal is formed to extend to a surface of a polysilicon layer located below the polysilicon and a metal. The present invention relates to a metal-silicon gate contact of a semiconductor device and a method for forming the semiconductor device, which remove the parasitic capacitance component formed in the semiconductor device to accurately predict the signal delay to improve the reliability of the semiconductor device.
반도체장치의 고집적화에 따라 셀 구조의 미세화와 함께 게이트 형성물질의 금속화가 필수적이지만, 게이트 금속에 인가전압을 안정된 시간지연을 갖도록 게이트 콘택을 형성하는 것이 용이하지 않다. 왜냐하면, 현재까지는 게이트를 금속만으로 형성하기는 기술적으로 곤란하고 폴리실리콘과 금속 적층구조의 게이트를 형성하는 것이 가능하기 때문이다. 그러나, 이러한 적층구조의 게이트는 폴리실리콘과 금속 사이의 계면에 소정의 막이 형성되어 기생캐패시터를 형성하여 불안정한 신호지연을 초래한다.Although the metallization of the gate forming material together with the miniaturization of the cell structure is essential with the high integration of the semiconductor device, it is not easy to form the gate contact to have a stable time delay of the applied voltage to the gate metal. This is because, until now, it is technically difficult to form the gate using only metal, and it is possible to form a gate of a polysilicon and a metal laminated structure. However, such a laminated gate has a predetermined film formed at the interface between the polysilicon and the metal to form a parasitic capacitor, resulting in unstable signal delay.
즉, 반도체장치의 고집적화에 따라 트랜지스터의 게이트를 금속으로 형성하고자 하는 것이 현재의 추세이고, 이는 소자의 고집적화 및 고속화에 필수적인 요소이다. 그러나, 금속 게이트는 특성상 폴리실리콘과의 계면에 소정의 물질층을 형성하게 되고, 이러한 물질층은 저항 성분과 함께 불안정한 기생 캐패시턴스를 유발하여 게이트에 인가되는 전압 또는 신호를 정확한 타이밍으로 전달하지 못하게 만든다.That is, the current trend is to form the gate of the transistor with a metal in accordance with the high integration of the semiconductor device, which is an essential element for high integration and high speed of the device. However, metal gates, by their nature, form a layer of material at the interface with polysilicon, which, together with the resistive components, causes unstable parasitic capacitances, preventing the voltage or signal applied to the gate from being delivered at the correct timing. .
일반적으로, 반도체장치는 수 많은 NMOS, PMOS 트랜지스터들로 구성되어 있다. 예를 들어, 도 2에 도시된 바와 같이, 이러한 소자들이 연속적으로 연결되어 인버터를 구성할 경우 최초의 소자에 입력된 신호는 최종적으로 소정 시간만큼 지연된 지연신호를 발생시킨다. 그러나, 이러한 지연신호의 지연량은 정확도가 생명인데, 적층구조의 게이트전극사이에 개재된 물질층으로 인하여 원하는 지연신호가 발생되지 않고 오차를 갖는 지연신호가 발생된다. 또한, 지연신호의 타이밍뿐만 아니라 신호의 파형까지도 변하는 경우가 발생한다. 심한 경우에는 지연회로를 구성하는 최종인버터에서 신호(보통 펄스형태를 가짐) 자체가 발생하지 않는 경우도 발생한다.In general, a semiconductor device is composed of many NMOS and PMOS transistors. For example, as shown in FIG. 2, when these devices are connected in series to form an inverter, a signal input to the first device generates a delay signal that is finally delayed by a predetermined time. However, the delay amount of the delay signal is accurate, and the delayed signal having an error is generated without the desired delay signal due to the material layer interposed between the gate electrodes of the stacked structure. In addition, not only the timing of the delay signal but also the waveform of the signal may occur. In severe cases, a signal (usually in the form of a pulse) does not occur in the final inverter constituting the delay circuit.
도 1a와 도 1b는 종래 기술에 따라 제조된 게이트 콘택부위에 대한 단면도와 그에 따른 등가회로도이다.1A and 1B are cross-sectional views and equivalent circuit diagrams of gate contact portions manufactured according to the prior art.
도 1a와 도 1b를 참조하면, 반도체기판인 실리콘기판(10)상에 게이트산화막(11)을 개재한 게이트(12,13,14)가 적층구조로 형성되어 있다. 게이트(14)상에는 게이트 콘택부위를 정의하는 게이트콘택홀이 형성된 층간절연층(15)이 형성되어 있다. 도시되지는 않았지만, 게이트콘택홀은 도전성 플러그로 충전되고 플러그는 이웃한 소자들에 전기적으로 연결된다.1A and 1B, gates 12, 13, and 14 having a gate oxide film 11 interposed therebetween are formed on a silicon substrate 10, which is a semiconductor substrate. An interlayer insulating layer 15 having a gate contact hole defining a gate contact portion is formed on the gate 14. Although not shown, the gate contact hole is filled with a conductive plug and the plug is electrically connected to neighboring devices.
적층구조로 이루어진 게이트를 살펴보면, 하부에 불순물로 도핑된 폴리실리콘층(12)이 게이트산화막(11)상에 위치하고, 폴리실리콘층(12)상에는 부산물질층(13)이 얇게 형성되어 있고, 부산물질층(13)상에 금속층(14)이 적층구조를 이루고 있다.Referring to the gate having a stacked structure, a polysilicon layer 12 doped with an impurity in the lower portion is disposed on the gate oxide layer 11, and a by-product layer 13 is formed on the polysilicon layer 12. The metal layer 14 is stacked on the material layer 13.
따라서, 부산물질층(13)은 저항성과 유전성을 동시에 갖기 때문에 금속층(14)과 폴리실리콘층(12) 사이에 개재되어 기생 캐패시터를 구성하고 저항성분과 함께 병렬 RC회로를 구성하게 된다.Therefore, since the by-product material layer 13 has both resistance and dielectric property, the parasitic capacitor is interposed between the metal layer 14 and the polysilicon layer 12 to form a parallel RC circuit together with the resistance component.
결국, 이러한 기생성분으로 인하여 게이트를 통하여 트랜지스터에 인가되는 신호의 타이밍 등의 정확성이 저하되거나 심한 경우 신호 자체가 소실되는 문제점이 있다.As a result, due to such parasitic components, accuracy such as timing of a signal applied to the transistor through the gate is degraded or, in severe cases, the signal itself is lost.
따라서, 본 발명의 목적은 폴리실리콘과 금속으로 이루어진 적층구조의 게이트에 대한 게이트 콘택을 하부에 위치한 폴리실리콘층 표면까지 연장되도록 형성하여 폴리실리콘과 금속 사이에 형성되는 기생캐패시턴스 성분을 제거하여 신호지연을 정확히 예측하도록 하여 반도체장치의 신뢰성을 개선하도록 한 반도체장치의 금속-실리콘 게이트 콘택 및 그 형성방법을 제공하는 데 있다.Accordingly, an object of the present invention is to form a gate contact for a gate of a laminated structure made of polysilicon and a metal to extend to the surface of the polysilicon layer located below to remove the parasitic capacitance component formed between the polysilicon and the metal to delay the signal. The present invention provides a metal-silicon gate contact of a semiconductor device and a method for forming the semiconductor device to accurately predict the accuracy of the semiconductor device.
상기 목적을 달성하기 위한 본 발명에 따른 반도체장치의 게이트 콘택은 소자활성영역과 소자격리영역이 정의된 반도체 기판과, 상기 기판상에 차례로 형성된 게이트절연막, 폴리실리콘층, 부산물질층, 금속층, 층간절연층과, 상기 층간절연층, 금속층, 부산물질층을 관통하여 상기 폴리실리콘층의 소정부위 표면을 노출시키는 게이트콘택홀과, 상기 게이트콘택홀을 충전하는 도전성 플러그를 포함하여 이루어진다.The gate contact of the semiconductor device according to the present invention for achieving the above object is a semiconductor substrate having a device active region and a device isolation region, a gate insulating film, a polysilicon layer, a by-product material layer, a metal layer, an interlayer formed sequentially on the substrate And an insulating layer, a gate contact hole penetrating the interlayer insulating layer, a metal layer, and a by-product layer to expose a surface of a predetermined portion of the polysilicon layer, and a conductive plug filling the gate contact hole.
상기 목적을 달성하기 위한 본 발명에 따른 반도체장치의 게이트 콘택 형성방법은 반도체 기판상에 절연막을 하부에 개재하고 폴리실리콘층과 금속층을 차례로 적층하는 제 1 단계와, 상기 금속층, 폴리실리콘층, 절연막을 패터닝하여 잔류한 상기 금속층과 폴리실리콘층으로 이루어진 게이트전극과 잔류한 상기 절연막으로 이루어진 게이트절연막을 형성하는 제 2 단계와, 상기 게이트전극을 이용하여 상기 반도체기판의 노출된 부위에 불순물 도핑영역을 형성하는 제 3 단계와, 상기 게이트전극을 포함하는 상기 기판상에 층간절연층을 형성하는 제 4 단계와, 상기 층간절연층의 게이트콘택 형성영역을 제거하여 상기 금속층 표면을 노출시키는 제 1 콘택홀을 형성하는 제 5 단계와, 노출된 상기 금속층 표면을 제거하여 상기 제 1 콘택홀에서 연장되며 상기 폴리실리콘층의 상부 표면을 노출시키는 제 2 콘택홀을 형성하는 제 6 단계와, 상기 제 1 및 제 2 콘택홀을 도전성 플러그로 충전시키는 제 7 단계를 포함하여 이루어진다.In order to achieve the above object, a method of forming a gate contact of a semiconductor device according to the present invention includes a first step of sequentially stacking a polysilicon layer and a metal layer with an insulating film disposed on a semiconductor substrate, and the metal layer, the polysilicon layer, and an insulating film. Forming a gate insulating film made of the remaining insulating layer and the gate electrode made of the remaining metal layer and polysilicon layer, and forming an impurity doped region in the exposed portion of the semiconductor substrate using the gate electrode. A third step of forming, a fourth step of forming an interlayer insulating layer on the substrate including the gate electrode, and a first contact hole exposing a surface of the metal layer by removing a gate contact forming region of the interlayer insulating layer And a fifth step of forming an extension of the first contact hole by removing the exposed metal layer surface. And a sixth step of forming a second contact hole exposing the top surface of the polysilicon layer, and a seventh step of filling the first and second contact holes with a conductive plug.
도 1a와 도 1b는 종래 기술에 따라 제조된 게이트 콘택부위에 대한 단면도와 그에 따른 등가회로도1A and 1B are cross-sectional views and equivalent circuit diagrams of gate contact portions manufactured according to the prior art.
도 2는 입력신호에 대한 펄스지연을 설명하기 위한 지연회로도2 is a delay circuit diagram illustrating a pulse delay with respect to an input signal.
도 3a와 도 3b는 본 발명에 따라 제조된 게이트 콘택부위에 대한 단면도와 그에 따른 등가회로도3A and 3B are cross-sectional views and equivalent circuit diagrams of gate contact portions fabricated according to the present invention.
도 4a 내지 도 4c는 본 발명에 따른 게이트 콘택 형성방법을 도시한 제조공정 단면도4A through 4C are cross-sectional views illustrating a method of forming a gate contact according to the present invention.
일반적으로 폴리실리콘과 금속의 적층 구조를 갖는 게이트에 형성되는 게이트콘택홀은 게이트상에 위치한 절연층을 제거하여 금속 표면을 노출시키는 구조로 형성되므로, 종래 기술에서는 금속과 폴리실리콘 사이에 개재된 부산물질층으로 부터의 악영향을 배제하기 곤란하였다.In general, the gate contact hole formed in the gate having a laminated structure of polysilicon and metal is formed to have a structure of exposing a metal surface by removing an insulating layer on the gate. It was difficult to rule out adverse effects from the material layer.
이를 해결하기 위하여 NMOS 또는 PMOS 트랜지스터의 게이트 상부에 형성되는 게이트콘택홀을 폴리실리콘이 노출되도록 형성하면, 주변회로 또는 셀에서 일반적으로 게이트콘택홀이 드레인 또는 소스콘택홀과 동일한 공정으로 형성되므로 소스/드레인졍션인 기판의 활성영역까지 파고들게 되는 문제가 발생한다.In order to solve this problem, when the gate contact hole formed on the gate of the NMOS or PMOS transistor is formed to expose the polysilicon, the gate / contact hole is generally formed in the same process as the drain or source contact hole in the peripheral circuit or the cell. There is a problem of digging into the active region of the substrate, which is a drain cushion.
따라서, 본 발명에서는 특정 영역의 게이트에만 폴리실리콘 표면을 노출시키는 게이트콘택홀을 형성하기 위하여 종래 기술에서와 같이 금속 표면을 노출시키는 각각의 제 1 게이트콘택홀을 형성한 다음, 주변회로의 게이트에만 식각마스크를 추가하여 형성한 다음 제 1 게이트콘택홀에서 연장된 제 2 게이트콘택홀을 형성하여 폴리실리콘 표면을 노출시킨다.Therefore, in the present invention, in order to form a gate contact hole exposing the polysilicon surface only to a gate of a specific region, each first gate contact hole exposing a metal surface is formed as in the prior art, and then only to the gate of the peripheral circuit. After forming an etching mask, a second gate contact hole extending from the first gate contact hole is formed to expose the polysilicon surface.
도 2는 입력신호에 대한 펄스지연을 설명하기 위한 지연회로도이다.2 is a delay circuit diagram illustrating a pulse delay with respect to an input signal.
도 2를 참조하면, 인버터들로 나열된 정상신호단과 지연신호단이 도시되어 있다. 지연회로에 입력된 펄스신호(Pulse)는 인버터 체인을 거쳐 주파수, 진폭, 주기 등은 초기 입력신호와 동일하지만 소정 시간만큼 지연되어(delayed) 지연신호(Pulse_D)를 발생시킨다. 이와 같이 초기신호와 지연신호를 이용하여 소저의 회로는 새로운 신호를 발생시킨다.Referring to FIG. 2, a normal signal stage and a delay signal stage listed as inverters are shown. The pulse signal (Pulse) input to the delay circuit is the same as the initial input signal, but the frequency, amplitude, period through the inverter chain is delayed by a predetermined time to generate a delay signal (Pulse_D). In this way, the initial circuit and the delay signal use the source circuit to generate a new signal.
따라서, 본 발명에서는 이러한 지연시간에 오류를 유발하는 기생캐패시턴스 성분을 게이트콘택을 폴리실리콘과 직접 연결되도록 하여 제거하므로, 초기신호와 지연신호간의 정확한 타이밍을 얻을 수 있다.Therefore, in the present invention, since the parasitic capacitance component causing an error in the delay time is removed by directly connecting the gate contact with the polysilicon, accurate timing between the initial signal and the delay signal can be obtained.
이하, 첨부한 도면을 참조하여 본 발명의 실시예를 상세히 설명한다.Hereinafter, with reference to the accompanying drawings will be described an embodiment of the present invention;
도 3a와 도 3b는 본 발명에 따라 제조된 게이트 콘택부위에 대한 단면도와 그에 따른 등가회로도이다.3A and 3B are cross-sectional views and equivalent circuit diagrams of gate contact portions fabricated according to the present invention.
도 3a와 도 3b를 참조하면, 반도체기판인 실리콘기판(30)상에 게이트산화막(31)을 개재한 게이트(32,33,34)가 적층구조로 형성되어 있다. 게이트(34)상에는 게이트 콘택부위를 정의하는 게이트콘택홀이 형성된 층간절연층(35)이 형성되어 있다. 도시되지는 않았지만, 게이트콘택홀은 도전성 플러그로 충전되고 플러그는 이웃한 소자들에 전기적으로 연결된다.Referring to FIGS. 3A and 3B, gates 32, 33, and 34 having a gate oxide film 31 interposed therebetween are formed on a silicon substrate 30, which is a semiconductor substrate. An interlayer insulating layer 35 having a gate contact hole defining a gate contact portion is formed on the gate 34. Although not shown, the gate contact hole is filled with a conductive plug and the plug is electrically connected to neighboring devices.
적층구조로 이루어진 게이트를 살펴보면, 하부에 불순물로 도핑된 폴리실리콘층(32)이 게이트산화막(31)상에 위치하고, 폴리실리콘층(32)상에는 부산물질층(33)이 얇게 형성되어 있고, 부산물질층(33)상에 금속층(34)이 적층구조를 이루고 있다. 이때, 부산물질층(33)은 하부에 위치한 폴리실리콘층(32)상에 금속층(34)을 형성할 경우, 자연적으로 생성되는 부산물로 이루어진다.Looking at the gate formed of a stacked structure, a polysilicon layer 32 doped with an impurity at the bottom is located on the gate oxide film 31, the by-product layer 33 is formed on the polysilicon layer 32 is thin, The metal layer 34 is stacked on the material layer 33. In this case, the by-product layer 33 is formed of a by-product naturally generated when the metal layer 34 is formed on the polysilicon layer 32 disposed below.
따라서, 부산물질층(33)은 저항성과 유전성을 동시에 갖기 때문에 금속층(34)과 폴리실리콘층(32) 사이에 개재되어 기생 캐패시터를 구성하고 저항성분과 함께 병렬 RC회로를 구성하게 된다.Accordingly, since the by-product material layer 33 has both resistance and dielectric property, it is interposed between the metal layer 34 and the polysilicon layer 32 to form a parasitic capacitor and a parallel RC circuit together with the resistance component.
따라서, 본 발명에서는 게이트콘택홀을 층간절연층(35), 금속층(34), 부산물질층(33)을 관통하여 폴리실리콘층(32) 표면을 노출시키도록 형성하므로서 이러한 기생성분을 제거하여 게이트를 통하여 트랜지스터에 인가되는 신호의 타이밍 등의 정확성을 확보한다.Therefore, in the present invention, the gate contact hole is formed to pass through the interlayer insulating layer 35, the metal layer 34, and the by-product material layer 33 to expose the surface of the polysilicon layer 32, thereby removing the parasitic component of the gate. Through this, the accuracy of the timing of the signal applied to the transistor is ensured.
도 4a 내지 도 4c는 본 발명에 따른 게이트 콘택 형성방법을 도시한 제조공정 단면도이다.4A to 4C are cross-sectional views of a manufacturing process illustrating a method of forming a gate contact according to the present invention.
도 4a를 참조하면, 반도체기판인 실리콘기판(40) 상에 게이트절연막(41)으로 열산화막을 소정 두께로 성장시켜 형성한 다음, 게이트의 제 1 층을 형성하기 위한 도핑된 폴리실리콘층(42)을 게이트절연막(41)상에 형성한다. 이때, 폴리실리콘층은 인-시튜 도핑된 폴리실리콘으로 형성하거나 도핑되지 않은 폴리실리콘층을 형성한 다음 이온주입 등으로 도핑시켜 형성할 수 있다.Referring to FIG. 4A, a thermal oxide film is formed on the silicon substrate 40, which is a semiconductor substrate, by using a gate insulating film 41 to grow to a predetermined thickness, and then a doped polysilicon layer 42 for forming a first layer of the gate. ) Is formed on the gate insulating film 41. In this case, the polysilicon layer may be formed by in-situ doped polysilicon or by forming an undoped polysilicon layer and then doping by ion implantation.
그리고, 폴리실리콘층(42)상에 금속층(44)을 소정 두께로 형성한다. 이때, 금속층(44)을 형성하는 이유는 다수개의 셀에 비저항값이 낮고 전압강하없이 고른 전압을 인가할 수 있는 물질로 금속이 적합하기 때문이다. 금속층(44)은 스퍼터링 등의 방법으로 귀금속(noble metal)을 증착하여 형성할 수 있다.The metal layer 44 is formed on the polysilicon layer 42 to have a predetermined thickness. At this time, the reason why the metal layer 44 is formed is because the metal is suitable as a material capable of applying a uniform voltage without a voltage drop to a plurality of cells with a low resistivity value. The metal layer 44 may be formed by depositing a noble metal by sputtering or the like.
그러나, 상기와 같이 폴리실리콘층(42)상에 금속층(44)을 형성하는 경우, 금속과 실리콘의 반응에 의하여 부산물질층(43)이 생성되어 기생캐패시턴스 및 저항을 발생시킨다.However, when the metal layer 44 is formed on the polysilicon layer 42 as described above, the by-product material layer 43 is generated by the reaction of the metal and silicon to generate parasitic capacitance and resistance.
도시되지는 않았지만, 금속층/폴리실리콘층과 게이트절연막을 포토리쏘그래피로 패터닝하여 게이트(44,43,42)와 게이트절연막(41)의 형태를 완성하고, 노출된 기판의활성영역에 기판과 반대되는 도전형의 도핑영역을 이온주입 등으로 형성하여 트랜지스터 소자를 제조하는 단계를 진행한다.Although not shown, the metal layer / polysilicon layer and the gate insulating film are patterned by photolithography to complete the shapes of the gates 44, 43, 42 and the gate insulating film 41, and opposite the substrate in the exposed area of the active substrate. The step of manufacturing a transistor device is performed by forming a conductive doped region by ion implantation or the like.
그 다음, 게이트(44) 표면을 포함하는 기판의 전면에 층간절연층(45)으로 HLD(high temperature low pressure dielectric) 또는 BPSG(boro phospho silicate glass)를 화학기상증착으로 형성한다.Next, a high temperature low pressure dielectric (HLD) or boro phospho silicate glass (BPSG) is formed on the front surface of the substrate including the surface of the gate 44 by chemical vapor deposition.
그리고, 층간절연층(45)의 소정부위를 포토리쏘그래피로 제거하여 게이트콘택 영역긔 금속층(44) 표면을 노출시키는 제 1 콘택홀을 형성한다. 이때, 제 1 식각마스크(도시안함)로 포토레지스트패턴을 형성하여 제 1 콘택홀을 형성한 후 제 1 식각마스크를 제거한다.A predetermined portion of the interlayer insulating layer 45 is removed by photolithography to form a first contact hole exposing the surface of the gate contact region 긔 the metal layer 44. In this case, the photoresist pattern is formed using the first etching mask (not shown) to form the first contact hole, and then the first etching mask is removed.
그 다음, 제 1 콘택홀이 형성된 층간절연층(45)상에 다시 포토레지스트를 도포한 후, 노광 및 현상을 실시하여 제 1 콘택홀에 의하여 노출되었던 게이트콘택 형성영역의 금속층(44) 표면을 다시 노출시키는 제 2 식각마스크(46)인 포토레지스트패턴(46)을 형성한다. 이때, 제 2 식각마스크(46)의 직경을 제 1 식각마스크 보다 약간 크게 형성하여 층간절연층(45)의 일부 표면도 노출시켜 사진공정 마진을 개선한다.Then, the photoresist is again applied on the interlayer insulating layer 45 on which the first contact hole is formed, and then exposed and developed to cover the surface of the metal layer 44 of the gate contact forming region that was exposed by the first contact hole. A photoresist pattern 46 that is a second etching mask 46 that is exposed again is formed. In this case, the diameter of the second etching mask 46 is slightly larger than that of the first etching mask, thereby exposing a part of the surface of the interlayer insulating layer 45 to improve a photo process margin.
도 4b를 참조하면, 포토레지스트로 이루어진 제 2 식각마스크로 보호되지 않는 노출된 폴리실리콘층을 건식식각 등의 비등방성식각으로 제거하여 폴리실리콘층(42)의 표면을 노출시키는 제 1 콘택홀이 연장된 제 2 콘택홀을 형성한다. 이때, 금속층(440)이 제거됨에 따라 노출되는 부산물질층(430)도 확실하게 제거되도록 과도식각을 실시한다. 이러한 식각과정에서 층간절연층(450)의 노출된 부분도 일부 식각된다.Referring to FIG. 4B, the first contact hole exposing the surface of the polysilicon layer 42 by removing the exposed polysilicon layer, which is not protected by the second etching mask made of photoresist, by anisotropic etching such as dry etching, An extended second contact hole is formed. At this time, the over-etching is performed so that the by-product layer 430 exposed as the metal layer 440 is removed is also removed. In this etching process, the exposed portion of the interlayer insulating layer 450 is also partially etched.
그리고, 제 2 콘택홀에 의하여 노출된 폴리실리콘층(44) 표면에 불순물 이온주입을 실시하여 콘택저항을 감소시키는 단계를 추가로 실시할 수 있다.In addition, the contact resistance may be further reduced by implanting impurity ions into the surface of the polysilicon layer 44 exposed by the second contact hole.
도 4c를 참조하면, 제 2 식각마스크를 산소 애슁(O2 ashing) 등의 방법으로 제거하여 층간절연층(450)의 상부 표면을 완전히 노출시킨다.Referring to FIG. 4C, the upper surface of the interlayer insulating layer 450 is completely exposed by removing the second etching mask by using oxygen ashing or the like.
이후, 도시되지는 않았지만, 노출된 폴리실리콘층(42) 표면과 접촉하도록 제 2 콘택홀을 도전성 플러그로 충전하여 게이트콘택을 완성한다.Thereafter, although not shown, the second contact hole is filled with the conductive plug to contact the exposed surface of the polysilicon layer 42 to complete the gate contact.
따라서, 본 발명은 게이트 콘택부에서의 기생캐패시턴스와 저항을 제거하므로서 신호지연을 정확히 예측하여 소자설계가 용이하고, 실제로 소자를 제작시 시뮬레이션 결과와 실측치가 동일하게 나오므로 소자설계 마진이 개선되며, 또한, 본 발명의 게이트콘택을 갖춘 지연회로는 셀의 비트라인에서 센스앰프로 데이터를 옮기는데 필요한 신호생성에 사용되므로 칩의 동작특성(Cas Latency)을 결정하는데 유리한 장점이 있다.Therefore, the present invention facilitates device design by accurately predicting signal delay by eliminating parasitic capacitance and resistance in the gate contact portion, and improves device design margin because the simulation results and actual measurements are the same when the device is actually manufactured. In addition, since the delay circuit having the gate contact of the present invention is used for signal generation required to transfer data from the bit line of the cell to the sense amplifier, there is an advantageous advantage in determining the cas characteristics of the chip.
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| US7776687B2 (en) | 2006-05-03 | 2010-08-17 | Samsung Electronics Co., Ltd. | Semiconductor device having a gate contact structure capable of reducing interfacial resistance and method of forming the same |
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| Publication number | Priority date | Publication date | Assignee | Title |
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| US7776687B2 (en) | 2006-05-03 | 2010-08-17 | Samsung Electronics Co., Ltd. | Semiconductor device having a gate contact structure capable of reducing interfacial resistance and method of forming the same |
| US8188532B2 (en) | 2006-05-03 | 2012-05-29 | Samsung Electronics Co., Ltd. | Semiconductor device having a gate contact structure capable of reducing interfacial resistance |
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