KR20020010993A - Non-burst mode sopport appatatus - Google Patents

Abstract

PURPOSE: A non-burst mode support system is provided to support a burst mode when making an access to an SDRAM so that it can increase a speed of making an access to an external memory. CONSTITUTION: The system comprises an external SDRAM(100) and a CPU(200). The CPU(100) embeds an SDRAM controller(12) and a burst data buffer(11). The SDRAM controller(12) controls processes of reading data from or writing data to address areas of the SDRAM via a data bus. The burst data buffer(11) transmits or receives some bits of data between the external SDRAM(100) and the SDRAM controller(12). In the case of making an access to an SDRAM using a 8 bit data bus, a single burst node, a 2-length burst mode or a 4-length burst mode can be adopted as a data access method. If the 4-length burst mode is used in the SDRAM and an internal data size is set as a 32 bit, the burst data buffer(11) divides the 32 bit data into four 8-bit data and transmits the 8-bit unit data with the SDRAM controller(12) and the SDRAM(100).

Description

NON-BURST MODE SOPPORT APPATATUS}

The present invention relates to a non-burst mode support apparatus, and more particularly, to a non-burst mode support apparatus capable of supporting a burst mode during data access with an SDRAM.

In general, the data of the non-burst mode support CPI, does not support the burst mode data transmission supported by SDRAM, will be described in detail with reference to the accompanying drawings, such a conventional device.

FIG. 1 is a block diagram showing the structure of a conventional non-burst mode supporting apparatus. As shown in FIG. 1, 8-bit, 16-bit, or 32-bit data is stored in an address area of an external SDRAM 10 in a single data access time. The operation of the present invention constituted by the CPI 20 that supports the non-burst mode by incorporating the SDRAM controller 1 for controlling to write or read through a data bus of a predetermined bit will be described.

First, in the case of read access, when the SDRAM controller 1 applies the read enable signal to the SDRAM 10 in a low state, the SDRAM controller 1 changes the respective addresses so that the SDRAM 10 may change. When applied to the CPI 20, the data corresponding to the address is read through the data bus.

On the contrary, in the case of write access, when the SDRAM controller 1 applies the write enable signal to the SDRAM 10 in a low state, the SDRAM controller 1 changes the respective addresses so that the SDRAM 10 may change. Upon application to the CPI 20, predetermined data is written to the area of the address via a data bus.

In this case, the ROM may be used in the same manner as in the case of using the ROM instead of the SDRAM 10.

If the DRAM access is read, the data is read according to the column address according to the cas signal CAS when the read access is performed. On the other hand, when the write access is performed, the data is read in the area corresponding to the column address according to the cas signal CAS. Light it.

However, the non-burst mode support apparatus according to the related art does not support the burst mode used in the SDRAM when performing an interface with the SDRAM.

Accordingly, an object of the present invention is to provide a non-burst mode support apparatus capable of improving an external memory access speed by supporting a burst mode when accessing data with an SDRAM.

1 is a block diagram showing the configuration of a conventional non-burst mode support apparatus.

Figure 2 is a block diagram showing the configuration of the non-burst mode support apparatus of the present invention.

Fig. 3 is a timing diagram of an internal signal for data write in burst mode in Fig. 2;

Fig. 4 is a timing diagram of an internal signal for data read in burst mode in Fig. 2;

***** Description of the symbols for the main parts of the drawings *****

100: S-DRAM 200: CPI

11: Burst data buffer 12: SDRAM controller

In order to achieve the above object, the present invention incorporates an SDRAM controller for controlling 8-bit, 16-bit, or 32-bit data to be written or read through the data bus in an address area of an external SDRAM within a single data access time. In the non-burst mode supporting apparatus comprising CPI supporting the non-burst mode, the non-burst mode supporting apparatus is connected to the CPI side of the data bus and is externally connected in accordance with the size and internal data size of the data bus in burst data mode. And a burst data buffer between the SDRAM and the SDRAM controller to exchange data of a predetermined bit through a data bus.

Hereinafter, the operation and effects of the non-burst mode support apparatus according to the present invention will be described in detail with reference to the accompanying drawings.

Figure 3 is a block diagram showing the configuration of the non-burst mode support apparatus of the present invention, the general configuration is the same as shown here, but is built-in connected to the CPI 200 side of the data bus, in the burst data mode, According to the size of the data bus and the size of the internal data, the configuration including the burst data buffer 11 for exchanging predetermined bits of data through the data bus between the external SDRAM 100 and the SDRAM controller 12 is different, and The same operation of the present invention will be described.

First, since the general data access operation is the same as the conventional one, it is omitted, and the operation in the burst mode according to the present invention will be described.

First, when accessing data with the SDRAM 100 using an 8-bit data bus, the data access method may use a single burst mode, a two-length burst mode, and a four-length burst mode. .

When the 4-Length burst mode is used in the SDRAM 100, when the internal data size is set to 32 bits, the burst data buffer 11 may store data with the SDRAM controller 12 and the SDRAM 100. Is divided into four 8-bit units.

Here, FIG. 3 is an internal signal waveform diagram at the time of writing when the 4-Length burst mode is used in the SDRAM 100 and the internal data size is set to 32 bits, and FIG. 4 is an SDRAM 100. ) Is the internal signal waveform at the time of data read when the 4-length burst mode is used and the internal data size is set to 32 bits.

In the case of using the 2-Length burst mode in the SDRAM 100, when the internal data size is set to 16 bits, the burst data buffer 11 divides data into two 8-bit units. do.

At this time, if the internal data size is set to 8 bits, the S-RAM 100 operates in the single burst mode.

On the other hand, when accessing the data and the SDRAM 100 using the data bus 16 bits, the data access method may be used in a single burst mode, two-length (Length) burst mode.

When using the 2-Length burst mode in the SDRAM 100, when the internal data size is set to 32 bits, the burst data buffer 11 may store data with the SDRAM controller 12 and the SDRAM 100. Is divided into two 16-bit units.

At this time, when the internal data size is set to 16 bits, the S-RAM 100 operates in the single burst mode.

Therefore, in the case of the SDRAM 100 using the 32-bit data bus, the data access method can be used only in the single burst mode. The burst data buffer 11 sets the internal data size to 32 bits so that the SDRAM controller 12 And exchange data with the SDRAM 100 in 32-bit units.

As described in detail above, the present invention has an effect of improving an external memory access speed by embedding a burst data buffer in a CPI supporting a non-burst mode, and supporting a burst mode when performing a memory access.

Claims (10)

CSI-E supports non-burst mode by embedding an SDRAM controller that controls 8-bit, 16-bit or 32-bit data to be written or read through the data bus in the address area of external SDRAM within a single data access time. In the non-burst mode support device, Built-in connection to the CPI side of the data bus, in burst data mode, according to the size of the data bus and the internal data size, a burst is transmitted and received a predetermined bit of data between the external SDRAM and the SDRAM controller through the data bus. Non-burst mode support device, characterized in that it comprises a data buffer. The apparatus of claim 1, wherein the data access method is divided into a single burst mode, a two-length burst mode, and a four-length burst mode when the size of the data bus is 8 bits. The method of claim 2, wherein when the data is accessed in the 4-length burst mode, when the internal data size is set to 32-bit, data is written or read into the SDRAM controller and the SDRAM in four 8-bit units. Non-burst mode support. The method of claim 2, wherein when the data is accessed in the two-length burst mode, when the internal data size is set to 16-bit, data is written or read to the SDRAM controller and the SDRAM in two 8-bit units. Non-burst mode support. The non-burst mode supporting apparatus of claim 2, wherein when the data is accessed in the single burst mode and the internal data size is set to 8 bits, data is written or read to the SDRAM controller and the SDRAM in 8-bit units. . The apparatus of claim 1, wherein when the size of the data bus is 16 bits, the data access method is classified into a single burst mode and a two-length burst mode. 7. The method of claim 6, wherein when the data is accessed in the two-length burst mode, when the internal data size is set to 32-bit, data is written or read with the SDRAM controller and the SDRAM in two 16-bit units. -Burst mode support device. The non-burst mode supporting apparatus of claim 6, wherein when the data is accessed through a single burst bus, when the internal data size is set to 16 bits, data is written or read with the SDRAM controller and the SDRAM in units of 16 bits. The apparatus of claim 1, wherein if the size of the data bus is 32 bits, the data access method is used only in a single burst mode. The non-burst mode supporting apparatus of claim 9, wherein when the data is accessed in the single burst mode, the internal data size is set to 32 bits to write or read data to the SDRAM controller and the SDRAM in 32-bit units.