KR20020010199A - Array substrate for Liquid crystal display and method for fabricating thereof - Google Patents

Array substrate for Liquid crystal display and method for fabricating thereof Download PDF

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Publication number
KR20020010199A
KR20020010199A KR1020000043483A KR20000043483A KR20020010199A KR 20020010199 A KR20020010199 A KR 20020010199A KR 1020000043483 A KR1020000043483 A KR 1020000043483A KR 20000043483 A KR20000043483 A KR 20000043483A KR 20020010199 A KR20020010199 A KR 20020010199A
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KR
South Korea
Prior art keywords
electrode
layer
substrate
metal layer
gate
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KR1020000043483A
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Korean (ko)
Inventor
류순성
곽동영
김후성
정유호
김용완
박덕진
이우채
Original Assignee
구본준, 론 위라하디락사
엘지.필립스 엘시디 주식회사
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Priority to KR1020000043483A priority Critical patent/KR20020010199A/en
Publication of KR20020010199A publication Critical patent/KR20020010199A/en

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Abstract

PURPOSE: An array substrate used for a liquid crystal display and a method of fabricating the substrate are provided, the array substrate creating no short-circuiting between a pixel electrode and a data line, the method fabricating a liquid crystal display having a uniform distance between the data line and pixel electrode. CONSTITUTION: An array substrate used for a liquid crystal display includes a transparent substrate, a gate electrode(126) and a gate line(113) formed on the substrate, and an active layer formed on the gate electrode having an insulating layer between the active layer and the gate electrode. The array substrate further has a source electrode(128) partially superposed on one side of the active layer, a drain electrode(130) located having a predetermined distance from the source electrode, and a data line(115) intersecting the gate line having an insulating layer between the data line and gate line to define a pixel region. The substrate also has a groove pattern(114) having a predetermined width and length at both sides of the data line running on the pixel region in the center, and a pixel electrode(117) formed on the pixel region, having a predetermined distance from the data line, having the groove pattern between the data line and the pixel electrode.

Description

Array substrate for liquid crystal display device and manufacturing method thereof

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a liquid crystal display device. In particular, it is possible to prevent a short circuit defect between the pixel electrode and the data wiring due to a foreign material during the manufacturing process of the array substrate for the liquid crystal display device, which is fabricated with four masks. The present invention relates to a method of manufacturing a constantly configured array substrate for a liquid crystal display device.

In general, the driving principle of the liquid crystal display device uses the optical anisotropy and polarization of the liquid crystal. Since the liquid crystal is thin and long in structure, the liquid crystal has directivity in the arrangement of molecules, and the direction of the molecular arrangement can be controlled by artificially applying an electric field to the liquid crystal.

Accordingly, when the molecular arrangement direction of the liquid crystal is arbitrarily adjusted, the molecular arrangement of the liquid crystal is changed, and light is refracted in the molecular arrangement direction of the liquid crystal due to optical anisotropy to express image information.

Currently, the active matrix liquid crystal display (AM-LCD) in which the aforementioned thin film transistor and pixel electrodes connected to the thin film transistor are arranged in a matrix manner is attracting the most attention because of its excellent resolution and ability to implement video.

In general, the structure of a liquid crystal panel, which is a basic component of a liquid crystal display, will be described.

1 is an exploded perspective view schematically illustrating a general liquid crystal display device.

As shown in the drawing, a general liquid crystal display includes a color filter 7 including a black matrix 6 and a sub color filter (red, green, blue) 8 and an upper portion on which a transparent common electrode 18 is formed on the color filter. And a lower substrate 22 having an array wiring including a substrate 5, a pixel region P and a pixel electrode 17 formed on the pixel region, and a switching element T. The upper substrate 5 and The liquid crystal 14 is filled between the lower substrates 22.

The lower substrate 22 is also referred to as an array substrate, and the thin film transistor T, which is a switching element, is positioned in a matrix type, and the gate wiring 13 and the data wiring 15 passing through the plurality of thin film transistors cross each other. Is formed.

The pixel area P is an area defined by the gate line 13 and the data line 15 intersecting each other. The pixel electrode 17 formed on the pixel region P uses a transparent conductive metal having relatively high light transmittance, such as indium-tin-oxide (ITO).

In the liquid crystal display device configured as described above, the liquid crystal layer 14 disposed on the pixel electrode 17 is oriented by a signal applied from the thin film transistor T, and the liquid crystal layer is aligned according to the degree of alignment of the liquid crystal layer. The image can be represented in a manner that controls the amount of light that passes through layer 14.

The gate wiring 13 transfers a pulse voltage driving a gate electrode, which is a first electrode of the thin film transistor T, and the data wiring 15 receives a source electrode, which is a second electrode of the thin film transistor T. It is a means for transmitting the driving signal voltage.

FIG. 2 is an enlarged plan view illustrating some pixels of an array substrate for a liquid crystal display device manufactured by a conventional four mask process.

As shown, the array substrate 22 is composed of a plurality of pixels P, and the pixels are thin film transistors T and pixel electrodes 17 which are switching elements. It consists of a storage capacitor (C).

The thin film transistor T includes a gate electrode 26, a source electrode 28, a drain electrode 30, and an active layer 29 ′, and the source electrode 28 includes a data line 15. The gate electrode 26 is connected to the gate line 13 defining the pixel region P by crossing the data line 15.

In this case, the data line 15 and the pixel electrode 17 are configured to be spaced apart from each other by a predetermined interval, and when the array substrate is manufactured using four masks, the side surface of the data line 15 is exposed.

Such a structure has the pixel electrode 17 and the data line 15 due to a foreign substance which may exist between the pixel electrode 17 and the data line 15 during the photoresist process of patterning the pixel electrode 17. Short circuit portion A is generated in the liver, causing short circuit failure.

In addition, after the data line 15 is formed, a mask process for patterning the pixel electrode 17 is performed between the data line 15 and the pixel electrode 17 by misalignment of a mask and a substrate. The spacing is not constant, which causes variations in the panel and non-uniformity of capacitance occurring between the data wiring 15 and the pixel electrode 17.

Hereinafter, a method of manufacturing a conventional array substrate for a liquid crystal display device will be described with reference to FIGS. 3A to 3D.

3A to 3D are sectional views taken along line III-III of the process plan view and FIG. 2 according to the process sequence.

In general, the structure of a thin film transistor used in a liquid crystal display is an inverted staggered structure. This is because the structure is simple and the performance is excellent.

First, a foreign material or an organic material is removed from the substrate 22, and the metal film is deposited by sputtering after cleaning to improve the adhesion between the metal film of the gate material to be deposited and the glass substrate. .

FIG. 3A illustrates a first mask step of forming a gate wiring and a gate electrode 26. A plurality of gate wirings 13 extending in one direction are formed by depositing and patterning a first conductive metal layer on a substrate 22. A gate electrode 26 protruding from the wiring is formed.

Here, part of the gate wiring 13 is used as the first electrode 13 ′ of the storage capacitor.

In general, the material of the gate electrode 26 constituting the active matrix substrate is mainly composed of aluminum having low resistance in order to reduce the RC delay, but pure aluminum has low chemical resistance to corrosion and subsequent high temperature processes. Since wiring defects are caused by the formation of hillocks, aluminum wirings may be used in the form of alloys or laminated structures may be applied.

Next, an amorphous silicon layer 31 containing a gate insulating film 27, a pure amorphous silicon layer 29, and impurities on the entire surface of the substrate 22 on which the gate electrode 26 and the gate wiring 13 are formed. And the second conductive metal layer 28 'are laminated.

3B is a second mask step of forming an active channel, patterning the second conductive metal layer so that the impurity amorphous silicon layer 31 is exposed on the gate electrode 26 as intended.

Next, the exposed impurity amorphous silicon layer is etched using the patterned second conductive metal layer as a mask to expose the active channel 29 ′ which is a part of the pure amorphous silicon layer 31.

Next, an insulating material is deposited on the substrate on which the patterned second conductive metal layer is formed to form a protective layer 33 that is a second insulating layer.

FIG. 3C is a third mask step of patterning a protective layer to form data wiring. A source formed on the left side of the active channel 29 ′ patterned on the gate electrode 26 by patterning the protective layer 33. An electrode 28, a drain electrode 30 spaced apart from the electrode 28, and a data line 15 formed in one direction perpendicular to the source electrode 28 are formed.

At the same time, an island-type storage second electrode 32 is formed on a portion of the gate line defining the pixel area.

In this case, the data line 15, the drain electrode 30, and the storage capacitor part C have a vertical shape with the side surface of the metal layer exposed.

3D is a four mask step for forming a pixel electrode. A transparent conductive metal is deposited and patterned on the substrate 22 on which the patterned protective layer 33 is formed to form the pixel electrode 17.

The pixel electrode 17 contacts the side surface of the drain electrode 30 and extends over the second storage electrode 32 through the pixel region P.

In this way, a conventional array substrate for a liquid crystal display device can be manufactured.

However, foreign matter may flow in the photoresist process for patterning the pixel electrode 17 to cause a short circuit portion A between the pixel electrode 17 and the data wiring 15 during the patterning of the pixel electrode 17. have.

In addition, the gap K of the pixel electrode on one side and the distance K + α of the pixel electrode on the other side may be configured differently with respect to the data wiring by misalignment in the exposing using four masks. .

In such a configuration, in particular, there is a problem that image quality defects may be caused by the capacitor component C dp occurring in a portion where the pixel electrode 30 and the data wiring 15 are adjacent to each other.

The liquid crystal display device array substrate according to the present invention for solving the above problems does not generate a short circuit defect between the pixel electrode and the data wiring as described above, and the liquid crystal display device having a constant gap between the data wiring and the pixel electrode. The purpose is to provide a method of making.

1 is an exploded perspective view illustrating a general liquid crystal display device;

2 is an enlarged plan view showing some pixels of a conventional array substrate for a liquid crystal display device;

3A to 3D are cross-sectional views illustrating a process sequence, taken along line III-III of FIG. 2,

4 is an enlarged plan view showing some pixels of an array substrate for a liquid crystal display device according to the present invention;

5A through 5E are cross-sectional views illustrating a process sequence by cutting along line V-V of FIG. 4.

6 is a plan view and a cross-sectional view illustrating a portion of the data line and the pixel electrode.

<Explanation of symbols for the main parts of the drawings>

113: gate wiring 115: data wiring

122: substrate 126: gate electrode

128: drain electrode 130: source electrode

129`: active channel

An array substrate for a liquid crystal display device according to the present invention for achieving the above object is a transparent substrate; A gate electrode and a gate wiring formed by patterning a first metal layer on the substrate; An active layer formed on the gate electrode with an insulating layer interposed therebetween; A source wiring overlapping one side of the active layer formed by patterning a second metal layer, a drain electrode spaced apart from the predetermined gap, and a gate wiring and an insulating layer intersecting each other to define a pixel region; A bone pattern composed of a predetermined width and length on both sides of the data line passing through the pixel region, and having a lower substrate exposed; And a pixel electrode formed on the pixel area and spaced apart from the data line with the valley pattern therebetween.

The first metal layer and the second metal layer is one selected from the group of conductive metals including aluminum (Al), aluminum alloy, molybdenum (Mo), tungsten (W) and the like.

The pixel electrode may be one selected from a group of transparent conductive metals including ITO and IZO.

According to another aspect of the present invention, there is provided a method of manufacturing an array substrate for a liquid crystal display device, the method including: providing a substrate; Depositing and patterning a first conductive metal on the substrate to form a gate electrode and a gate wiring; Stacking a gate insulating layer, an amorphous silicon layer, an impurity amorphous silicon, and a second conductive metal layer on an entire surface of the substrate on which the first conductive metal layer is patterned; Patterning the second conductive metal layer to expose a valley pattern between the active channel and the data line to be formed later and the pixel electrode; Depositing an insulating material on the substrate on which the second conductive metal layer is patterned to form a protective layer; The protective layer, the second conductive metal layer, and the pure amorphous silicon layer are etched to form a data line defining a pixel region by crossing the source electrode, the drain electrode, and the gate wiring, and simultaneously forming an amorphous silicon layer, a second conductive metal layer, and a gate. Etching the insulating layer to form an island-type metal layer, which is a storage electrode formed on a portion of the gate wiring defining the valley pattern and the pixel region; And depositing and patterning a transparent conductive metal on the substrate having the protective layer patterned thereon, the pixel electrode being in lateral contact with the drain electrode and configured on the pixel area and in contact with the side of the storage electrode.

The first conductive metal layer and the second conductive metal layer is one selected from the group of conductive metals including aluminum, aluminum alloy, molybdenum, tungsten and the like.

The gate insulating layer and the protective layer may be selected from an inorganic insulating material group including silicon nitride and silicon oxide, and an organic insulating material group including benzocyclobutene and acrylic resin.

The pixel electrode may be one selected from a group of transparent conductive metals including ITO and IZO.

Hereinafter, exemplary embodiments of the present invention will be described with reference to the accompanying drawings.

Example

According to an embodiment of the present invention, by using a method of forming a pattern defining a distance between the data line and the pixel electrode in advance, it is possible to prevent a short circuit defect due to foreign matter that may flow in the process of patterning the pixel electrode. The distance between the pixel electrode and the data wiring can be kept constant due to the self-alignment effect of the pixel electrode.

4 is a plan view showing some pixels of an array substrate for a liquid crystal display according to the present invention.

As shown in the drawing, the array substrate for a liquid crystal display device according to the present invention comprises a gate wiring and a data wiring crossing each other, and a thin film transistor T as a switching element at the intersection of the two wirings.

The thin film transistor T includes a gate electrode 126, an active channel 29 ′, a source electrode 128, and a drain electrode 130.

The gate wiring 113 and the data wiring 115 intersect to define the pixel region P, and the pixel electrode 117 is formed on the pixel region.

In this case, the bone pattern 114 is formed between the pixel electrode 117 and the data wiring 115, and the predefined bone pattern is formed so as to vertically pattern the side surface of the pixel electrode 117. The short circuit defect between the gate wirings 115 can be prevented, and since the self alignment of the pixel electrodes is performed by the valley pattern, the gap between the pixel electrodes 117 and the data wirings 117 can be kept constant. Can be.

Hereinafter, a method of manufacturing an array substrate for a liquid crystal display device according to the present invention will be described with reference to FIGS. 5A to 5D.

Hereinafter, a method of manufacturing an array substrate for a liquid crystal display device according to an exemplary embodiment of the present invention will be described with reference to FIGS. 5A to 5D.

5A through 5D are cross-sectional views taken along the process plan of FIG. 4 and taken along the line V-V of the plan view.

FIG. 5A illustrates a first mask process step of forming a gate electrode and a gate wiring, and includes aluminum (Al), aluminum alloy (AlNd), chromium (Cr), molybdenum (Mo), tungsten (W), and the like on the substrate 122. A gate wiring (115 of FIG. 4) having a predetermined area of a gate pad (not shown) is formed at the end by using a first conductive metal layer selected from the group of the conductive metals included therein, and protrudes in one direction from the gate wiring 113. The formed gate electrode 126 is formed.

A portion of the gate wiring 113 is used as the storage first electrode 113 ′.

The gate insulating film 127, the pure amorphous silicon layer 129, the impurity amorphous silicon layer 131, which is the first insulating layer, is formed on the entire surface of the substrate 122 so as to cover the gate electrode 126 and the like. The second conductive metal layer 128 'selected from the conductive metal groups is stacked in this order.

Here, the second metal layer 128 ′ is preferably a metal such as molybdenum (Mo) capable of dry etching.

5B is a step of patterning an active channel to pattern the second conductive metal layer to expose the impurity amorphous silicon layer 131 that is part of the active layer 129 on the gate electrode 126.

At the same time, the second conductive metal layer 133 is etched by the width and length between the pixel electrode 117 of FIG. 4 and the data wiring 115 of FIG. 4 to form a bone pattern 141.

Next, using the patterned second conductive metal layer 133 as a mask, the amorphous silicon layer 131 containing the impurities exposed below is etched.

Next, inorganic insulating materials such as silicon nitride (SiN X ), silicon oxide (SiO 2 ), and benzocyclobutene (BCB) and acryl (Acryl) -based materials are formed on the entire surface of the substrate 122 on which the patterned second conductive metal layer is formed. The protective layer 133, which is a second insulating layer, is formed by depositing or applying an organic insulating material including a resin or the like.

FIG. 5C is a third mask step for patterning the protective layer, and is a process of patterning the shapes of the data line 115, the source electrode 128, and the drain electrode 130 as designed.

In this case, the protective layer / second conductive metal layer / semiconductor layer (pure amorphous silicon, impurity amorphous silicon) is etched in the pixel region including the pixel electrode 117 of FIG. 4 to expose the gate insulating layer 127 thereunder. .

On the other hand, the valley pattern 141 between the portion where the pixel electrode 117 of FIG. 4 is formed and the data line 115 has an amorphous silicon layer / second conductive metal layer / gate insulating film etched thereon to form a substrate (below the substrate). 122) is formed by exposure.

In this process, the data line 115 and the drain electrode 130 are vertically etched to form a structure in which side surfaces thereof are exposed.

Next, FIG. 5D is a step of exposing the pixel electrode, and description starts from the photoresist process omitted for each mask process of FIGS. 5A to 5C.

As described above, after the data line 115, the source electrode 128, the drain electrode 130, and the valley pattern 141 are formed in the process of patterning the protective layer 133, indium-tin-oxide (indium— Transparent conductive metals such as tin-oxide (ITO) and indium-zinc-oxide (IZO) are deposited to form a transparent electrode layer 117`.

Next, a PR layer 143 is formed by applying photoresist on the substrate 122 on which the transparent electrode layer 117 ′ is formed.

In this case, since the photoresist has a viscosity to some extent, since the photoresist flows to the end of the bone pattern, the transparent electrode layer remains at the end of the bone pattern 114 after etching the transparent electrode layer 117 ′. do.

That is, the step of the photoresist layer formed on one side step portion of the valley pattern is applied to form a hill compared to the other part.

Therefore, the residual PR remains in the stepped portion of the bone pattern during the stripping process of the photoresist. Thus, the lower transparent electrode layer remains.

5E illustrates a fourth mask step of forming a pixel electrode, exposing the photoresist, and etching the lower transparent electrode layer (143 of FIG. 5E) of the exposed photoresist (143 of FIG. 5E) to form the drain electrode 128. ) And the pixel electrode 117 is formed so as to be formed on the pixel region P while being in side contact.

Since the end line 117 ′ of the transparent conductive metal comes at intervals between the valley patterns 114 formed in the conductive second metal layer and the protective layer pattern process, even if a slight misalignment occurs, the gap between the pixel electrode and the data wiring is maintained. It is defined at intervals of the bone pattern 114.

Therefore, the C dp component, which is a capacitor generated between the pixel electrode 117 and the data wiring 115, can be kept constant.

FIG. 6 is a cross-sectional view illustrating a plan view of the enlarged view of FIG. 5E and a cross section thereof. FIG. (When the protruding pattern of the pixel electrode due to the foreign matter is formed in the data wiring direction during the pattern process of the pixel electrode)

As illustrated, even when the pixel electrode is protruded to be close to the data wiring by a foreign material during the photoresist process for patterning the pixel electrode 117, the short circuit defect between the data wiring and the pixel electrode 117 is not affected. This can be prevented by preventing the pixel electrode 117 and the data wiring 115 from being formed on the same plane by the step of the valley pattern 114.

In the same manner as described above, an array substrate for a liquid crystal display device according to the present invention can be manufactured.

Therefore, according to the present invention, since a valley pattern is formed between the data line and the pixel electrode, even if a slight misalignment occurs in the pixel electrode and the data line, a capacitor component generated between the data line and the pixel electrode is generated. Since it can be kept constant, there is an effect that a poor image quality does not occur.

In addition, the short pattern between the pixel electrode and the data wiring can be prevented by the valley pattern, thereby improving the product yield of the liquid crystal display device.

Claims (7)

  1. A transparent substrate;
    A gate electrode and a gate wiring formed by patterning a first metal layer on the substrate;
    An active layer formed on the gate electrode with an insulating layer interposed therebetween;
    A source wiring overlapping one side of the active layer formed by patterning a second metal layer, a drain electrode spaced apart from the predetermined gap, and a gate wiring and an insulating layer intersecting each other to define a pixel region;
    A bone pattern composed of a predetermined width and length on both sides of the data line passing through the pixel region, and having a lower substrate exposed;
    A pixel electrode formed on the pixel area and spaced apart from the data line with the valley pattern therebetween;
    Array substrate for liquid crystal display device.
  2. The method of claim 1,
    And the first metal layer and the second metal layer are one selected from a group of conductive metals including aluminum (Al), aluminum alloy, molybdenum (Mo), tungsten (W), and the like.
  3. The method of claim 1,
    And the pixel electrode is one selected from a group of transparent conductive metals including ITO and IZO.
  4. Providing a substrate;
    Depositing and patterning a first conductive metal on the substrate to form a gate electrode and a gate wiring;
    Stacking a gate insulating layer, an amorphous silicon layer, an impurity amorphous silicon, and a second conductive metal layer on an entire surface of the substrate on which the first conductive metal layer is patterned;
    Patterning the second conductive metal layer to expose a valley pattern between the active channel and the data line to be formed later and the pixel electrode;
    Depositing an insulating material on the substrate on which the second conductive metal layer is patterned to form a protective layer;
    The protective layer, the second conductive metal layer, and the pure amorphous silicon layer are etched to form a data line defining a pixel region by crossing the source electrode, the drain electrode, and the gate wiring, and simultaneously forming an amorphous silicon layer, a second conductive metal layer, and a gate. Etching the insulating layer to form an island-type metal layer, which is a storage electrode formed on a portion of the gate wiring defining the valley pattern and the pixel region;
    Depositing and patterning a transparent conductive metal on the substrate having the protective layer patterned thereon, the pixel electrode being in side contact with the drain electrode and formed on the pixel area and in contact with the side of the storage electrode
    Array substrate manufacturing method for a liquid crystal display device comprising a.
  5. The method of claim 4, wherein
    And the first conductive metal layer and the second conductive metal layer are one selected from a group of conductive metals including aluminum, aluminum alloy, molybdenum, tungsten, and the like.
  6. The method of claim 4, wherein
    And the gate insulating layer and the protective layer are selected from an inorganic insulating material group including silicon nitride and silicon oxide, and an organic insulating material group including benzocyclobutene, acrylic resin, and the like.
  7. The method of claim 4, wherein
    And the pixel electrode is one selected from a group of transparent conductive metals including ITO and IZO.
KR1020000043483A 2000-07-27 2000-07-27 Array substrate for Liquid crystal display and method for fabricating thereof KR20020010199A (en)

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Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR101539354B1 (en) * 2008-09-02 2015-07-29 삼성디스플레이 주식회사 Liquid crystal display device

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR101539354B1 (en) * 2008-09-02 2015-07-29 삼성디스플레이 주식회사 Liquid crystal display device

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